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cmd/internal/obj: delete all Pconv, replace with Prog.String
Remove the per-achitecture formatter for Prog and replace it with a global String method. Clean up and regularize the output. Update tests affected by the format; some tests are made correct now when they were broken before (and known to be). Also, related: Change the encoding of the (R1+R2) syntax on ppc64 to be equivalent to (R1)(R2*1), which means it needs no special handling. Delete the now unused STRINGSZ constant. Change-Id: I7f6654d11f80065f3914a3f19353f2f12edfe310 Reviewed-on: https://go-review.googlesource.com/6931 Reviewed-by: Russ Cox <rsc@golang.org>
This commit is contained in:
Rob Pike
parent
d5b5d6702a
commit
24a43e6a75
@ -81,7 +81,6 @@ func jumpX86(word string) bool {
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func archX86(linkArch *obj.LinkArch) *Arch {
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register := make(map[string]int16)
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// Create maps for easy lookup of instruction names etc.
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// TODO: Should this be done in obj for us?
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for i, s := range x86.Register {
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register[s] = int16(i + x86.REG_AL)
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}
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@ -154,9 +153,7 @@ func archX86(linkArch *obj.LinkArch) *Arch {
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func archArm() *Arch {
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register := make(map[string]int16)
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// Create maps for easy lookup of instruction names etc.
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// TODO: Should this be done in obj for us?
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// Note that there is no list of names as there is for x86.
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// TODO: Are there aliases we need to add?
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for i := arm.REG_R0; i < arm.REG_SPSR; i++ {
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register[obj.Rconv(i)] = int16(i)
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}
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@ -203,7 +200,6 @@ func archArm() *Arch {
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func archPPC64() *Arch {
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register := make(map[string]int16)
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// Create maps for easy lookup of instruction names etc.
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// TODO: Should this be done in obj for us?
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// Note that there is no list of names as there is for x86.
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for i := ppc64.REG_R0; i <= ppc64.REG_R31; i++ {
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register[obj.Rconv(i)] = int16(i)
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@ -460,21 +460,6 @@ func (p *Parser) asmInstruction(op int, cond string, a []obj.Addr) {
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}
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prog.From = a[0]
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prog.To = a[1]
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switch p.arch.Thechar {
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case '9':
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var reg0, reg1 int16
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// Handle (R1+R2)
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if a[0].Scale != 0 {
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reg0 = int16(a[0].Scale)
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prog.Reg = reg0
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} else if a[1].Scale != 0 {
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reg1 = int16(a[1].Scale)
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prog.Reg = reg1
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}
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if reg0 != 0 && reg1 != 0 {
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p.errorf("register pair cannot be both left and right operands")
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}
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}
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case 3:
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switch p.arch.Thechar {
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case '5':
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@ -59,18 +59,6 @@ func TestARMOperandParser(t *testing.T) {
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func TestPPC64OperandParser(t *testing.T) {
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parser := newParser("ppc64")
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testOperandParser(t, parser, ppc64OperandTests)
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// Special encoding for (R1+R2).
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parser.start(lex.Tokenize("(R1+R2)"))
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addr := obj.Addr{}
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parser.operand(&addr)
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want := obj.Addr{
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Type: obj.TYPE_MEM,
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Reg: parser.arch.Register["R1"],
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Scale: parser.arch.Register["R2"], // TODO: clean up how this is encoded in parse.go
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}
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if want != addr {
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t.Errorf("(R1+R2): expected %+v got %+v", want, addr)
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}
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}
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type operandTest struct {
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@ -321,6 +309,8 @@ var ppc64OperandTests = []operandTest{
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{"(R3)", "(R3)"},
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{"(R4)", "(R4)"},
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{"(R5)", "(R5)"},
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{"(R5)(R6*1)", "(R5)(R6*1)"},
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{"(R5+R6)", "(R5)(R6*1)"}, // Old syntax.
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{"-1(R4)", "-1(R4)"},
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{"-1(R5)", "-1(R5)"},
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{"6(PC)", "6(PC)"},
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@ -646,9 +646,9 @@ func (p *Parser) registerIndirect(a *obj.Addr, prefix rune) {
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p.errorf("illegal address mode for register pair")
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return
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}
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// TODO: This is rewritten in asm. Clumsy.
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a.Type = obj.TYPE_MEM
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a.Scale = r2
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a.Scale = 1
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a.Index = r2
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// Nothing may follow.
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return
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}
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106
src/cmd/asm/internal/asm/testdata/arm.out
vendored
106
src/cmd/asm/internal/asm/testdata/arm.out
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@ -1,53 +1,53 @@
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5 00001 (testdata/arm.s:5) TEXT foo(SB),0,$0
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14 00002 (testdata/arm.s:14) ADD $1,R2,R3
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15 00003 (testdata/arm.s:15) ADD R1<<R2,R3,R4
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16 00004 (testdata/arm.s:16) ADD R1>>R2,R3,R4
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17 00005 (testdata/arm.s:17) ADD R1@>R2,R3,R4
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18 00006 (testdata/arm.s:18) ADD R1->R2,R3,R4
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19 00007 (testdata/arm.s:19) ADD R1,R2,R3
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20 00008 (testdata/arm.s:20) ADD R1<<R2,R3,R4
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30 00009 (testdata/arm.s:30) ADD $1,R2
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31 00010 (testdata/arm.s:31) ADD R1<<R2,R3
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32 00011 (testdata/arm.s:32) ADD R1>>R2,R3
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33 00012 (testdata/arm.s:33) ADD R1@>R2,R3
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34 00013 (testdata/arm.s:34) ADD R1->R2,R3
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35 00014 (testdata/arm.s:35) ADD R1,R2
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44 00015 (testdata/arm.s:44) CLZ.S R1,R2
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53 00016 (testdata/arm.s:53) MOVW.S R1,R2
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54 00017 (testdata/arm.s:54) MOVW.S $1,R2
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55 00018 (testdata/arm.s:55) MOVW.S R1<<R2,R3
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64 00019 (testdata/arm.s:64) JMP.S ,20(PC)
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70 00020 (testdata/arm.s:70) JMP.S ,(R2)
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71 00021 (testdata/arm.s:71) JMP.S ,foo(SB)
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72 00022 (testdata/arm.s:72) JMP.S ,bar<>(SB)
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81 00023 (testdata/arm.s:81) BX (R2),
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90 00024 (testdata/arm.s:90) BEQ ,25(PC)
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99 00025 (testdata/arm.s:99) SWI.S ,R1
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100 00026 (testdata/arm.s:100) SWI.S ,(R1)
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101 00027 (testdata/arm.s:101) SWI.S ,foo(SB)
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110 00028 (testdata/arm.s:110) CMP.S $1,R2,
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111 00029 (testdata/arm.s:111) CMP.S R1<<R2,R3,
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112 00030 (testdata/arm.s:112) CMP.S R1,R2,
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126 00031 (testdata/arm.s:126) MOVM (R1),[R2,R5,R8,g]
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127 00032 (testdata/arm.s:127) MOVM (R1),[R2,R3,R4,R5]
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128 00033 (testdata/arm.s:128) MOVM.S (R1),[R2]
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139 00034 (testdata/arm.s:139) MOVM [R2,R5,R8,g],(R1)
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140 00035 (testdata/arm.s:140) MOVM [R2,R3,R4,R5],(R1)
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141 00036 (testdata/arm.s:141) MOVM.S [R2],(R1)
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150 00037 (testdata/arm.s:150) STREX.S (R2),R1,R3
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156 00038 (testdata/arm.s:156) STREX.S (R2),R1,R1
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162 00039 (testdata/arm.s:162) STREX.S (R2),R3,R3
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170 00040 (testdata/arm.s:170) CASE.S R1,
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179 00041 (testdata/arm.s:179) WORD ,$1234
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188 00042 (testdata/arm.s:188) ABSF.S F1,F2
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194 00043 (testdata/arm.s:194) ADDD.S F1,F2
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195 00044 (testdata/arm.s:195) ADDD.S $(0.5),F2
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201 00045 (testdata/arm.s:201) ADDD.S F1,F2,F3
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202 00046 (testdata/arm.s:202) ADDD.S $(0.5),F2,F3
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208 00047 (testdata/arm.s:208) CMPD.S F1,F2
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242 00048 (testdata/arm.s:242) MULL R1,R2,(R3, R4)
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254 00049 (testdata/arm.s:254) MULAWT R1,R2,R3, R4
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262 00050 (testdata/arm.s:262) PLD (R1),
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263 00051 (testdata/arm.s:263) PLD 4(R1),
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272 00052 (testdata/arm.s:272) RET ,
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281 00053 (testdata/arm.s:281) END ,
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5 00001 (testdata/arm.s:5) TEXT foo(SB), 0, $0
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14 00002 (testdata/arm.s:14) ADD $1, R2, R3
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15 00003 (testdata/arm.s:15) ADD R1<<R2, R3, R4
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16 00004 (testdata/arm.s:16) ADD R1>>R2, R3, R4
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17 00005 (testdata/arm.s:17) ADD R1@>R2, R3, R4
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18 00006 (testdata/arm.s:18) ADD R1->R2, R3, R4
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19 00007 (testdata/arm.s:19) ADD R1, R2, R3
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20 00008 (testdata/arm.s:20) ADD R1<<R2, R3, R4
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30 00009 (testdata/arm.s:30) ADD $1, R2
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31 00010 (testdata/arm.s:31) ADD R1<<R2, R3
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32 00011 (testdata/arm.s:32) ADD R1>>R2, R3
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33 00012 (testdata/arm.s:33) ADD R1@>R2, R3
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34 00013 (testdata/arm.s:34) ADD R1->R2, R3
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35 00014 (testdata/arm.s:35) ADD R1, R2
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44 00015 (testdata/arm.s:44) CLZ.S R1, R2
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53 00016 (testdata/arm.s:53) MOVW.S R1, R2
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54 00017 (testdata/arm.s:54) MOVW.S $1, R2
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55 00018 (testdata/arm.s:55) MOVW.S R1<<R2, R3
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64 00019 (testdata/arm.s:64) JMP.S 20(PC)
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70 00020 (testdata/arm.s:70) JMP.S (R2)
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71 00021 (testdata/arm.s:71) JMP.S foo(SB)
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72 00022 (testdata/arm.s:72) JMP.S bar<>(SB)
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81 00023 (testdata/arm.s:81) BX (R2)
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90 00024 (testdata/arm.s:90) BEQ 25(PC)
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99 00025 (testdata/arm.s:99) SWI.S R1
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100 00026 (testdata/arm.s:100) SWI.S (R1)
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101 00027 (testdata/arm.s:101) SWI.S foo(SB)
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110 00028 (testdata/arm.s:110) CMP.S $1, R2
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111 00029 (testdata/arm.s:111) CMP.S R1<<R2, R3
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112 00030 (testdata/arm.s:112) CMP.S R1, R2
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126 00031 (testdata/arm.s:126) MOVM (R1), [R2,R5,R8,g]
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127 00032 (testdata/arm.s:127) MOVM (R1), [R2,R3,R4,R5]
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128 00033 (testdata/arm.s:128) MOVM.S (R1), [R2]
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139 00034 (testdata/arm.s:139) MOVM [R2,R5,R8,g], (R1)
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140 00035 (testdata/arm.s:140) MOVM [R2,R3,R4,R5], (R1)
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141 00036 (testdata/arm.s:141) MOVM.S [R2], (R1)
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150 00037 (testdata/arm.s:150) STREX.S (R2), R1, R3
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156 00038 (testdata/arm.s:156) STREX.S (R2), R1, R1
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162 00039 (testdata/arm.s:162) STREX.S (R2), R3, R3
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170 00040 (testdata/arm.s:170) CASE.S R1
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179 00041 (testdata/arm.s:179) WORD $1234
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188 00042 (testdata/arm.s:188) ABSF.S F1, F2
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194 00043 (testdata/arm.s:194) ADDD.S F1, F2
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195 00044 (testdata/arm.s:195) ADDD.S $(0.5), F2
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201 00045 (testdata/arm.s:201) ADDD.S F1, F2, F3
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202 00046 (testdata/arm.s:202) ADDD.S $(0.5), F2, F3
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208 00047 (testdata/arm.s:208) CMPD.S F1, F2
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242 00048 (testdata/arm.s:242) MULL R1, R2, (R3, R4)
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254 00049 (testdata/arm.s:254) MULAWT R1, R2, R3, R4
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262 00050 (testdata/arm.s:262) PLD (R1)
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263 00051 (testdata/arm.s:263) PLD 4(R1)
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272 00052 (testdata/arm.s:272) RET
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281 00053 (testdata/arm.s:281) END
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220
src/cmd/asm/internal/asm/testdata/ppc64.out
vendored
220
src/cmd/asm/internal/asm/testdata/ppc64.out
vendored
@ -1,110 +1,110 @@
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5 00001 (testdata/ppc64.s:5) TEXT foo(SB),$0
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15 00002 (testdata/ppc64.s:15) MOVW R1,R2
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21 00003 (testdata/ppc64.s:21) MOVW foo<>+3(SB),R2
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22 00004 (testdata/ppc64.s:22) MOVW 16(R1),R2
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28 00005 (testdata/ppc64.s:28) MOVW (R1),R2
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29 00006 (testdata/ppc64.s:29) MOVW (R1+R2),R3
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35 00007 (testdata/ppc64.s:35) MOVW R1,R2
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41 00008 (testdata/ppc64.s:41) MOVB foo<>+3(SB),R2
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42 00009 (testdata/ppc64.s:42) MOVB 16(R1),R2
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48 00010 (testdata/ppc64.s:48) MOVB (R1),R2
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49 00011 (testdata/ppc64.s:49) MOVB (R1+R2),R3
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58 00012 (testdata/ppc64.s:58) FMOVD foo<>+3(SB),F2
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59 00013 (testdata/ppc64.s:59) FMOVD 16(R1),F2
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65 00014 (testdata/ppc64.s:65) FMOVD (R1),F2
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71 00015 (testdata/ppc64.s:71) FMOVD $(0.10000000000000001),F2
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77 00016 (testdata/ppc64.s:77) FMOVD F1,F2
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83 00017 (testdata/ppc64.s:83) FMOVD F2,foo<>+3(SB)
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84 00018 (testdata/ppc64.s:84) FMOVD F2,16(R1)
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90 00019 (testdata/ppc64.s:90) FMOVD F2,(R1)
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99 00020 (testdata/ppc64.s:99) MOVW R1,foo<>+3(SB)
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100 00021 (testdata/ppc64.s:100) MOVW R1,16(R2)
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106 00022 (testdata/ppc64.s:106) MOVW R1,(R1)
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107 00023 (testdata/ppc64.s:107) MOVW R1,(R2+R3)
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113 00024 (testdata/ppc64.s:113) MOVB R1,foo<>+3(SB)
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114 00025 (testdata/ppc64.s:114) MOVB R1,16(R2)
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120 00026 (testdata/ppc64.s:120) MOVB R1,(R1)
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121 00027 (testdata/ppc64.s:121) MOVB R1,(R2+R3)
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129 00028 (testdata/ppc64.s:129) FMOVD F1,foo<>+3(SB)
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130 00029 (testdata/ppc64.s:130) FMOVD F1,16(R2)
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136 00030 (testdata/ppc64.s:136) FMOVD F1,(R1)
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145 00031 (testdata/ppc64.s:145) MOVFL FPSCR,F1
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151 00032 (testdata/ppc64.s:151) MOVFL F1,FPSCR
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157 00033 (testdata/ppc64.s:157) MOVFL F1,$4,FPSCR
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163 00034 (testdata/ppc64.s:163) MOVFL FPSCR,CR0
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184 00035 (testdata/ppc64.s:184) MOVW R1,CR1
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190 00036 (testdata/ppc64.s:190) MOVW R1,CR
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202 00037 (testdata/ppc64.s:202) ADD R1,R2,R3
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208 00038 (testdata/ppc64.s:208) ADD $1,R2,R3
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220 00039 (testdata/ppc64.s:220) ADD R1,R2
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226 00040 (testdata/ppc64.s:226) ADD $4,R1
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232 00041 (testdata/ppc64.s:232) ADDE R1,R2,R3
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238 00042 (testdata/ppc64.s:238) ADDE R1,R2
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244 00043 (testdata/ppc64.s:244) SLW R1,R2,R3
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250 00044 (testdata/ppc64.s:250) SLW R1,R2
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256 00045 (testdata/ppc64.s:256) SLW $4,R1,R2
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262 00046 (testdata/ppc64.s:262) SLW $4,R1
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268 00047 (testdata/ppc64.s:268) SLW $4,R1
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274 00048 (testdata/ppc64.s:274) SUBME R1,R1
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292 00049 (testdata/ppc64.s:292) MOVW $1,R1
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298 00050 (testdata/ppc64.s:298) MOVW $1,R1
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299 00051 (testdata/ppc64.s:299) MOVW $foo(SB),R1
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323 00052 (testdata/ppc64.s:323) MOVFL CR0,CR1
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335 00053 (testdata/ppc64.s:335) MOVW CR,R1
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341 00054 (testdata/ppc64.s:341) MOVW SPR(0),R1
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342 00055 (testdata/ppc64.s:342) MOVW SPR(7),R1
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348 00056 (testdata/ppc64.s:348) MOVW LR,R1
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349 00057 (testdata/ppc64.s:349) MOVW CTR,R1
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355 00058 (testdata/ppc64.s:355) MOVW R1,LR
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356 00059 (testdata/ppc64.s:356) MOVW R1,CTR
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368 00060 (testdata/ppc64.s:368) MOVW R1,SPR(7)
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380 00061 (testdata/ppc64.s:380) JMP ,62(PC)
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381 00062 (testdata/ppc64.s:381) JMP ,61
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387 00063 (testdata/ppc64.s:387) JMP ,4(R1)
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388 00064 (testdata/ppc64.s:388) JMP ,foo(SB)
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394 00065 (testdata/ppc64.s:394) JMP ,CTR
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413 00066 (testdata/ppc64.s:413) BEQ CR1,67(PC)
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414 00067 (testdata/ppc64.s:414) BEQ CR1,66
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440 00068 (testdata/ppc64.s:440) BC 4,CTR
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450 00069 (testdata/ppc64.s:450) BC $3,R4,66
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470 00070 (testdata/ppc64.s:470) BC $3,R3,LR
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500 00071 (testdata/ppc64.s:500) FABS F1,F2
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506 00072 (testdata/ppc64.s:506) FADD F1,F2
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512 00073 (testdata/ppc64.s:512) FADD F1,F2,F3
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518 00074 (testdata/ppc64.s:518) FMADD F1,F2,F3,F4
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524 00075 (testdata/ppc64.s:524) FCMPU F1,F2
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530 00076 (testdata/ppc64.s:530) FCMPU F1,F2,CR0
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539 00077 (testdata/ppc64.s:539) CMP R1,R2
|
||||
545 00078 (testdata/ppc64.s:545) CMP R1,$4
|
||||
551 00079 (testdata/ppc64.s:551) CMP R1,CR0,R2
|
||||
557 00080 (testdata/ppc64.s:557) CMP R1,CR0,$4
|
||||
566 00081 (testdata/ppc64.s:566) RLDC $4,R1,$5,R2
|
||||
572 00082 (testdata/ppc64.s:572) RLDC $26,R1,$201326592,R2
|
||||
578 00083 (testdata/ppc64.s:578) RLDC R1,R2,$4,R3
|
||||
584 00084 (testdata/ppc64.s:584) RLWMI R1,R2,$201326592,R3
|
||||
593 00085 (testdata/ppc64.s:593) MOVMW foo(SB),R2
|
||||
594 00086 (testdata/ppc64.s:594) MOVMW 4(R1),R2
|
||||
600 00087 (testdata/ppc64.s:600) MOVMW R1,foo(SB)
|
||||
601 00088 (testdata/ppc64.s:601) MOVMW R1,4(R2)
|
||||
611 00089 (testdata/ppc64.s:611) LSW (R1),R2
|
||||
612 00090 (testdata/ppc64.s:612) LSW (R1+R2),R3
|
||||
618 00091 (testdata/ppc64.s:618) LSW (R1+NONE),R2
|
||||
619 00092 (testdata/ppc64.s:619) LSW (R1+NONE),R3
|
||||
625 00093 (testdata/ppc64.s:625) STSW R1,(R2)
|
||||
626 00094 (testdata/ppc64.s:626) STSW R1,(R2+R3)
|
||||
632 00095 (testdata/ppc64.s:632) STSW R1,(R2+NONE)
|
||||
633 00096 (testdata/ppc64.s:633) STSW R1,(R2+NONE)
|
||||
639 00097 (testdata/ppc64.s:639) MOVHBR (R1),R2
|
||||
640 00098 (testdata/ppc64.s:640) MOVHBR (R1+R2),R3
|
||||
646 00099 (testdata/ppc64.s:646) MOVHBR R1,(R2)
|
||||
647 00100 (testdata/ppc64.s:647) MOVHBR R1,(R2+R3)
|
||||
653 00101 (testdata/ppc64.s:653) DCBF (R1),
|
||||
654 00102 (testdata/ppc64.s:654) DCBF (R1),
|
||||
663 00103 (testdata/ppc64.s:663) NOP ,
|
||||
669 00104 (testdata/ppc64.s:669) NOP R2,
|
||||
675 00105 (testdata/ppc64.s:675) NOP F2,
|
||||
681 00106 (testdata/ppc64.s:681) NOP R2,
|
||||
687 00107 (testdata/ppc64.s:687) NOP F2,
|
||||
693 00108 (testdata/ppc64.s:693) NOP $4,
|
||||
701 00109 (testdata/ppc64.s:701) RET ,
|
||||
709 00110 (testdata/ppc64.s:709) END ,
|
||||
5 00001 (testdata/ppc64.s:5) TEXT foo(SB), 0, $0
|
||||
15 00002 (testdata/ppc64.s:15) MOVW R1, R2
|
||||
21 00003 (testdata/ppc64.s:21) MOVW foo<>+3(SB), R2
|
||||
22 00004 (testdata/ppc64.s:22) MOVW 16(R1), R2
|
||||
28 00005 (testdata/ppc64.s:28) MOVW (R1), R2
|
||||
29 00006 (testdata/ppc64.s:29) MOVW (R1)(R2*1), R3
|
||||
35 00007 (testdata/ppc64.s:35) MOVW R1, R2
|
||||
41 00008 (testdata/ppc64.s:41) MOVB foo<>+3(SB), R2
|
||||
42 00009 (testdata/ppc64.s:42) MOVB 16(R1), R2
|
||||
48 00010 (testdata/ppc64.s:48) MOVB (R1), R2
|
||||
49 00011 (testdata/ppc64.s:49) MOVB (R1)(R2*1), R3
|
||||
58 00012 (testdata/ppc64.s:58) FMOVD foo<>+3(SB), F2
|
||||
59 00013 (testdata/ppc64.s:59) FMOVD 16(R1), F2
|
||||
65 00014 (testdata/ppc64.s:65) FMOVD (R1), F2
|
||||
71 00015 (testdata/ppc64.s:71) FMOVD $(0.10000000000000001), F2
|
||||
77 00016 (testdata/ppc64.s:77) FMOVD F1, F2
|
||||
83 00017 (testdata/ppc64.s:83) FMOVD F2, foo<>+3(SB)
|
||||
84 00018 (testdata/ppc64.s:84) FMOVD F2, 16(R1)
|
||||
90 00019 (testdata/ppc64.s:90) FMOVD F2, (R1)
|
||||
99 00020 (testdata/ppc64.s:99) MOVW R1, foo<>+3(SB)
|
||||
100 00021 (testdata/ppc64.s:100) MOVW R1, 16(R2)
|
||||
106 00022 (testdata/ppc64.s:106) MOVW R1, (R1)
|
||||
107 00023 (testdata/ppc64.s:107) MOVW R1, (R2)(R3*1)
|
||||
113 00024 (testdata/ppc64.s:113) MOVB R1, foo<>+3(SB)
|
||||
114 00025 (testdata/ppc64.s:114) MOVB R1, 16(R2)
|
||||
120 00026 (testdata/ppc64.s:120) MOVB R1, (R1)
|
||||
121 00027 (testdata/ppc64.s:121) MOVB R1, (R2)(R3*1)
|
||||
129 00028 (testdata/ppc64.s:129) FMOVD F1, foo<>+3(SB)
|
||||
130 00029 (testdata/ppc64.s:130) FMOVD F1, 16(R2)
|
||||
136 00030 (testdata/ppc64.s:136) FMOVD F1, (R1)
|
||||
145 00031 (testdata/ppc64.s:145) MOVFL FPSCR, F1
|
||||
151 00032 (testdata/ppc64.s:151) MOVFL F1, FPSCR
|
||||
157 00033 (testdata/ppc64.s:157) MOVFL F1, $4, FPSCR
|
||||
163 00034 (testdata/ppc64.s:163) MOVFL FPSCR, CR0
|
||||
184 00035 (testdata/ppc64.s:184) MOVW R1, CR1
|
||||
190 00036 (testdata/ppc64.s:190) MOVW R1, CR
|
||||
202 00037 (testdata/ppc64.s:202) ADD R1, R2, R3
|
||||
208 00038 (testdata/ppc64.s:208) ADD $1, R2, R3
|
||||
220 00039 (testdata/ppc64.s:220) ADD R1, R2
|
||||
226 00040 (testdata/ppc64.s:226) ADD $4, R1
|
||||
232 00041 (testdata/ppc64.s:232) ADDE R1, R2, R3
|
||||
238 00042 (testdata/ppc64.s:238) ADDE R1, R2
|
||||
244 00043 (testdata/ppc64.s:244) SLW R1, R2, R3
|
||||
250 00044 (testdata/ppc64.s:250) SLW R1, R2
|
||||
256 00045 (testdata/ppc64.s:256) SLW $4, R1, R2
|
||||
262 00046 (testdata/ppc64.s:262) SLW $4, R1
|
||||
268 00047 (testdata/ppc64.s:268) SLW $4, R1
|
||||
274 00048 (testdata/ppc64.s:274) SUBME R1, R1
|
||||
292 00049 (testdata/ppc64.s:292) MOVW $1, R1
|
||||
298 00050 (testdata/ppc64.s:298) MOVW $1, R1
|
||||
299 00051 (testdata/ppc64.s:299) MOVW $foo(SB), R1
|
||||
323 00052 (testdata/ppc64.s:323) MOVFL CR0, CR1
|
||||
335 00053 (testdata/ppc64.s:335) MOVW CR, R1
|
||||
341 00054 (testdata/ppc64.s:341) MOVW SPR(0), R1
|
||||
342 00055 (testdata/ppc64.s:342) MOVW SPR(7), R1
|
||||
348 00056 (testdata/ppc64.s:348) MOVW LR, R1
|
||||
349 00057 (testdata/ppc64.s:349) MOVW CTR, R1
|
||||
355 00058 (testdata/ppc64.s:355) MOVW R1, LR
|
||||
356 00059 (testdata/ppc64.s:356) MOVW R1, CTR
|
||||
368 00060 (testdata/ppc64.s:368) MOVW R1, SPR(7)
|
||||
380 00061 (testdata/ppc64.s:380) JMP 62(PC)
|
||||
381 00062 (testdata/ppc64.s:381) JMP 61
|
||||
387 00063 (testdata/ppc64.s:387) JMP 4(R1)
|
||||
388 00064 (testdata/ppc64.s:388) JMP foo(SB)
|
||||
394 00065 (testdata/ppc64.s:394) JMP CTR
|
||||
413 00066 (testdata/ppc64.s:413) BEQ CR1, 67(PC)
|
||||
414 00067 (testdata/ppc64.s:414) BEQ CR1, 66
|
||||
440 00068 (testdata/ppc64.s:440) BC 4, CTR
|
||||
450 00069 (testdata/ppc64.s:450) BC $3, R4, 66
|
||||
470 00070 (testdata/ppc64.s:470) BC $3, R3, LR
|
||||
500 00071 (testdata/ppc64.s:500) FABS F1, F2
|
||||
506 00072 (testdata/ppc64.s:506) FADD F1, F2
|
||||
512 00073 (testdata/ppc64.s:512) FADD F1, F2, F3
|
||||
518 00074 (testdata/ppc64.s:518) FMADD F1, F2, F3, F4
|
||||
524 00075 (testdata/ppc64.s:524) FCMPU F1, F2
|
||||
530 00076 (testdata/ppc64.s:530) FCMPU F1, F2, CR0
|
||||
539 00077 (testdata/ppc64.s:539) CMP R1, R2
|
||||
545 00078 (testdata/ppc64.s:545) CMP R1, $4
|
||||
551 00079 (testdata/ppc64.s:551) CMP R1, CR0, R2
|
||||
557 00080 (testdata/ppc64.s:557) CMP R1, CR0, $4
|
||||
566 00081 (testdata/ppc64.s:566) RLDC $4, R1, $5, R2
|
||||
572 00082 (testdata/ppc64.s:572) RLDC $26, R1, $201326592, R2
|
||||
578 00083 (testdata/ppc64.s:578) RLDC R1, R2, $4, R3
|
||||
584 00084 (testdata/ppc64.s:584) RLWMI R1, R2, $201326592, R3
|
||||
593 00085 (testdata/ppc64.s:593) MOVMW foo(SB), R2
|
||||
594 00086 (testdata/ppc64.s:594) MOVMW 4(R1), R2
|
||||
600 00087 (testdata/ppc64.s:600) MOVMW R1, foo(SB)
|
||||
601 00088 (testdata/ppc64.s:601) MOVMW R1, 4(R2)
|
||||
611 00089 (testdata/ppc64.s:611) LSW (R1), R2
|
||||
612 00090 (testdata/ppc64.s:612) LSW (R1)(R2*1), R3
|
||||
618 00091 (testdata/ppc64.s:618) LSW (R1), $1, R2
|
||||
619 00092 (testdata/ppc64.s:619) LSW (R1)(R2*1), $1, R3
|
||||
625 00093 (testdata/ppc64.s:625) STSW R1, (R2)
|
||||
626 00094 (testdata/ppc64.s:626) STSW R1, (R2)(R3*1)
|
||||
632 00095 (testdata/ppc64.s:632) STSW R1, $1, (R2)
|
||||
633 00096 (testdata/ppc64.s:633) STSW R1, $1, (R2)(R3*1)
|
||||
639 00097 (testdata/ppc64.s:639) MOVHBR (R1), R2
|
||||
640 00098 (testdata/ppc64.s:640) MOVHBR (R1)(R2*1), R3
|
||||
646 00099 (testdata/ppc64.s:646) MOVHBR R1, (R2)
|
||||
647 00100 (testdata/ppc64.s:647) MOVHBR R1, (R2)(R3*1)
|
||||
653 00101 (testdata/ppc64.s:653) DCBF (R1)
|
||||
654 00102 (testdata/ppc64.s:654) DCBF (R1)(R2*1)
|
||||
663 00103 (testdata/ppc64.s:663) NOP
|
||||
669 00104 (testdata/ppc64.s:669) NOP R2
|
||||
675 00105 (testdata/ppc64.s:675) NOP F2
|
||||
681 00106 (testdata/ppc64.s:681) NOP R2
|
||||
687 00107 (testdata/ppc64.s:687) NOP F2
|
||||
693 00108 (testdata/ppc64.s:693) NOP $4
|
||||
701 00109 (testdata/ppc64.s:701) RET
|
||||
709 00110 (testdata/ppc64.s:709) END
|
||||
|
||||
@ -81,7 +81,6 @@ const (
|
||||
EOF = -1
|
||||
IGN = -2
|
||||
NHASH = 503
|
||||
STRINGSZ = 200
|
||||
NMACRO = 10
|
||||
)
|
||||
|
||||
|
||||
@ -20,16 +20,19 @@ import (
|
||||
// or bison will check for its definition and use
|
||||
// a potentially smaller value if it is undefined.
|
||||
const (
|
||||
NHUNK = 50000
|
||||
BUFSIZ = 8192
|
||||
NSYMB = 500
|
||||
NHASH = 1024
|
||||
STRINGSZ = 200
|
||||
MAXALIGN = 7
|
||||
UINF = 100
|
||||
PRIME1 = 3
|
||||
AUNK = 100
|
||||
AMEM = 0 + iota - 9
|
||||
NHUNK = 50000
|
||||
BUFSIZ = 8192
|
||||
NSYMB = 500
|
||||
NHASH = 1024
|
||||
MAXALIGN = 7
|
||||
UINF = 100
|
||||
PRIME1 = 3
|
||||
BADWIDTH = -1000000000
|
||||
MaxStackVarSize = 10 * 1024 * 1024
|
||||
)
|
||||
|
||||
const (
|
||||
AMEM = iota
|
||||
AMEM0
|
||||
AMEM8
|
||||
AMEM16
|
||||
@ -51,8 +54,7 @@ const (
|
||||
AFLOAT64
|
||||
ACPLX64
|
||||
ACPLX128
|
||||
BADWIDTH = -1000000000
|
||||
MaxStackVarSize = 10 * 1024 * 1024
|
||||
AUNK = 100
|
||||
)
|
||||
|
||||
const (
|
||||
|
||||
@ -32,9 +32,6 @@ package arm
|
||||
|
||||
import "cmd/internal/obj"
|
||||
|
||||
// TODO(ality): remove this workaround.
|
||||
// It's here because Pconv in liblink/list?.c references %L.
|
||||
|
||||
const (
|
||||
NSNAME = 8
|
||||
NSYM = 50
|
||||
|
||||
@ -35,67 +35,6 @@ import (
|
||||
"fmt"
|
||||
)
|
||||
|
||||
const (
|
||||
STRINGSZ = 1000
|
||||
)
|
||||
|
||||
var extra = []string{
|
||||
".EQ",
|
||||
".NE",
|
||||
".CS",
|
||||
".CC",
|
||||
".MI",
|
||||
".PL",
|
||||
".VS",
|
||||
".VC",
|
||||
".HI",
|
||||
".LS",
|
||||
".GE",
|
||||
".LT",
|
||||
".GT",
|
||||
".LE",
|
||||
"",
|
||||
".NV",
|
||||
}
|
||||
|
||||
var bigP *obj.Prog
|
||||
|
||||
func Pconv(p *obj.Prog) string {
|
||||
a := int(p.As)
|
||||
s := int(p.Scond)
|
||||
sc := extra[(s&C_SCOND)^C_SCOND_XOR]
|
||||
if s&C_SBIT != 0 {
|
||||
sc += ".S"
|
||||
}
|
||||
if s&C_PBIT != 0 {
|
||||
sc += ".P"
|
||||
}
|
||||
if s&C_WBIT != 0 {
|
||||
sc += ".W"
|
||||
}
|
||||
if s&C_UBIT != 0 { /* ambiguous with FBIT */
|
||||
sc += ".U"
|
||||
}
|
||||
var str string
|
||||
if a == obj.ADATA {
|
||||
str = fmt.Sprintf("%.5d (%v)\t%v\t%v/%d,%v",
|
||||
p.Pc, p.Line(), obj.Aconv(a), obj.Dconv(p, &p.From), p.From3.Offset, obj.Dconv(p, &p.To))
|
||||
} else if p.As == obj.ATEXT {
|
||||
str = fmt.Sprintf("%.5d (%v)\t%v\t%v,%d,%v",
|
||||
p.Pc, p.Line(), obj.Aconv(a), obj.Dconv(p, &p.From), p.From3.Offset, obj.Dconv(p, &p.To))
|
||||
} else if p.Reg == 0 {
|
||||
str = fmt.Sprintf("%.5d (%v)\t%v%s\t%v,%v",
|
||||
p.Pc, p.Line(), obj.Aconv(a), sc, obj.Dconv(p, &p.From), obj.Dconv(p, &p.To))
|
||||
} else {
|
||||
str = fmt.Sprintf("%.5d (%v)\t%v%s\t%v,%v,%v",
|
||||
p.Pc, p.Line(), obj.Aconv(a), sc, obj.Dconv(p, &p.From), Rconv(int(p.Reg)), obj.Dconv(p, &p.To))
|
||||
}
|
||||
|
||||
var fp string
|
||||
fp += str
|
||||
return fp
|
||||
}
|
||||
|
||||
func init() {
|
||||
obj.RegisterRegister(obj.RBaseARM, MAXREG, Rconv)
|
||||
obj.RegisterOpcode(obj.ABaseARM, Anames)
|
||||
|
||||
@ -1045,7 +1045,6 @@ var unaryDst = map[int]bool{
|
||||
|
||||
var Linkarm = obj.LinkArch{
|
||||
ByteOrder: binary.LittleEndian,
|
||||
Pconv: Pconv,
|
||||
Name: "arm",
|
||||
Thechar: '5',
|
||||
Preprocess: preprocess,
|
||||
|
||||
@ -234,7 +234,6 @@ type Plist struct {
|
||||
}
|
||||
|
||||
type LinkArch struct {
|
||||
Pconv func(*Prog) string
|
||||
ByteOrder binary.ByteOrder
|
||||
Name string
|
||||
Thechar int
|
||||
@ -382,7 +381,16 @@ type Pciter struct {
|
||||
// offset = bit mask of registers in list; R0 is low bit.
|
||||
//
|
||||
// reg, reg
|
||||
// TYPE_REGREG2, to be removed.
|
||||
// Register pair for ARM.
|
||||
// TYPE_REGREG2
|
||||
//
|
||||
// (reg+reg)
|
||||
// Register pair for PPC64.
|
||||
// Encoding:
|
||||
// type = TYPE_MEM
|
||||
// reg = first register
|
||||
// index = second register
|
||||
// scale = 1
|
||||
//
|
||||
|
||||
const (
|
||||
|
||||
@ -604,7 +604,7 @@ func aclass(ctxt *obj.Link, a *obj.Addr) int {
|
||||
}
|
||||
return C_LAUTO
|
||||
|
||||
case obj.TYPE_NONE:
|
||||
case obj.NAME_NONE:
|
||||
ctxt.Instoffset = a.Offset
|
||||
if ctxt.Instoffset == 0 {
|
||||
return C_ZOREG
|
||||
@ -1579,11 +1579,11 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) {
|
||||
r = int(o.param)
|
||||
}
|
||||
v := regoff(ctxt, &p.To)
|
||||
if p.To.Type == obj.TYPE_MEM && p.Reg != 0 {
|
||||
if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 {
|
||||
if v != 0 {
|
||||
ctxt.Diag("illegal indexed instruction\n%v", p)
|
||||
}
|
||||
o1 = AOP_RRR(uint32(opstorex(ctxt, int(p.As))), uint32(p.From.Reg), uint32(p.Reg), uint32(r))
|
||||
o1 = AOP_RRR(uint32(opstorex(ctxt, int(p.As))), uint32(p.From.Reg), uint32(p.To.Index), uint32(r))
|
||||
} else {
|
||||
if int32(int16(v)) != v {
|
||||
log.Fatalf("mishandled instruction %v", p)
|
||||
@ -1598,11 +1598,11 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) {
|
||||
r = int(o.param)
|
||||
}
|
||||
v := regoff(ctxt, &p.From)
|
||||
if p.From.Type == obj.TYPE_MEM && p.Reg != 0 {
|
||||
if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 {
|
||||
if v != 0 {
|
||||
ctxt.Diag("illegal indexed instruction\n%v", p)
|
||||
}
|
||||
o1 = AOP_RRR(uint32(oploadx(ctxt, int(p.As))), uint32(p.To.Reg), uint32(p.Reg), uint32(r))
|
||||
o1 = AOP_RRR(uint32(oploadx(ctxt, int(p.As))), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
|
||||
} else {
|
||||
if int32(int16(v)) != v {
|
||||
log.Fatalf("mishandled instruction %v", p)
|
||||
@ -1617,11 +1617,11 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) {
|
||||
r = int(o.param)
|
||||
}
|
||||
v := regoff(ctxt, &p.From)
|
||||
if p.From.Type == obj.TYPE_MEM && p.Reg != 0 {
|
||||
if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 {
|
||||
if v != 0 {
|
||||
ctxt.Diag("illegal indexed instruction\n%v", p)
|
||||
}
|
||||
o1 = AOP_RRR(uint32(oploadx(ctxt, int(p.As))), uint32(p.To.Reg), uint32(p.Reg), uint32(r))
|
||||
o1 = AOP_RRR(uint32(oploadx(ctxt, int(p.As))), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
|
||||
} else {
|
||||
o1 = AOP_IRR(uint32(opload(ctxt, int(p.As))), uint32(p.To.Reg), uint32(r), uint32(v))
|
||||
}
|
||||
@ -1764,16 +1764,12 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) {
|
||||
} else {
|
||||
v = 20 /* unconditional */
|
||||
}
|
||||
r := int(p.Reg)
|
||||
if r == 0 {
|
||||
r = 0
|
||||
}
|
||||
o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11
|
||||
o2 = OPVCC(19, 16, 0, 0)
|
||||
if p.As == ABL || p.As == ABCL {
|
||||
o2 |= 1
|
||||
}
|
||||
o2 = OP_BCR(o2, uint32(v), uint32(r))
|
||||
o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index))
|
||||
|
||||
case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */
|
||||
var v int32
|
||||
@ -2085,28 +2081,13 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) {
|
||||
o1 = AOP_RRR(uint32(opirr(ctxt, int(p.As))), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(regoff(ctxt, &p.From3))&0x7F)<<11
|
||||
|
||||
case 43: /* unary indexed source: dcbf (b); dcbf (a+b) */
|
||||
r := int(p.Reg)
|
||||
|
||||
if r == 0 {
|
||||
r = 0
|
||||
}
|
||||
o1 = AOP_RRR(uint32(oprrr(ctxt, int(p.As))), 0, uint32(r), uint32(p.From.Reg))
|
||||
o1 = AOP_RRR(uint32(oprrr(ctxt, int(p.As))), 0, uint32(p.From.Index), uint32(p.From.Reg))
|
||||
|
||||
case 44: /* indexed store */
|
||||
r := int(p.Reg)
|
||||
|
||||
if r == 0 {
|
||||
r = 0
|
||||
}
|
||||
o1 = AOP_RRR(uint32(opstorex(ctxt, int(p.As))), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
|
||||
o1 = AOP_RRR(uint32(opstorex(ctxt, int(p.As))), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
|
||||
|
||||
case 45: /* indexed load */
|
||||
r := int(p.Reg)
|
||||
|
||||
if r == 0 {
|
||||
r = 0
|
||||
}
|
||||
o1 = AOP_RRR(uint32(oploadx(ctxt, int(p.As))), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
|
||||
o1 = AOP_RRR(uint32(oploadx(ctxt, int(p.As))), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
|
||||
|
||||
case 46: /* plain op */
|
||||
o1 = uint32(oprrr(ctxt, int(p.As)))
|
||||
|
||||
@ -34,85 +34,6 @@ import (
|
||||
"fmt"
|
||||
)
|
||||
|
||||
const (
|
||||
STRINGSZ = 1000
|
||||
)
|
||||
|
||||
//
|
||||
// Format conversions
|
||||
// %A int Opcodes (instruction mnemonics)
|
||||
//
|
||||
// %D Addr* Addresses (instruction operands)
|
||||
//
|
||||
// %P Prog* Instructions
|
||||
//
|
||||
// %R int Registers
|
||||
//
|
||||
// %$ char* String constant addresses (for internal use only)
|
||||
// %^ int C_* classes (for liblink internal use)
|
||||
|
||||
var bigP *obj.Prog
|
||||
|
||||
func Pconv(p *obj.Prog) string {
|
||||
a := int(p.As)
|
||||
|
||||
str := ""
|
||||
if a == obj.ADATA {
|
||||
str = fmt.Sprintf("%.5d (%v)\t%v\t%v/%d,%v",
|
||||
p.Pc, p.Line(), obj.Aconv(a), obj.Dconv(p, &p.From), p.From3.Offset, obj.Dconv(p, &p.To))
|
||||
} else if a == obj.ATEXT || a == obj.AGLOBL {
|
||||
if p.From3.Offset != 0 {
|
||||
str = fmt.Sprintf("%.5d (%v)\t%v\t%v,%d,%v",
|
||||
p.Pc, p.Line(), obj.Aconv(a), obj.Dconv(p, &p.From), p.From3.Offset, obj.Dconv(p, &p.To))
|
||||
} else {
|
||||
str = fmt.Sprintf("%.5d (%v)\t%v\t%v,%v",
|
||||
p.Pc, p.Line(), obj.Aconv(a), obj.Dconv(p, &p.From), obj.Dconv(p, &p.To))
|
||||
}
|
||||
} else {
|
||||
if p.Mark&NOSCHED != 0 {
|
||||
str += fmt.Sprintf("*")
|
||||
}
|
||||
if p.Reg == 0 && p.From3.Type == obj.TYPE_NONE {
|
||||
str += fmt.Sprintf("%.5d (%v)\t%v\t%v,%v",
|
||||
p.Pc, p.Line(), obj.Aconv(a), obj.Dconv(p, &p.From), obj.Dconv(p, &p.To))
|
||||
} else if a != obj.ATEXT && p.From.Type == obj.TYPE_MEM {
|
||||
off := ""
|
||||
if p.From.Offset != 0 {
|
||||
off = fmt.Sprintf("%d", p.From.Offset)
|
||||
}
|
||||
str += fmt.Sprintf("%.5d (%v)\t%v\t%s(%v+%v),%v",
|
||||
p.Pc, p.Line(), obj.Aconv(a), off, Rconv(int(p.From.Reg)), Rconv(int(p.Reg)), obj.Dconv(p, &p.To))
|
||||
} else if p.To.Type == obj.TYPE_MEM {
|
||||
off := ""
|
||||
if p.From.Offset != 0 {
|
||||
off = fmt.Sprintf("%d", p.From.Offset)
|
||||
}
|
||||
str += fmt.Sprintf("%.5d (%v)\t%v\t%v,%s(%v+%v)",
|
||||
p.Pc, p.Line(), obj.Aconv(a), obj.Dconv(p, &p.From), off, Rconv(int(p.To.Reg)), Rconv(int(p.Reg)))
|
||||
} else {
|
||||
str += fmt.Sprintf("%.5d (%v)\t%v\t%v",
|
||||
p.Pc, p.Line(), obj.Aconv(a), obj.Dconv(p, &p.From))
|
||||
if p.Reg != 0 {
|
||||
str += fmt.Sprintf(",%v", Rconv(int(p.Reg)))
|
||||
}
|
||||
if p.From3.Type != obj.TYPE_NONE {
|
||||
str += fmt.Sprintf(",%v", obj.Dconv(p, &p.From3))
|
||||
}
|
||||
str += fmt.Sprintf(",%v", obj.Dconv(p, &p.To))
|
||||
}
|
||||
|
||||
if p.Spadj != 0 {
|
||||
var fp string
|
||||
fp += fmt.Sprintf("%s # spadj=%d", str, p.Spadj)
|
||||
return fp
|
||||
}
|
||||
}
|
||||
|
||||
var fp string
|
||||
fp += str
|
||||
return fp
|
||||
}
|
||||
|
||||
func init() {
|
||||
obj.RegisterRegister(obj.RBasePPC64, REG_DCR0+1024, Rconv)
|
||||
obj.RegisterOpcode(obj.ABasePPC64, Anames)
|
||||
|
||||
@ -949,7 +949,6 @@ loop:
|
||||
|
||||
var Linkppc64 = obj.LinkArch{
|
||||
ByteOrder: binary.BigEndian,
|
||||
Pconv: Pconv,
|
||||
Name: "ppc64",
|
||||
Thechar: '9',
|
||||
Preprocess: preprocess,
|
||||
@ -963,7 +962,6 @@ var Linkppc64 = obj.LinkArch{
|
||||
|
||||
var Linkppc64le = obj.LinkArch{
|
||||
ByteOrder: binary.LittleEndian,
|
||||
Pconv: Pconv,
|
||||
Name: "ppc64le",
|
||||
Thechar: '9',
|
||||
Preprocess: preprocess,
|
||||
|
||||
@ -6,6 +6,7 @@ package obj
|
||||
|
||||
import (
|
||||
"bufio"
|
||||
"bytes"
|
||||
"fmt"
|
||||
"io"
|
||||
"log"
|
||||
@ -248,11 +249,90 @@ func (p *Prog) Line() string {
|
||||
return Linklinefmt(p.Ctxt, int(p.Lineno), false, false)
|
||||
}
|
||||
|
||||
var armCondCode = []string{
|
||||
".EQ",
|
||||
".NE",
|
||||
".CS",
|
||||
".CC",
|
||||
".MI",
|
||||
".PL",
|
||||
".VS",
|
||||
".VC",
|
||||
".HI",
|
||||
".LS",
|
||||
".GE",
|
||||
".LT",
|
||||
".GT",
|
||||
".LE",
|
||||
"",
|
||||
".NV",
|
||||
}
|
||||
|
||||
/* ARM scond byte */
|
||||
const (
|
||||
C_SCOND = (1 << 4) - 1
|
||||
C_SBIT = 1 << 4
|
||||
C_PBIT = 1 << 5
|
||||
C_WBIT = 1 << 6
|
||||
C_FBIT = 1 << 7
|
||||
C_UBIT = 1 << 7
|
||||
C_SCOND_XOR = 14
|
||||
)
|
||||
|
||||
// CConv formats ARM condition codes.
|
||||
func CConv(s uint8) string {
|
||||
if s == 0 {
|
||||
return ""
|
||||
}
|
||||
sc := armCondCode[(s&C_SCOND)^C_SCOND_XOR]
|
||||
if s&C_SBIT != 0 {
|
||||
sc += ".S"
|
||||
}
|
||||
if s&C_PBIT != 0 {
|
||||
sc += ".P"
|
||||
}
|
||||
if s&C_WBIT != 0 {
|
||||
sc += ".W"
|
||||
}
|
||||
if s&C_UBIT != 0 { /* ambiguous with FBIT */
|
||||
sc += ".U"
|
||||
}
|
||||
return sc
|
||||
}
|
||||
|
||||
func (p *Prog) String() string {
|
||||
if p.Ctxt == nil {
|
||||
return "<Prog without ctxt>"
|
||||
}
|
||||
return p.Ctxt.Arch.Pconv(p)
|
||||
|
||||
sc := CConv(p.Scond)
|
||||
|
||||
var buf bytes.Buffer
|
||||
|
||||
fmt.Fprintf(&buf, "%.5d (%v)\t%v%s", p.Pc, p.Line(), Aconv(int(p.As)), sc)
|
||||
sep := "\t"
|
||||
if p.From.Type != TYPE_NONE {
|
||||
fmt.Fprintf(&buf, "%s%v", sep, Dconv(p, &p.From))
|
||||
sep = ", "
|
||||
}
|
||||
if p.Reg != REG_NONE {
|
||||
// Should not happen but might as well show it if it does.
|
||||
fmt.Fprintf(&buf, "%s%v", sep, Rconv(int(p.Reg)))
|
||||
sep = ", "
|
||||
}
|
||||
if p.From3.Type != TYPE_NONE {
|
||||
if p.From3.Type == TYPE_CONST && (p.As == ADATA || p.As == ATEXT || p.As == AGLOBL) {
|
||||
// Special case - omit $.
|
||||
fmt.Fprintf(&buf, "%s%d", sep, p.From3.Offset)
|
||||
} else {
|
||||
fmt.Fprintf(&buf, "%s%v", sep, Dconv(p, &p.From3))
|
||||
}
|
||||
sep = ", "
|
||||
}
|
||||
if p.To.Type != TYPE_NONE {
|
||||
fmt.Fprintf(&buf, "%s%v", sep, Dconv(p, &p.To))
|
||||
}
|
||||
return buf.String()
|
||||
}
|
||||
|
||||
func (ctxt *Link) NewProg() *Prog {
|
||||
|
||||
@ -31,58 +31,10 @@
|
||||
package x86
|
||||
|
||||
import (
|
||||
"bytes"
|
||||
"cmd/internal/obj"
|
||||
"fmt"
|
||||
)
|
||||
|
||||
//
|
||||
// Format conversions
|
||||
// %A int Opcodes (instruction mnemonics)
|
||||
//
|
||||
// %D Addr* Addresses (instruction operands)
|
||||
//
|
||||
// %P Prog* Instructions
|
||||
//
|
||||
// %R int Registers
|
||||
//
|
||||
// %$ char* String constant addresses (for internal use only)
|
||||
|
||||
const (
|
||||
STRINGSZ = 1000
|
||||
)
|
||||
|
||||
var bigP *obj.Prog
|
||||
|
||||
func Pconv(p *obj.Prog) string {
|
||||
var buf bytes.Buffer
|
||||
|
||||
fmt.Fprintf(&buf, "%.5d (%v)\t%v", p.Pc, p.Line(), obj.Aconv(int(p.As)))
|
||||
sep := "\t"
|
||||
if p.From.Type != obj.TYPE_NONE {
|
||||
fmt.Fprintf(&buf, "%s%v", sep, obj.Dconv(p, &p.From))
|
||||
sep = ", "
|
||||
}
|
||||
if p.Reg != obj.REG_NONE {
|
||||
// Should not happen but might as well show it if it does.
|
||||
fmt.Fprintf(&buf, "%s%v", sep, obj.Rconv(int(p.Reg)))
|
||||
sep = ", "
|
||||
}
|
||||
if p.From3.Type != obj.TYPE_NONE {
|
||||
if p.From3.Type == obj.TYPE_CONST && (p.As == obj.ADATA || p.As == obj.ATEXT || p.As == obj.AGLOBL) {
|
||||
// Special case - omit $.
|
||||
fmt.Fprintf(&buf, "%s%d", sep, p.From3.Offset)
|
||||
} else {
|
||||
fmt.Fprintf(&buf, "%s%v", sep, obj.Dconv(p, &p.From3))
|
||||
}
|
||||
sep = ", "
|
||||
}
|
||||
if p.To.Type != obj.TYPE_NONE {
|
||||
fmt.Fprintf(&buf, "%s%v", sep, obj.Dconv(p, &p.To))
|
||||
}
|
||||
return buf.String()
|
||||
}
|
||||
|
||||
var Register = []string{
|
||||
"AL", /* [D_AL] */
|
||||
"CL",
|
||||
|
||||
@ -1187,7 +1187,6 @@ var unaryDst = map[int]bool{
|
||||
|
||||
var Linkamd64 = obj.LinkArch{
|
||||
ByteOrder: binary.LittleEndian,
|
||||
Pconv: Pconv,
|
||||
Name: "amd64",
|
||||
Thechar: '6',
|
||||
Preprocess: preprocess,
|
||||
@ -1202,7 +1201,6 @@ var Linkamd64 = obj.LinkArch{
|
||||
|
||||
var Linkamd64p32 = obj.LinkArch{
|
||||
ByteOrder: binary.LittleEndian,
|
||||
Pconv: Pconv,
|
||||
Name: "amd64p32",
|
||||
Thechar: '6',
|
||||
Preprocess: preprocess,
|
||||
@ -1217,7 +1215,6 @@ var Linkamd64p32 = obj.LinkArch{
|
||||
|
||||
var Link386 = obj.LinkArch{
|
||||
ByteOrder: binary.LittleEndian,
|
||||
Pconv: Pconv,
|
||||
Name: "386",
|
||||
Thechar: '8',
|
||||
Preprocess: preprocess,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user