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math/big: add all architectures to mini-compiler
Step 2 of the mini-compiler: add all the remaining architectures. Change-Id: I8c5283aa8baa497785a5c15f2248528fa9ae886e Reviewed-on: https://go-review.googlesource.com/c/go/+/664936 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Alan Donovan <adonovan@google.com> Auto-Submit: Russ Cox <rsc@golang.org>
This commit is contained in:
Russ Cox
Gopher Robot
parent
8cc98a04ef
commit
2a88106617
58
src/math/big/internal/asmgen/386.go
Normal file
58
src/math/big/internal/asmgen/386.go
Normal file
@ -0,0 +1,58 @@
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// Copyright 2025 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package asmgen
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import "fmt"
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var Arch386 = &Arch{
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Name: "386",
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WordBits: 32,
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WordBytes: 4,
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regs: []string{
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"BX", "SI", "DI", "BP",
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"CX", "DX", "AX", // last, to leave available for hinted allocation
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},
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op3: x86Op3,
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hint: x86Hint,
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memOK: true,
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subCarryIsBorrow: true,
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maxColumns: 1, // not enough registers for more
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// Note: It would be nice to not set memIndex and then
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// delete all the code in pipe.go that supports it.
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// But a few routines, notably lshVU and mulAddVWW,
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// benefit dramatically from the use of index registers.
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// Perhaps some day we will decide 386 performance
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// does not matter enough to keep this code.
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memIndex: _386MemIndex,
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mov: "MOVL",
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adds: "ADDL",
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adcs: "ADCL",
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subs: "SUBL",
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sbcs: "SBBL",
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lsh: "SHLL",
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lshd: "SHLL",
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rsh: "SHRL",
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rshd: "SHRL",
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and: "ANDL",
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or: "ORL",
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xor: "XORL",
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neg: "NEGL",
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lea: "LEAL",
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mulWideF: x86MulWide,
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addWords: "LEAL (%[2]s)(%[1]s*4), %[3]s",
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jmpZero: "TESTL %[1]s, %[1]s; JZ %[2]s",
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jmpNonZero: "TESTL %[1]s, %[1]s; JNZ %[2]s",
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loopBottom: "SUBL $1, %[1]s; JNZ %[2]s",
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loopBottomNeg: "ADDL $1, %[1]s; JNZ %[2]s",
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}
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func _386MemIndex(a *Asm, off int, ix Reg, p RegPtr) Reg {
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return Reg{fmt.Sprintf("%d(%s)(%s*%d)", off, p, ix, a.Arch.WordBytes)}
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}
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146
src/math/big/internal/asmgen/amd64.go
Normal file
146
src/math/big/internal/asmgen/amd64.go
Normal file
@ -0,0 +1,146 @@
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// Copyright 2025 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package asmgen
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var ArchAMD64 = &Arch{
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Name: "amd64",
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WordBits: 64,
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WordBytes: 8,
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regs: []string{
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"BX", "SI", "DI",
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"R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
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"AX", "DX", "CX", // last to leave available for hinted allocation
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},
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op3: x86Op3,
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hint: x86Hint,
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memOK: true,
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subCarryIsBorrow: true,
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// Note: Not setting memIndex, because code generally runs faster
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// if we avoid the use of scaled-index memory references,
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// particularly in ADX instructions.
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options: map[Option]func(*Asm, string){
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OptionAltCarry: amd64JmpADX,
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},
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mov: "MOVQ",
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adds: "ADDQ",
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adcs: "ADCQ",
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subs: "SUBQ",
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sbcs: "SBBQ",
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lsh: "SHLQ",
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lshd: "SHLQ",
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rsh: "SHRQ",
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rshd: "SHRQ",
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and: "ANDQ",
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or: "ORQ",
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xor: "XORQ",
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neg: "NEGQ",
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lea: "LEAQ",
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addF: amd64Add,
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mulWideF: x86MulWide,
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addWords: "LEAQ (%[2]s)(%[1]s*8), %[3]s",
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jmpZero: "TESTQ %[1]s, %[1]s; JZ %[2]s",
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jmpNonZero: "TESTQ %[1]s, %[1]s; JNZ %[2]s",
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loopBottom: "SUBQ $1, %[1]s; JNZ %[2]s",
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loopBottomNeg: "ADDQ $1, %[1]s; JNZ %[2]s",
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}
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func amd64JmpADX(a *Asm, label string) {
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a.Printf("\tCMPB ·hasADX(SB), $0; JNZ %s\n", label)
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}
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func amd64Add(a *Asm, src1, src2 Reg, dst Reg, carry Carry) bool {
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if a.Enabled(OptionAltCarry) {
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// If OptionAltCarry is enabled, the generator is emitting ADD instructions
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// both with and without the AltCarry flag set; the AltCarry flag means to
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// use ADOX. Otherwise we have to use ADCX.
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// Using regular ADD/ADC would smash both carry flags,
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// so we reject anything we can't handled with ADCX/ADOX.
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if carry&UseCarry != 0 && carry&(SetCarry|SmashCarry) != 0 {
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if carry&AltCarry != 0 {
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a.op3("ADOXQ", src1, src2, dst)
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} else {
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a.op3("ADCXQ", src1, src2, dst)
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}
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return true
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}
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if carry&(SetCarry|UseCarry) == SetCarry && a.IsZero(src1) && src2 == dst {
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// Clearing carry flag. Caller will add EOL comment.
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a.Printf("\tTESTQ AX, AX\n")
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return true
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}
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if carry != KeepCarry {
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a.Fatalf("unsupported carry")
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}
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}
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return false
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}
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// The x86-prefixed functions are shared with Arch386 in 386.go.
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func x86Op3(name string) bool {
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// As far as a.op3 is concerned, there are no 3-op instructions.
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// (We print instructions like MULX ourselves.)
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return false
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}
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func x86Hint(a *Asm, h Hint) string {
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switch h {
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case HintShiftCount:
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return "CX"
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case HintMulSrc:
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if a.Enabled(OptionAltCarry) { // using MULX
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return "DX"
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}
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return "AX"
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case HintMulHi:
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if a.Enabled(OptionAltCarry) { // using MULX
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return ""
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}
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return "DX"
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}
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return ""
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}
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func x86Suffix(a *Asm) string {
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// Note: Not using a.Arch == Arch386 to avoid init cycle.
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if a.Arch.Name == "386" {
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return "L"
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}
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return "Q"
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}
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func x86MulWide(a *Asm, src1, src2, dstlo, dsthi Reg) {
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if a.Enabled(OptionAltCarry) {
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// Using ADCX/ADOX; use MULX to avoid clearing carry flag.
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if src1.name != "DX" {
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if src2.name != "DX" {
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a.Fatalf("mul src1 or src2 must be DX")
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}
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src2 = src1
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}
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a.Printf("\tMULXQ %s, %s, %s\n", src2, dstlo, dsthi)
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return
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}
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if src1.name != "AX" {
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if src2.name != "AX" {
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a.Fatalf("mulwide src1 or src2 must be AX")
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}
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src2 = src1
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}
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if dstlo.name != "AX" {
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a.Fatalf("mulwide dstlo must be AX")
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}
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if dsthi.name != "DX" {
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a.Fatalf("mulwide dsthi must be DX")
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}
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a.Printf("\tMUL%s %s\n", x86Suffix(a), src2)
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}
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111
src/math/big/internal/asmgen/arm64.go
Normal file
111
src/math/big/internal/asmgen/arm64.go
Normal file
@ -0,0 +1,111 @@
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// Copyright 2025 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package asmgen
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var ArchARM64 = &Arch{
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Name: "arm64",
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WordBits: 64,
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WordBytes: 8,
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CarrySafeLoop: true,
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regs: []string{
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// R18 is the platform register.
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// R27 is the assembler/linker temporary (which we could potentially use but don't).
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// R28 is g.
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// R29 is FP.
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// R30 is LR.
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"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "R8", "R9",
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"R10", "R11", "R12", "R13", "R14", "R15", "R16", "R17", "R19",
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"R20", "R21", "R22", "R23", "R24", "R25", "R26",
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},
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reg0: "ZR",
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mov: "MOVD",
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add: "ADD",
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adds: "ADDS",
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adc: "ADC",
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adcs: "ADCS",
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sub: "SUB",
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subs: "SUBS",
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sbc: "SBC",
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sbcs: "SBCS",
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mul: "MUL",
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mulhi: "UMULH",
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lsh: "LSL",
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rsh: "LSR",
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and: "AND",
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or: "ORR",
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xor: "EOR",
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addWords: "ADD %[1]s<<3, %[2]s, %[3]s",
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jmpZero: "CBZ %s, %s",
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jmpNonZero: "CBNZ %s, %s",
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loadIncN: arm64LoadIncN,
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loadDecN: arm64LoadDecN,
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storeIncN: arm64StoreIncN,
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storeDecN: arm64StoreDecN,
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}
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func arm64LoadIncN(a *Asm, p RegPtr, regs []Reg) {
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if len(regs) == 1 {
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a.Printf("\tMOVD.P %d(%s), %s\n", a.Arch.WordBytes, p, regs[0])
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return
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}
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a.Printf("\tLDP.P %d(%s), (%s, %s)\n", len(regs)*a.Arch.WordBytes, p, regs[0], regs[1])
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var i int
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for i = 2; i+2 <= len(regs); i += 2 {
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a.Printf("\tLDP %d(%s), (%s, %s)\n", (i-len(regs))*a.Arch.WordBytes, p, regs[i], regs[i+1])
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}
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if i < len(regs) {
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a.Printf("\tMOVD %d(%s), %s\n", -1*a.Arch.WordBytes, p, regs[i])
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}
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}
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func arm64LoadDecN(a *Asm, p RegPtr, regs []Reg) {
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if len(regs) == 1 {
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a.Printf("\tMOVD.W -%d(%s), %s\n", a.Arch.WordBytes, p, regs[0])
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return
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}
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a.Printf("\tLDP.W %d(%s), (%s, %s)\n", -len(regs)*a.Arch.WordBytes, p, regs[len(regs)-1], regs[len(regs)-2])
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var i int
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for i = 2; i+2 <= len(regs); i += 2 {
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a.Printf("\tLDP %d(%s), (%s, %s)\n", i*a.Arch.WordBytes, p, regs[len(regs)-1-i], regs[len(regs)-2-i])
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}
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if i < len(regs) {
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a.Printf("\tMOVD %d(%s), %s\n", i*a.Arch.WordBytes, p, regs[0])
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}
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}
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func arm64StoreIncN(a *Asm, p RegPtr, regs []Reg) {
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if len(regs) == 1 {
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a.Printf("\tMOVD.P %s, %d(%s)\n", regs[0], a.Arch.WordBytes, p)
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return
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}
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a.Printf("\tSTP.P (%s, %s), %d(%s)\n", regs[0], regs[1], len(regs)*a.Arch.WordBytes, p)
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var i int
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for i = 2; i+2 <= len(regs); i += 2 {
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a.Printf("\tSTP (%s, %s), %d(%s)\n", regs[i], regs[i+1], (i-len(regs))*a.Arch.WordBytes, p)
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}
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if i < len(regs) {
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a.Printf("\tMOVD %s, %d(%s)\n", regs[i], -1*a.Arch.WordBytes, p)
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}
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}
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func arm64StoreDecN(a *Asm, p RegPtr, regs []Reg) {
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if len(regs) == 1 {
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a.Printf("\tMOVD.W %s, -%d(%s)\n", regs[0], a.Arch.WordBytes, p)
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return
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}
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a.Printf("\tSTP.W (%s, %s), %d(%s)\n", regs[len(regs)-1], regs[len(regs)-2], -len(regs)*a.Arch.WordBytes, p)
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var i int
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for i = 2; i+2 <= len(regs); i += 2 {
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a.Printf("\tSTP (%s, %s), %d(%s)\n", regs[len(regs)-1-i], regs[len(regs)-2-i], i*a.Arch.WordBytes, p)
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}
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if i < len(regs) {
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a.Printf("\tMOVD %s, %d(%s)\n", regs[0], i*a.Arch.WordBytes, p)
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}
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}
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52
src/math/big/internal/asmgen/cheat.go
Normal file
52
src/math/big/internal/asmgen/cheat.go
Normal file
@ -0,0 +1,52 @@
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// Copyright 2025 The Go Authors. All rights reserved.
|
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// Use of this source code is governed by a BSD-style
|
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// license that can be found in the LICENSE file.
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//go:build ignore
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// This program can be compiled with -S to produce a “cheat sheet”
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// for filling out a new Arch: the compiler will show you how to implement
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// the various operations.
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//
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// Usage (replace TARGET with your target architecture):
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//
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// GOOS=linux GOARCH=TARGET go build -gcflags='-p=cheat -S' cheat.go
|
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|
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package p
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import "math/bits"
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func mov(x, y uint) uint { return y }
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func zero() uint { return 0 }
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func add(x, y uint) uint { return x + y }
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func adds(x, y, c uint) (uint, uint) { return bits.Add(x, y, 0) }
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func adcs(x, y, c uint) (uint, uint) { return bits.Add(x, y, c) }
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func sub(x, y uint) uint { return x + y }
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func subs(x, y uint) (uint, uint) { return bits.Sub(x, y, 0) }
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func sbcs(x, y, c uint) (uint, uint) { return bits.Sub(x, y, c) }
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func mul(x, y uint) uint { return x * y }
|
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func mulWide(x, y uint) (uint, uint) { return bits.Mul(x, y) }
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func lsh(x, s uint) uint { return x << s }
|
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func rsh(x, s uint) uint { return x >> s }
|
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func and(x, y uint) uint { return x & y }
|
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func or(x, y uint) uint { return x | y }
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func xor(x, y uint) uint { return x ^ y }
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func neg(x uint) uint { return -x }
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func loop(x int) int {
|
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s := 0
|
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for i := 1; i < x; i++ {
|
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s += i
|
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if s == 98 {
|
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return 99
|
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}
|
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if s == 99 {
|
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return 100
|
||||
}
|
||||
if s == 0 {
|
||||
return 101
|
||||
}
|
||||
s += 2
|
||||
}
|
||||
return s
|
||||
}
|
||||
func mem(x *[10]struct{ a, b uint }, i int) uint { return x[i].b }
|
||||
45
src/math/big/internal/asmgen/loong64.go
Normal file
45
src/math/big/internal/asmgen/loong64.go
Normal file
@ -0,0 +1,45 @@
|
||||
// Copyright 2025 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
// license that can be found in the LICENSE file.
|
||||
|
||||
package asmgen
|
||||
|
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var ArchLoong64 = &Arch{
|
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Name: "loong64",
|
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WordBits: 64,
|
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WordBytes: 8,
|
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CarrySafeLoop: true,
|
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|
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regs: []string{
|
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// R0 is set to 0.
|
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// R1 is LR.
|
||||
// R2 is ???
|
||||
// R3 is SP.
|
||||
// R22 is g.
|
||||
// R28 and R29 are our virtual carry flags.
|
||||
// R30 is the linker/assembler temp, which we use too.
|
||||
"R4", "R5", "R6", "R7", "R8", "R9",
|
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"R10", "R11", "R12", "R13", "R14", "R15", "R16", "R17", "R18", "R19",
|
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"R20", "R21", "R23", "R24", "R25", "R26", "R27",
|
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"R31",
|
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},
|
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reg0: "R0",
|
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regCarry: "R28",
|
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regAltCarry: "R29",
|
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regTmp: "R30",
|
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|
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mov: "MOVV",
|
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add: "ADDVU",
|
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sub: "SUBVU",
|
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sltu: "SGTU",
|
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mul: "MULV",
|
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mulhi: "MULHVU",
|
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lsh: "SLLV",
|
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rsh: "SRLV",
|
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and: "AND",
|
||||
or: "OR",
|
||||
xor: "XOR",
|
||||
|
||||
jmpZero: "BEQ %s, %s",
|
||||
jmpNonZero: "BNE %s, %s",
|
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}
|
||||
@ -15,9 +15,16 @@
|
||||
package asmgen
|
||||
|
||||
var arches = []*Arch{
|
||||
Arch386,
|
||||
ArchAMD64,
|
||||
ArchARM,
|
||||
ArchARM64,
|
||||
ArchLoong64,
|
||||
ArchMIPS,
|
||||
ArchMIPS64x,
|
||||
ArchPPC64x,
|
||||
ArchRISCV64,
|
||||
ArchS390X,
|
||||
}
|
||||
|
||||
// generate returns the file name and content of the generated assembly for the given architecture.
|
||||
|
||||
64
src/math/big/internal/asmgen/ppc64.go
Normal file
64
src/math/big/internal/asmgen/ppc64.go
Normal file
@ -0,0 +1,64 @@
|
||||
// Copyright 2025 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
// license that can be found in the LICENSE file.
|
||||
|
||||
package asmgen
|
||||
|
||||
var ArchPPC64x = &Arch{
|
||||
Name: "ppc64x",
|
||||
Build: "ppc64 || ppc64le",
|
||||
WordBits: 64,
|
||||
WordBytes: 8,
|
||||
CarrySafeLoop: true,
|
||||
|
||||
// Note: The old, hand-written ppc64x assembly used MOVDU
|
||||
// to avoid explicit pointer updates in a few routines, but the new
|
||||
// generated code runs just as fast, so we haven't bothered to try
|
||||
// to add that back. (It's not trivial; you'd have to keep the pointers
|
||||
// shifted one word in order to make the semantics work.)
|
||||
//
|
||||
// The old assembly also used some complex vector instructions
|
||||
// to implement lshVU and rshVU, but the generated code that uses
|
||||
// ordinary integer instructions is much faster than the vector code was,
|
||||
// at least on the power10 gomote.
|
||||
|
||||
regs: []string{
|
||||
// R0 is 0 by convention.
|
||||
// R1 is SP.
|
||||
// R2 is TOC.
|
||||
// R30 is g.
|
||||
// R31 is the assembler/linker temporary (which we use too).
|
||||
"R3", "R4", "R5", "R6", "R7", "R8", "R9",
|
||||
"R10", "R11", "R12" /*R13 is TLS*/, "R14", "R15", "R16", "R17", "R18", "R19",
|
||||
"R20", "R21", "R22", "R23", "R24", "R25", "R26", "R27", "R28", "R29",
|
||||
},
|
||||
reg0: "R0",
|
||||
regTmp: "R31",
|
||||
|
||||
// Note: Could write an addF and subF to use ADDZE and SUBZE,
|
||||
// but we have R0 so it doesn't seem to matter much.
|
||||
|
||||
mov: "MOVD",
|
||||
add: "ADD",
|
||||
adds: "ADDC",
|
||||
adcs: "ADDE",
|
||||
sub: "SUB",
|
||||
subs: "SUBC",
|
||||
sbcs: "SUBE",
|
||||
mul: "MULLD",
|
||||
mulhi: "MULHDU",
|
||||
lsh: "SLD",
|
||||
rsh: "SRD",
|
||||
and: "ANDCC", // regular AND does not accept immediates
|
||||
or: "OR",
|
||||
xor: "XOR",
|
||||
|
||||
jmpZero: "CMP %[1]s, $0; BEQ %[2]s",
|
||||
jmpNonZero: "CMP %s, $0; BNE %s",
|
||||
|
||||
// Note: Using CTR means that we could free the count register
|
||||
// during the loop body, but the portable logic doesn't know that,
|
||||
// and we're not hurting for registers.
|
||||
loopTop: "CMP %[1]s, $0; BEQ %[2]s; MOVD %[1]s, CTR",
|
||||
loopBottom: "BDNZ %[2]s",
|
||||
}
|
||||
47
src/math/big/internal/asmgen/riscv64.go
Normal file
47
src/math/big/internal/asmgen/riscv64.go
Normal file
@ -0,0 +1,47 @@
|
||||
// Copyright 2025 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
// license that can be found in the LICENSE file.
|
||||
|
||||
package asmgen
|
||||
|
||||
var ArchRISCV64 = &Arch{
|
||||
Name: "riscv64",
|
||||
WordBits: 64,
|
||||
WordBytes: 8,
|
||||
CarrySafeLoop: true,
|
||||
|
||||
regs: []string{
|
||||
// X0 is zero.
|
||||
// X1 is LR.
|
||||
// X2 is SP.
|
||||
// X3 is SB.
|
||||
// X4 is TP.
|
||||
// X27 is g.
|
||||
// X28 and X29 are our virtual carry flags.
|
||||
// X31 is the assembler/linker temporary (which we use too).
|
||||
"X5", "X6", "X7", "X8", "X9",
|
||||
"X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19",
|
||||
"X20", "X21", "X22", "X23", "X24", "X25", "X26",
|
||||
"X30",
|
||||
},
|
||||
|
||||
reg0: "X0",
|
||||
regCarry: "X28",
|
||||
regAltCarry: "X29",
|
||||
regTmp: "X31",
|
||||
|
||||
mov: "MOV",
|
||||
add: "ADD",
|
||||
sub: "SUB",
|
||||
mul: "MUL",
|
||||
mulhi: "MULHU",
|
||||
lsh: "SLL",
|
||||
rsh: "SRL",
|
||||
and: "AND",
|
||||
or: "OR",
|
||||
xor: "XOR",
|
||||
sltu: "SLTU",
|
||||
|
||||
jmpZero: "BEQZ %s, %s",
|
||||
jmpNonZero: "BNEZ %s, %s",
|
||||
}
|
||||
100
src/math/big/internal/asmgen/s390x.go
Normal file
100
src/math/big/internal/asmgen/s390x.go
Normal file
@ -0,0 +1,100 @@
|
||||
// Copyright 2025 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
// license that can be found in the LICENSE file.
|
||||
|
||||
package asmgen
|
||||
|
||||
var ArchS390X = &Arch{
|
||||
Name: "s390x",
|
||||
WordBits: 64,
|
||||
WordBytes: 8,
|
||||
CarrySafeLoop: true,
|
||||
|
||||
regs: []string{
|
||||
// R0 is 0 by convention in this code (see setup).
|
||||
// R10 is the assembler/linker temporary.
|
||||
// R11 is a second assembler/linker temporary, for wide multiply.
|
||||
// We allow allocating R10 and R11 so that we can use them as
|
||||
// direct multiplication targets while tracking whether they're in use.
|
||||
// R13 is g.
|
||||
// R14 is LR.
|
||||
// R15 is SP.
|
||||
"R1", "R2", "R3", "R4", "R5", "R6", "R7", "R8", "R9",
|
||||
"R10", "R11", "R12",
|
||||
},
|
||||
reg0: "R0",
|
||||
regTmp: "R10",
|
||||
setup: s390xSetup,
|
||||
maxColumns: 2,
|
||||
op3: s390xOp3,
|
||||
hint: s390xHint,
|
||||
|
||||
// Instruction reference: chapter 7 of
|
||||
// https://www.ibm.com/docs/en/SSQ2R2_15.0.0/com.ibm.tpf.toolkit.hlasm.doc/dz9zr006.pdf
|
||||
|
||||
mov: "MOVD",
|
||||
adds: "ADDC", // ADD is an alias for ADDC, sets carry
|
||||
adcs: "ADDE",
|
||||
subs: "SUBC", // SUB is an alias for SUBC, sets carry
|
||||
sbcs: "SUBE",
|
||||
mulWideF: s390MulWide,
|
||||
lsh: "SLD",
|
||||
rsh: "SRD",
|
||||
and: "AND",
|
||||
or: "OR",
|
||||
xor: "XOR",
|
||||
neg: "NEG",
|
||||
lea: "LAY", // LAY because LA only accepts positive offsets
|
||||
|
||||
jmpZero: "CMPBEQ %s, $0, %s",
|
||||
jmpNonZero: "CMPBNE %s, $0, %s",
|
||||
}
|
||||
|
||||
func s390xSetup(f *Func) {
|
||||
a := f.Asm
|
||||
if f.Name == "addVV" || f.Name == "subVV" {
|
||||
// S390x, unlike every other system, has vector instructions
|
||||
// that can propagate carry bits during parallel adds (VACC).
|
||||
// Instead of trying to generate that for this one system,
|
||||
// jump to the hand-written code in arithvec_s390x.s.
|
||||
a.Printf("\tMOVB ·hasVX(SB), R1\n")
|
||||
a.Printf("\tCMPBEQ R1, $0, novec\n")
|
||||
a.Printf("\tJMP ·%svec(SB)\n", f.Name)
|
||||
a.Printf("novec:\n")
|
||||
}
|
||||
a.Printf("\tMOVD $0, R0\n")
|
||||
}
|
||||
|
||||
func s390xOp3(name string) bool {
|
||||
if name == "AND" { // AND with immediate only takes imm, reg; not imm, reg, reg.
|
||||
return false
|
||||
}
|
||||
return true
|
||||
}
|
||||
|
||||
func s390xHint(_ *Asm, h Hint) string {
|
||||
switch h {
|
||||
case HintMulSrc:
|
||||
return "R11"
|
||||
case HintMulHi:
|
||||
return "R10"
|
||||
}
|
||||
return ""
|
||||
}
|
||||
|
||||
func s390MulWide(a *Asm, src1, src2, dstlo, dsthi Reg) {
|
||||
if src1.name != "R11" && src2.name != "R11" {
|
||||
a.Fatalf("mulWide src1 or src2 must be R11")
|
||||
}
|
||||
if dstlo.name != "R11" {
|
||||
a.Fatalf("mulWide dstlo must be R11")
|
||||
}
|
||||
if dsthi.name != "R10" {
|
||||
a.Fatalf("mulWide dsthi must be R10")
|
||||
}
|
||||
src := src1
|
||||
if src.name == "R11" {
|
||||
src = src2
|
||||
}
|
||||
a.Printf("\tMLGR %s, R10\n", src)
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user