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cmd/internal/obj/riscv: add support for vector reduction instructions

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Add support for vector reduction instructions to the RISC-V assembler,
including single-width integer reduction, widening integer reduction,
single-width floating-point reduction and widening floating-point
reduction.

Change-Id: I8f17bef11389f3a017e0430275023fc5d75936e3
Reviewed-on: https://go-review.googlesource.com/c/go/+/646778
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Carlos Amedee <carlos@golang.org>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
This commit is contained in:
Joel Sing 2025-02-02 22:26:07 +11:00
parent 7785528c50
commit 2e60916f6e
4 changed files with 98 additions and 1 deletions
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40
src/cmd/asm/internal/asm/testdata/riscv64.s vendored
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@ -1161,6 +1161,46 @@ start:
VFNCVTRODFFW V2, V3 // d7912a4a
VFNCVTRODFFW V2, V0, V3 // d7912a48
// 31.14.1: Vector Single-Width Integer Reduction Instructions
VREDSUMVS V1, V2, V3 // d7a12002
VREDSUMVS V1, V2, V0, V3 // d7a12000
VREDMAXUVS V1, V2, V3 // d7a1201a
VREDMAXUVS V1, V2, V0, V3 // d7a12018
VREDMAXVS V1, V2, V3 // d7a1201e
VREDMAXVS V1, V2, V0, V3 // d7a1201c
VREDMINUVS V1, V2, V3 // d7a12012
VREDMINUVS V1, V2, V0, V3 // d7a12010
VREDMINVS V1, V2, V3 // d7a12016
VREDMINVS V1, V2, V0, V3 // d7a12014
VREDANDVS V1, V2, V3 // d7a12006
VREDANDVS V1, V2, V0, V3 // d7a12004
VREDORVS V1, V2, V3 // d7a1200a
VREDORVS V1, V2, V0, V3 // d7a12008
VREDXORVS V1, V2, V3 // d7a1200e
VREDXORVS V1, V2, V0, V3 // d7a1200c
// 31.14.2: Vector Widening Integer Reduction Instructions
VWREDSUMUVS V1, V2, V3 // d78120c2
VWREDSUMUVS V1, V2, V0, V3 // d78120c0
VWREDSUMVS V1, V2, V3 // d78120c6
VWREDSUMVS V1, V2, V0, V3 // d78120c4
// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
VFREDOSUMVS V1, V2, V3 // d791200e
VFREDOSUMVS V1, V2, V0, V3 // d791200c
VFREDUSUMVS V1, V2, V3 // d7912006
VFREDUSUMVS V1, V2, V0, V3 // d7912004
VFREDMAXVS V1, V2, V3 // d791201e
VFREDMAXVS V1, V2, V0, V3 // d791201c
VFREDMINVS V1, V2, V3 // d7912016
VFREDMINVS V1, V2, V0, V3 // d7912014
// 31.14.4: Vector Widening Floating-Point Reduction Instructions
VFWREDOSUMVS V1, V2, V3 // d79120ce
VFWREDOSUMVS V1, V2, V0, V3 // d79120cc
VFWREDUSUMVS V1, V2, V3 // d79120c6
VFWREDUSUMVS V1, V2, V0, V3 // d79120c4
//
// Privileged ISA
//

15
src/cmd/asm/internal/asm/testdata/riscv64error.s vendored
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@ -347,5 +347,20 @@ TEXT errors(SB),$0
VFNCVTFXW V2, V4, V3 // ERROR "invalid vector mask register"
VFNCVTFFW V2, V4, V3 // ERROR "invalid vector mask register"
VFNCVTRODFFW V2, V4, V3 // ERROR "invalid vector mask register"
VREDSUMVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VREDMAXUVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VREDMAXVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VREDMINUVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VREDMINVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VREDANDVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VREDORVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VREDXORVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VWREDSUMUVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VWREDSUMVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VFREDOSUMVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VFREDUSUMVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VFREDMAXVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VFREDMINVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
VFWREDOSUMVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
RET

16
src/cmd/asm/internal/asm/testdata/riscv64validation.s vendored
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@ -364,5 +364,21 @@ TEXT validation(SB),$0
VFNCVTFXW X10, V3 // ERROR "expected vector register in vs2 position"
VFNCVTFFW X10, V3 // ERROR "expected vector register in vs2 position"
VFNCVTRODFFW X10, V3 // ERROR "expected vector register in vs2 position"
VREDSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VREDMAXUVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VREDMAXVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VREDMINUVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VREDMINVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VREDANDVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VREDORVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VREDXORVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VWREDSUMUVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VWREDSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VFREDOSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VFREDUSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VFREDMAXVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VFREDMINVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VFWREDOSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
VFWREDUSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
RET

28
src/cmd/internal/obj/riscv/obj.go
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@ -2585,6 +2585,30 @@ var instructions = [ALAST & obj.AMask]instructionData{
AVFNCVTFFW & obj.AMask: {enc: rVVEncoding},
AVFNCVTRODFFW & obj.AMask: {enc: rVVEncoding},
// 31.14.1: Vector Single-Width Integer Reduction Instructions
AVREDSUMVS & obj.AMask: {enc: rVVVEncoding},
AVREDMAXUVS & obj.AMask: {enc: rVVVEncoding},
AVREDMAXVS & obj.AMask: {enc: rVVVEncoding},
AVREDMINUVS & obj.AMask: {enc: rVVVEncoding},
AVREDMINVS & obj.AMask: {enc: rVVVEncoding},
AVREDANDVS & obj.AMask: {enc: rVVVEncoding},
AVREDORVS & obj.AMask: {enc: rVVVEncoding},
AVREDXORVS & obj.AMask: {enc: rVVVEncoding},
// 31.14.2: Vector Widening Integer Reduction Instructions
AVWREDSUMUVS & obj.AMask: {enc: rVVVEncoding},
AVWREDSUMVS & obj.AMask: {enc: rVVVEncoding},
// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
AVFREDOSUMVS & obj.AMask: {enc: rVVVEncoding},
AVFREDUSUMVS & obj.AMask: {enc: rVVVEncoding},
AVFREDMAXVS & obj.AMask: {enc: rVVVEncoding},
AVFREDMINVS & obj.AMask: {enc: rVVVEncoding},
// 31.14.4: Vector Widening Floating-Point Reduction Instructions
AVFWREDOSUMVS & obj.AMask: {enc: rVVVEncoding},
AVFWREDUSUMVS & obj.AMask: {enc: rVVVEncoding},
//
// Privileged ISA
//
@ -3578,7 +3602,9 @@ func instructionsForProg(p *obj.Prog) []*instruction {
AVFMULVV, AVFMULVF, AVFDIVVV, AVFDIVVF, AVFRDIVVF, AVFWMULVV, AVFWMULVF,
AVFMINVV, AVFMINVF, AVFMAXVV, AVFMAXVF,
AVFSGNJVV, AVFSGNJVF, AVFSGNJNVV, AVFSGNJNVF, AVFSGNJXVV, AVFSGNJXVF,
AVMFEQVV, AVMFEQVF, AVMFNEVV, AVMFNEVF, AVMFLTVV, AVMFLTVF, AVMFLEVV, AVMFLEVF, AVMFGTVF, AVMFGEVF:
AVMFEQVV, AVMFEQVF, AVMFNEVV, AVMFNEVF, AVMFLTVV, AVMFLTVF, AVMFLEVV, AVMFLEVF, AVMFGTVF, AVMFGEVF,
AVREDSUMVS, AVREDMAXUVS, AVREDMAXVS, AVREDMINUVS, AVREDMINVS, AVREDANDVS, AVREDORVS, AVREDXORVS,
AVWREDSUMUVS, AVWREDSUMVS, AVFREDOSUMVS, AVFREDUSUMVS, AVFREDMAXVS, AVFREDMINVS, AVFWREDOSUMVS, AVFWREDUSUMVS:
// Set mask bit
switch {
case ins.rs3 == obj.REG_NONE: