mirror of
https://github.com/golang/go.git
synced 2025-05-28 02:41:30 +00:00
cmd/compile: start on ARM port
Start working on arm port. Gets close to correct
code for fibonacci:
func fib(n int) int {
if n < 2 {
return n
}
return fib(n-1) + fib(n-2)
}
Still a lot to do, but this is a good starting point.
Cleaned up some arch-specific dependencies in regalloc.
Change-Id: I4301c6c31a8402168e50dcfee8bcf7aee73ea9d5
Reviewed-on: https://go-review.googlesource.com/21000
Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Keith Randall
parent
44d3f89e99
commit
4c9a470d46
@ -6,6 +6,7 @@ package arm
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import (
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"cmd/compile/internal/gc"
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"cmd/compile/internal/ssa"
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"cmd/internal/obj/arm"
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)
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@ -65,6 +66,11 @@ func Main() {
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gc.Thearch.Doregbits = doregbits
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gc.Thearch.Regnames = regnames
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gc.Thearch.SSARegToReg = ssaRegToReg
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gc.Thearch.SSAMarkMoves = func(s *gc.SSAGenState, b *ssa.Block) {}
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gc.Thearch.SSAGenValue = ssaGenValue
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gc.Thearch.SSAGenBlock = ssaGenBlock
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gc.Main()
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gc.Exit(0)
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}
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152
src/cmd/compile/internal/arm/ssa.go
Normal file
152
src/cmd/compile/internal/arm/ssa.go
Normal file
@ -0,0 +1,152 @@
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// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package arm
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import (
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"cmd/compile/internal/gc"
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"cmd/compile/internal/ssa"
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"cmd/internal/obj"
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"cmd/internal/obj/arm"
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)
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var ssaRegToReg = []int16{
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arm.REG_R0,
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arm.REG_R1,
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arm.REG_R2,
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arm.REG_R3,
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arm.REGSP, // aka R13
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}
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func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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s.SetLineno(v.Line)
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switch v.Op {
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case ssa.OpInitMem:
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// memory arg needs no code
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case ssa.OpArg:
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// input args need no code
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case ssa.OpSP, ssa.OpSB:
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// nothing to do
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case ssa.OpCopy:
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case ssa.OpLoadReg:
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// TODO: by type
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p := gc.Prog(arm.AMOVW)
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n, off := gc.AutoVar(v.Args[0])
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p.From.Type = obj.TYPE_MEM
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p.From.Node = n
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p.From.Sym = gc.Linksym(n.Sym)
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p.From.Offset = off
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if n.Class == gc.PPARAM || n.Class == gc.PPARAMOUT {
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p.From.Name = obj.NAME_PARAM
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p.From.Offset += n.Xoffset
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} else {
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p.From.Name = obj.NAME_AUTO
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}
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpStoreReg:
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// TODO: by type
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p := gc.Prog(arm.AMOVW)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = gc.SSARegNum(v.Args[0])
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n, off := gc.AutoVar(v)
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p.To.Type = obj.TYPE_MEM
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p.To.Node = n
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p.To.Sym = gc.Linksym(n.Sym)
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p.To.Offset = off
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if n.Class == gc.PPARAM || n.Class == gc.PPARAMOUT {
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p.To.Name = obj.NAME_PARAM
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p.To.Offset += n.Xoffset
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} else {
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p.To.Name = obj.NAME_AUTO
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}
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case ssa.OpARMADD:
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r := gc.SSARegNum(v)
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r1 := gc.SSARegNum(v.Args[0])
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r2 := gc.SSARegNum(v.Args[1])
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r1
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p.Reg = r2
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpARMADDconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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if v.Aux != nil {
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panic("can't handle symbolic constant yet")
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}
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p.Reg = gc.SSARegNum(v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpARMMOVWconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt2Int64()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpARMCMP:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = gc.SSARegNum(v.Args[0])
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p.Reg = gc.SSARegNum(v.Args[1])
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case ssa.OpARMMOVWload:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = gc.SSARegNum(v.Args[0])
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpARMMOVWstore:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = gc.SSARegNum(v.Args[1])
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = gc.SSARegNum(v.Args[0])
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gc.AddAux(&p.To, v)
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case ssa.OpARMCALLstatic:
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// TODO: deferreturn
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p := gc.Prog(obj.ACALL)
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p.To.Type = obj.TYPE_MEM
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p.To.Name = obj.NAME_EXTERN
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p.To.Sym = gc.Linksym(v.Aux.(*gc.Sym))
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if gc.Maxarg < v.AuxInt {
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gc.Maxarg = v.AuxInt
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}
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case ssa.OpVarDef:
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gc.Gvardef(v.Aux.(*gc.Node))
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case ssa.OpVarKill:
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gc.Gvarkill(v.Aux.(*gc.Node))
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case ssa.OpVarLive:
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gc.Gvarlive(v.Aux.(*gc.Node))
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case ssa.OpARMLessThan:
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v.Fatalf("pseudo-op made it to output: %s", v.LongString())
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default:
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v.Unimplementedf("genValue not implemented: %s", v.LongString())
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}
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}
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func ssaGenBlock(s *gc.SSAGenState, b, next *ssa.Block) {
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s.SetLineno(b.Line)
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switch b.Kind {
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case ssa.BlockCall:
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if b.Succs[0] != next {
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p := gc.Prog(obj.AJMP)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{p, b.Succs[0]})
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}
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case ssa.BlockRet:
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gc.Prog(obj.ARET)
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case ssa.BlockARMLT:
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p := gc.Prog(arm.ABGE)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{p, b.Succs[0]})
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p = gc.Prog(obj.AJMP)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{p, b.Succs[1]})
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}
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}
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@ -30,8 +30,14 @@ func initssa() *ssa.Config {
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}
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func shouldssa(fn *Node) bool {
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if Thearch.Thestring != "amd64" {
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return false
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switch Thearch.Thestring {
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default:
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// Only available for testing.
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if os.Getenv("SSATEST") == "" {
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return false
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}
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// Generally available.
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case "amd64":
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}
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if !ssaEnabled {
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return false
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@ -18,6 +18,7 @@ type Config struct {
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PtrSize int64 // 4 or 8
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lowerBlock func(*Block) bool // lowering function
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lowerValue func(*Value, *Config) bool // lowering function
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registers []Register // machine registers
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fe Frontend // callbacks into compiler frontend
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HTML *HTMLWriter // html writer, for debugging
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ctxt *obj.Link // Generic arch information
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@ -112,11 +113,18 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
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c.PtrSize = 8
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c.lowerBlock = rewriteBlockAMD64
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c.lowerValue = rewriteValueAMD64
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c.registers = registersAMD64[:]
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case "386":
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c.IntSize = 4
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c.PtrSize = 4
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c.lowerBlock = rewriteBlockAMD64
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c.lowerValue = rewriteValueAMD64 // TODO(khr): full 32-bit support
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case "arm":
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c.IntSize = 4
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c.PtrSize = 4
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c.lowerBlock = rewriteBlockARM
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c.lowerValue = rewriteValueARM
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c.registers = registersARM[:]
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default:
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fe.Unimplementedf(0, "arch %s not implemented", arch)
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}
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32
src/cmd/compile/internal/ssa/gen/ARM.rules
Normal file
32
src/cmd/compile/internal/ssa/gen/ARM.rules
Normal file
@ -0,0 +1,32 @@
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// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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(Add32 x y) -> (ADD x y)
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(Const32 [val]) -> (MOVWconst [val])
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(Less32 x y) -> (LessThan (CMP x y))
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(OffPtr [off] ptr) -> (ADD (MOVWconst <config.Frontend().TypeInt32()> [off]) ptr)
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(Addr {sym} base) -> (ADDconst {sym} base)
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(Load <t> ptr mem) && is32BitInt(t) -> (MOVWload ptr mem)
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(Store [4] ptr val mem) -> (MOVWstore ptr val mem)
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(StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem)
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// Absorb LessThan into blocks.
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(If (LessThan cc) yes no) -> (LT cc yes no)
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// Optimizations
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(ADD (MOVWconst [c]) x) -> (ADDconst [c] x)
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(ADD x (MOVWconst [c])) -> (ADDconst [c] x)
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(MOVWload [off1] {sym1} (ADDconst [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVWstore [off1] {sym1} (ADDconst [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
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(MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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66
src/cmd/compile/internal/ssa/gen/ARMOps.go
Normal file
66
src/cmd/compile/internal/ssa/gen/ARMOps.go
Normal file
@ -0,0 +1,66 @@
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// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package main
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func init() {
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var (
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gp01 = regInfo{inputs: []regMask{}, outputs: []regMask{31}}
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gp11 = regInfo{inputs: []regMask{31}, outputs: []regMask{31}}
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gp21 = regInfo{inputs: []regMask{31, 31}, outputs: []regMask{31}}
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gp2flags = regInfo{inputs: []regMask{31, 31}, outputs: []regMask{32}}
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gpload = regInfo{inputs: []regMask{31}, outputs: []regMask{31}}
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gpstore = regInfo{inputs: []regMask{31, 31}, outputs: []regMask{}}
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flagsgp = regInfo{inputs: []regMask{32}, outputs: []regMask{31}}
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callerSave = regMask(15)
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)
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ops := []opData{
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{name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1
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{name: "ADDconst", argLength: 1, reg: gp11, asm: "ADD", aux: "SymOff"}, // arg0 + auxInt + aux.(*gc.Sym)
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{name: "MOVWconst", argLength: 0, reg: gp01, aux: "Int32", asm: "MOVW", rematerializeable: true}, // 32 low bits of auxint
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{name: "CMP", argLength: 2, reg: gp2flags, asm: "CMP", typ: "Flags"}, // arg0 compare to arg1
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{name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW"}, // load from arg0 + auxInt + aux. arg1=mem.
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{name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
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{name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
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// pseudo-ops
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{name: "LessThan", argLength: 2, reg: flagsgp}, // bool, 1 flags encode x<y 0 otherwise.
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}
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blocks := []blockData{
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{name: "EQ"},
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{name: "NE"},
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{name: "LT"},
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{name: "LE"},
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{name: "GT"},
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{name: "GE"},
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{name: "ULT"},
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{name: "ULE"},
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{name: "UGT"},
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{name: "UGE"},
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}
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regNames := []string{
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"R0",
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"R1",
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"R2",
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"R3",
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"SP",
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"FLAGS",
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"SB",
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}
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archs = append(archs, arch{
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name: "ARM",
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pkg: "cmd/internal/obj/arm",
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genfile: "../../arm/ssa.go",
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ops: ops,
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blocks: blocks,
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regnames: regNames,
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})
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}
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@ -10,8 +10,9 @@ var decBlocks = []blockData{}
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func init() {
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archs = append(archs, arch{
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name: "dec",
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ops: decOps,
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blocks: decBlocks,
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name: "dec",
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ops: decOps,
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blocks: decBlocks,
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generic: true,
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})
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}
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@ -414,8 +414,9 @@ var genericBlocks = []blockData{
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func init() {
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archs = append(archs, arch{
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name: "generic",
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ops: genericOps,
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blocks: genericBlocks,
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name: "generic",
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ops: genericOps,
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blocks: genericBlocks,
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generic: true,
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})
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}
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@ -26,6 +26,7 @@ type arch struct {
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ops []opData
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blocks []blockData
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regnames []string
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generic bool
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}
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type opData struct {
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@ -205,6 +206,18 @@ func genOp() {
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// generate op string method
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fmt.Fprintln(w, "func (o Op) String() string {return opcodeTable[o].name }")
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// generate registers
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for _, a := range archs {
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if a.generic {
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continue
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}
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fmt.Fprintf(w, "var registers%s = [...]Register {\n", a.name)
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for i, r := range a.regnames {
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fmt.Fprintf(w, " {%d, \"%s\"},\n", i, r)
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}
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fmt.Fprintln(w, "}")
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}
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// gofmt result
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b := w.Bytes()
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var err error
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@ -55,6 +55,8 @@ const (
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auxSym // aux is a symbol
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auxSymOff // aux is a symbol, auxInt is an offset
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auxSymValAndOff // aux is a symbol, auxInt is a ValAndOff
|
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auxSymInt32 // aux is a symbol, auxInt is a 32-bit integer
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)
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// A ValAndOff is used by the several opcodes. It holds
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@ -5,6 +5,7 @@ package ssa
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import (
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"cmd/internal/obj"
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"cmd/internal/obj/arm"
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"cmd/internal/obj/x86"
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)
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@ -26,6 +27,17 @@ const (
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BlockAMD64ORD
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BlockAMD64NAN
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BlockARMEQ
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BlockARMNE
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BlockARMLT
|
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BlockARMLE
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BlockARMGT
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BlockARMGE
|
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BlockARMULT
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BlockARMULE
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BlockARMUGT
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BlockARMUGE
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BlockPlain
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BlockIf
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BlockCall
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@ -56,6 +68,17 @@ var blockString = [...]string{
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BlockAMD64ORD: "ORD",
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BlockAMD64NAN: "NAN",
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BlockARMEQ: "EQ",
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BlockARMNE: "NE",
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BlockARMLT: "LT",
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BlockARMLE: "LE",
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BlockARMGT: "GT",
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BlockARMGE: "GE",
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BlockARMULT: "ULT",
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BlockARMULE: "ULE",
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BlockARMUGT: "UGT",
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BlockARMUGE: "UGE",
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|
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BlockPlain: "Plain",
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BlockIf: "If",
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BlockCall: "Call",
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@ -309,6 +332,15 @@ const (
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OpAMD64FlagGT_UGT
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OpAMD64FlagGT_ULT
|
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|
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OpARMADD
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OpARMADDconst
|
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OpARMMOVWconst
|
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OpARMCMP
|
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OpARMMOVWload
|
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OpARMMOVWstore
|
||||
OpARMCALLstatic
|
||||
OpARMLessThan
|
||||
|
||||
OpAdd8
|
||||
OpAdd16
|
||||
OpAdd32
|
||||
@ -3915,6 +3947,106 @@ var opcodeTable = [...]opInfo{
|
||||
reg: regInfo{},
|
||||
},
|
||||
|
||||
{
|
||||
name: "ADD",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
asm: arm.AADD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 31}, // R0 R1 R2 R3 SP
|
||||
{1, 31}, // R0 R1 R2 R3 SP
|
||||
},
|
||||
outputs: []regMask{
|
||||
31, // R0 R1 R2 R3 SP
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDconst",
|
||||
auxType: auxSymOff,
|
||||
argLen: 1,
|
||||
asm: arm.AADD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 31}, // R0 R1 R2 R3 SP
|
||||
},
|
||||
outputs: []regMask{
|
||||
31, // R0 R1 R2 R3 SP
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVWconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 0,
|
||||
rematerializeable: true,
|
||||
asm: arm.AMOVW,
|
||||
reg: regInfo{
|
||||
outputs: []regMask{
|
||||
31, // R0 R1 R2 R3 SP
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMP",
|
||||
argLen: 2,
|
||||
asm: arm.ACMP,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 31}, // R0 R1 R2 R3 SP
|
||||
{1, 31}, // R0 R1 R2 R3 SP
|
||||
},
|
||||
outputs: []regMask{
|
||||
32, // FLAGS
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVWload",
|
||||
argLen: 2,
|
||||
asm: arm.AMOVW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 31}, // R0 R1 R2 R3 SP
|
||||
},
|
||||
outputs: []regMask{
|
||||
31, // R0 R1 R2 R3 SP
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVWstore",
|
||||
argLen: 3,
|
||||
asm: arm.AMOVW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 31}, // R0 R1 R2 R3 SP
|
||||
{1, 31}, // R0 R1 R2 R3 SP
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CALLstatic",
|
||||
auxType: auxSymOff,
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
clobbers: 15, // R0 R1 R2 R3
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "LessThan",
|
||||
argLen: 2,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 32}, // FLAGS
|
||||
},
|
||||
outputs: []regMask{
|
||||
31, // R0 R1 R2 R3 SP
|
||||
},
|
||||
},
|
||||
},
|
||||
|
||||
{
|
||||
name: "Add8",
|
||||
argLen: 2,
|
||||
@ -5343,3 +5475,49 @@ var opcodeTable = [...]opInfo{
|
||||
|
||||
func (o Op) Asm() obj.As { return opcodeTable[o].asm }
|
||||
func (o Op) String() string { return opcodeTable[o].name }
|
||||
|
||||
var registersAMD64 = [...]Register{
|
||||
{0, "AX"},
|
||||
{1, "CX"},
|
||||
{2, "DX"},
|
||||
{3, "BX"},
|
||||
{4, "SP"},
|
||||
{5, "BP"},
|
||||
{6, "SI"},
|
||||
{7, "DI"},
|
||||
{8, "R8"},
|
||||
{9, "R9"},
|
||||
{10, "R10"},
|
||||
{11, "R11"},
|
||||
{12, "R12"},
|
||||
{13, "R13"},
|
||||
{14, "R14"},
|
||||
{15, "R15"},
|
||||
{16, "X0"},
|
||||
{17, "X1"},
|
||||
{18, "X2"},
|
||||
{19, "X3"},
|
||||
{20, "X4"},
|
||||
{21, "X5"},
|
||||
{22, "X6"},
|
||||
{23, "X7"},
|
||||
{24, "X8"},
|
||||
{25, "X9"},
|
||||
{26, "X10"},
|
||||
{27, "X11"},
|
||||
{28, "X12"},
|
||||
{29, "X13"},
|
||||
{30, "X14"},
|
||||
{31, "X15"},
|
||||
{32, "SB"},
|
||||
{33, "FLAGS"},
|
||||
}
|
||||
var registersARM = [...]Register{
|
||||
{0, "R0"},
|
||||
{1, "R1"},
|
||||
{2, "R2"},
|
||||
{3, "R3"},
|
||||
{4, "SP"},
|
||||
{5, "FLAGS"},
|
||||
{6, "SB"},
|
||||
}
|
||||
|
||||
@ -129,10 +129,11 @@ type regMask uint64
|
||||
|
||||
func (m regMask) String() string {
|
||||
s := ""
|
||||
for r := register(0); r < numRegs; r++ {
|
||||
for r := register(0); m != 0; r++ {
|
||||
if m>>r&1 == 0 {
|
||||
continue
|
||||
}
|
||||
m &^= regMask(1) << r
|
||||
if s != "" {
|
||||
s += " "
|
||||
}
|
||||
@ -141,47 +142,6 @@ func (m regMask) String() string {
|
||||
return s
|
||||
}
|
||||
|
||||
// TODO: make arch-dependent
|
||||
var numRegs register = 64
|
||||
|
||||
var registers = [...]Register{
|
||||
Register{0, "AX"},
|
||||
Register{1, "CX"},
|
||||
Register{2, "DX"},
|
||||
Register{3, "BX"},
|
||||
Register{4, "SP"},
|
||||
Register{5, "BP"},
|
||||
Register{6, "SI"},
|
||||
Register{7, "DI"},
|
||||
Register{8, "R8"},
|
||||
Register{9, "R9"},
|
||||
Register{10, "R10"},
|
||||
Register{11, "R11"},
|
||||
Register{12, "R12"},
|
||||
Register{13, "R13"},
|
||||
Register{14, "R14"},
|
||||
Register{15, "R15"},
|
||||
Register{16, "X0"},
|
||||
Register{17, "X1"},
|
||||
Register{18, "X2"},
|
||||
Register{19, "X3"},
|
||||
Register{20, "X4"},
|
||||
Register{21, "X5"},
|
||||
Register{22, "X6"},
|
||||
Register{23, "X7"},
|
||||
Register{24, "X8"},
|
||||
Register{25, "X9"},
|
||||
Register{26, "X10"},
|
||||
Register{27, "X11"},
|
||||
Register{28, "X12"},
|
||||
Register{29, "X13"},
|
||||
Register{30, "X14"},
|
||||
Register{31, "X15"},
|
||||
Register{32, "SB"}, // pseudo-register for global base pointer (aka %rip)
|
||||
|
||||
// TODO: make arch-dependent
|
||||
}
|
||||
|
||||
// countRegs returns the number of set bits in the register mask.
|
||||
func countRegs(r regMask) int {
|
||||
n := 0
|
||||
@ -231,6 +191,11 @@ type regState struct {
|
||||
type regAllocState struct {
|
||||
f *Func
|
||||
|
||||
registers []Register
|
||||
numRegs register
|
||||
SPReg register
|
||||
SBReg register
|
||||
|
||||
// for each block, its primary predecessor.
|
||||
// A predecessor of b is primary if it is the closest
|
||||
// predecessor that appears before b in the layout order.
|
||||
@ -298,7 +263,7 @@ func (s *regAllocState) freeReg(r register) {
|
||||
|
||||
// Mark r as unused.
|
||||
if s.f.pass.debug > regDebug {
|
||||
fmt.Printf("freeReg %s (dump %s/%s)\n", registers[r].Name(), v, s.regs[r].c)
|
||||
fmt.Printf("freeReg %s (dump %s/%s)\n", s.registers[r].Name(), v, s.regs[r].c)
|
||||
}
|
||||
s.regs[r] = regState{}
|
||||
s.values[v.ID].regs &^= regMask(1) << r
|
||||
@ -328,7 +293,7 @@ func (s *regAllocState) setOrig(c *Value, v *Value) {
|
||||
// r must be unused.
|
||||
func (s *regAllocState) assignReg(r register, v *Value, c *Value) {
|
||||
if s.f.pass.debug > regDebug {
|
||||
fmt.Printf("assignReg %s %s/%s\n", registers[r].Name(), v, c)
|
||||
fmt.Printf("assignReg %s %s/%s\n", s.registers[r].Name(), v, c)
|
||||
}
|
||||
if s.regs[r].v != nil {
|
||||
s.f.Fatalf("tried to assign register %d to %s/%s but it is already used by %s", r, v, c, s.regs[r].v)
|
||||
@ -338,7 +303,7 @@ func (s *regAllocState) assignReg(r register, v *Value, c *Value) {
|
||||
s.regs[r] = regState{v, c}
|
||||
s.values[v.ID].regs |= regMask(1) << r
|
||||
s.used |= regMask(1) << r
|
||||
s.f.setHome(c, ®isters[r])
|
||||
s.f.setHome(c, &s.registers[r])
|
||||
}
|
||||
|
||||
// allocReg chooses a register for v from the set of registers in mask.
|
||||
@ -377,14 +342,14 @@ func (s *regAllocState) allocReg(v *Value, mask regMask) register {
|
||||
|
||||
// SP and SB are allocated specially. No regular value should
|
||||
// be allocated to them.
|
||||
mask &^= 1<<4 | 1<<32
|
||||
mask &^= 1<<s.SPReg | 1<<s.SBReg
|
||||
|
||||
// Find a register to spill. We spill the register containing the value
|
||||
// whose next use is as far in the future as possible.
|
||||
// https://en.wikipedia.org/wiki/Page_replacement_algorithm#The_theoretically_optimal_page_replacement_algorithm
|
||||
var r register
|
||||
maxuse := int32(-1)
|
||||
for t := register(0); t < numRegs; t++ {
|
||||
for t := register(0); t < s.numRegs; t++ {
|
||||
if mask>>t&1 == 0 {
|
||||
continue
|
||||
}
|
||||
@ -425,10 +390,10 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, line
|
||||
}
|
||||
|
||||
if v.Op != OpSP {
|
||||
mask &^= 1 << 4 // dont' spill SP
|
||||
mask &^= 1 << s.SPReg // dont' spill SP
|
||||
}
|
||||
if v.Op != OpSB {
|
||||
mask &^= 1 << 32 // don't spill SB
|
||||
mask &^= 1 << s.SBReg // don't spill SB
|
||||
}
|
||||
mask &^= s.reserved()
|
||||
|
||||
@ -469,12 +434,22 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, line
|
||||
}
|
||||
|
||||
func (s *regAllocState) init(f *Func) {
|
||||
if numRegs > noRegister || numRegs > register(unsafe.Sizeof(regMask(0))*8) {
|
||||
s.registers = f.Config.registers
|
||||
s.numRegs = register(len(s.registers))
|
||||
if s.numRegs > noRegister || s.numRegs > register(unsafe.Sizeof(regMask(0))*8) {
|
||||
panic("too many registers")
|
||||
}
|
||||
for r := register(0); r < s.numRegs; r++ {
|
||||
if s.registers[r].Name() == "SP" {
|
||||
s.SPReg = r
|
||||
}
|
||||
if s.registers[r].Name() == "SB" {
|
||||
s.SBReg = r
|
||||
}
|
||||
}
|
||||
|
||||
s.f = f
|
||||
s.regs = make([]regState, numRegs)
|
||||
s.regs = make([]regState, s.numRegs)
|
||||
s.values = make([]valState, f.NumValues())
|
||||
s.orig = make([]*Value, f.NumValues())
|
||||
for _, b := range f.Blocks {
|
||||
@ -663,7 +638,7 @@ func (s *regAllocState) regalloc(f *Func) {
|
||||
// Drop any values which are no longer live.
|
||||
// This may happen because at the end of p, a value may be
|
||||
// live but only used by some other successor of p.
|
||||
for r := register(0); r < numRegs; r++ {
|
||||
for r := register(0); r < s.numRegs; r++ {
|
||||
v := s.regs[r].v
|
||||
if v != nil && !liveSet.contains(v.ID) {
|
||||
s.freeReg(r)
|
||||
@ -687,7 +662,7 @@ func (s *regAllocState) regalloc(f *Func) {
|
||||
if s.f.pass.debug > regDebug {
|
||||
fmt.Printf("starting merge block %s with end state of %s:\n", b, p)
|
||||
for _, x := range s.endRegs[p.ID] {
|
||||
fmt.Printf(" %s: orig:%s cache:%s\n", registers[x.r].Name(), x.v, x.c)
|
||||
fmt.Printf(" %s: orig:%s cache:%s\n", s.registers[x.r].Name(), x.v, x.c)
|
||||
}
|
||||
}
|
||||
|
||||
@ -769,7 +744,7 @@ func (s *regAllocState) regalloc(f *Func) {
|
||||
|
||||
// Save the starting state for use by merge edges.
|
||||
var regList []startReg
|
||||
for r := register(0); r < numRegs; r++ {
|
||||
for r := register(0); r < s.numRegs; r++ {
|
||||
v := s.regs[r].v
|
||||
if v == nil {
|
||||
continue
|
||||
@ -786,7 +761,7 @@ func (s *regAllocState) regalloc(f *Func) {
|
||||
if s.f.pass.debug > regDebug {
|
||||
fmt.Printf("after phis\n")
|
||||
for _, x := range s.startRegs[b.ID] {
|
||||
fmt.Printf(" %s: v%d\n", registers[x.r].Name(), x.vid)
|
||||
fmt.Printf(" %s: v%d\n", s.registers[x.r].Name(), x.vid)
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -866,13 +841,13 @@ func (s *regAllocState) regalloc(f *Func) {
|
||||
f.Fatalf("phi %s not at start of block", v)
|
||||
}
|
||||
if v.Op == OpSP {
|
||||
s.assignReg(4, v, v) // TODO: arch-dependent
|
||||
s.assignReg(s.SPReg, v, v)
|
||||
b.Values = append(b.Values, v)
|
||||
s.advanceUses(v)
|
||||
continue
|
||||
}
|
||||
if v.Op == OpSB {
|
||||
s.assignReg(32, v, v) // TODO: arch-dependent
|
||||
s.assignReg(s.SBReg, v, v)
|
||||
b.Values = append(b.Values, v)
|
||||
s.advanceUses(v)
|
||||
continue
|
||||
@ -1030,7 +1005,7 @@ func (s *regAllocState) regalloc(f *Func) {
|
||||
// Save end-of-block register state.
|
||||
// First count how many, this cuts allocations in half.
|
||||
k := 0
|
||||
for r := register(0); r < numRegs; r++ {
|
||||
for r := register(0); r < s.numRegs; r++ {
|
||||
v := s.regs[r].v
|
||||
if v == nil {
|
||||
continue
|
||||
@ -1038,7 +1013,7 @@ func (s *regAllocState) regalloc(f *Func) {
|
||||
k++
|
||||
}
|
||||
regList := make([]endReg, 0, k)
|
||||
for r := register(0); r < numRegs; r++ {
|
||||
for r := register(0); r < s.numRegs; r++ {
|
||||
v := s.regs[r].v
|
||||
if v == nil {
|
||||
continue
|
||||
@ -1053,7 +1028,7 @@ func (s *regAllocState) regalloc(f *Func) {
|
||||
for _, x := range s.live[b.ID] {
|
||||
liveSet.add(x.ID)
|
||||
}
|
||||
for r := register(0); r < numRegs; r++ {
|
||||
for r := register(0); r < s.numRegs; r++ {
|
||||
v := s.regs[r].v
|
||||
if v == nil {
|
||||
continue
|
||||
@ -1214,7 +1189,7 @@ func (e *edgeState) setup(idx int, srcReg []endReg, dstReg []startReg, stacklive
|
||||
|
||||
// Live registers can be sources.
|
||||
for _, x := range srcReg {
|
||||
e.set(®isters[x.r], x.v.ID, x.c, false)
|
||||
e.set(&e.s.registers[x.r], x.v.ID, x.c, false)
|
||||
}
|
||||
// So can all of the spill locations.
|
||||
for _, spillID := range stacklive {
|
||||
@ -1226,7 +1201,7 @@ func (e *edgeState) setup(idx int, srcReg []endReg, dstReg []startReg, stacklive
|
||||
// Figure out all the destinations we need.
|
||||
dsts := e.destinations[:0]
|
||||
for _, x := range dstReg {
|
||||
dsts = append(dsts, dstRecord{®isters[x.r], x.vid, nil})
|
||||
dsts = append(dsts, dstRecord{&e.s.registers[x.r], x.vid, nil})
|
||||
}
|
||||
// Phis need their args to end up in a specific location.
|
||||
for _, v := range e.b.Values {
|
||||
@ -1519,15 +1494,15 @@ func (e *edgeState) findRegFor(typ Type) Location {
|
||||
// 3) a non-unique register
|
||||
x := m &^ e.usedRegs
|
||||
if x != 0 {
|
||||
return ®isters[pickReg(x)]
|
||||
return &e.s.registers[pickReg(x)]
|
||||
}
|
||||
x = m &^ e.uniqueRegs &^ e.finalRegs
|
||||
if x != 0 {
|
||||
return ®isters[pickReg(x)]
|
||||
return &e.s.registers[pickReg(x)]
|
||||
}
|
||||
x = m &^ e.uniqueRegs
|
||||
if x != 0 {
|
||||
return ®isters[pickReg(x)]
|
||||
return &e.s.registers[pickReg(x)]
|
||||
}
|
||||
|
||||
// No register is available. Allocate a temp location to spill a register to.
|
||||
|
||||
294
src/cmd/compile/internal/ssa/rewriteARM.go
Normal file
294
src/cmd/compile/internal/ssa/rewriteARM.go
Normal file
@ -0,0 +1,294 @@
|
||||
// autogenerated from gen/ARM.rules: do not edit!
|
||||
// generated with: cd gen; go run *.go
|
||||
|
||||
package ssa
|
||||
|
||||
import "math"
|
||||
|
||||
var _ = math.MinInt8 // in case not otherwise used
|
||||
func rewriteValueARM(v *Value, config *Config) bool {
|
||||
switch v.Op {
|
||||
case OpARMADD:
|
||||
return rewriteValueARM_OpARMADD(v, config)
|
||||
case OpAdd32:
|
||||
return rewriteValueARM_OpAdd32(v, config)
|
||||
case OpAddr:
|
||||
return rewriteValueARM_OpAddr(v, config)
|
||||
case OpConst32:
|
||||
return rewriteValueARM_OpConst32(v, config)
|
||||
case OpLess32:
|
||||
return rewriteValueARM_OpLess32(v, config)
|
||||
case OpLoad:
|
||||
return rewriteValueARM_OpLoad(v, config)
|
||||
case OpARMMOVWload:
|
||||
return rewriteValueARM_OpARMMOVWload(v, config)
|
||||
case OpARMMOVWstore:
|
||||
return rewriteValueARM_OpARMMOVWstore(v, config)
|
||||
case OpOffPtr:
|
||||
return rewriteValueARM_OpOffPtr(v, config)
|
||||
case OpStaticCall:
|
||||
return rewriteValueARM_OpStaticCall(v, config)
|
||||
case OpStore:
|
||||
return rewriteValueARM_OpStore(v, config)
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpARMADD(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (ADD (MOVWconst [c]) x)
|
||||
// cond:
|
||||
// result: (ADDconst [c] x)
|
||||
for {
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
c := v_0.AuxInt
|
||||
x := v.Args[1]
|
||||
v.reset(OpARMADDconst)
|
||||
v.AuxInt = c
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (ADD x (MOVWconst [c]))
|
||||
// cond:
|
||||
// result: (ADDconst [c] x)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
v_1 := v.Args[1]
|
||||
if v_1.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
c := v_1.AuxInt
|
||||
v.reset(OpARMADDconst)
|
||||
v.AuxInt = c
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpAdd32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Add32 x y)
|
||||
// cond:
|
||||
// result: (ADD x y)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMADD)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpAddr(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Addr {sym} base)
|
||||
// cond:
|
||||
// result: (ADDconst {sym} base)
|
||||
for {
|
||||
sym := v.Aux
|
||||
base := v.Args[0]
|
||||
v.reset(OpARMADDconst)
|
||||
v.Aux = sym
|
||||
v.AddArg(base)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpConst32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Const32 [val])
|
||||
// cond:
|
||||
// result: (MOVWconst [val])
|
||||
for {
|
||||
val := v.AuxInt
|
||||
v.reset(OpARMMOVWconst)
|
||||
v.AuxInt = val
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpLess32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Less32 x y)
|
||||
// cond:
|
||||
// result: (LessThan (CMP x y))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMLessThan)
|
||||
v0 := b.NewValue0(v.Line, OpARMCMP, TypeFlags)
|
||||
v0.AddArg(x)
|
||||
v0.AddArg(y)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpLoad(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Load <t> ptr mem)
|
||||
// cond: is32BitInt(t)
|
||||
// result: (MOVWload ptr mem)
|
||||
for {
|
||||
t := v.Type
|
||||
ptr := v.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(is32BitInt(t)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMMOVWload)
|
||||
v.AddArg(ptr)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpARMMOVWload(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVWload [off1] {sym1} (ADDconst [off2] {sym2} ptr) mem)
|
||||
// cond: canMergeSym(sym1,sym2)
|
||||
// result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpARMADDconst {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
sym2 := v_0.Aux
|
||||
ptr := v_0.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(canMergeSym(sym1, sym2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMMOVWload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(ptr)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpARMMOVWstore(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVWstore [off1] {sym1} (ADDconst [off2] {sym2} ptr) val mem)
|
||||
// cond: canMergeSym(sym1,sym2)
|
||||
// result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpARMADDconst {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
sym2 := v_0.Aux
|
||||
ptr := v_0.Args[0]
|
||||
val := v.Args[1]
|
||||
mem := v.Args[2]
|
||||
if !(canMergeSym(sym1, sym2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMMOVWstore)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(ptr)
|
||||
v.AddArg(val)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpOffPtr(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (OffPtr [off] ptr)
|
||||
// cond:
|
||||
// result: (ADD (MOVWconst <config.Frontend().TypeInt32()> [off]) ptr)
|
||||
for {
|
||||
off := v.AuxInt
|
||||
ptr := v.Args[0]
|
||||
v.reset(OpARMADD)
|
||||
v0 := b.NewValue0(v.Line, OpARMMOVWconst, config.Frontend().TypeInt32())
|
||||
v0.AuxInt = off
|
||||
v.AddArg(v0)
|
||||
v.AddArg(ptr)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpStaticCall(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (StaticCall [argwid] {target} mem)
|
||||
// cond:
|
||||
// result: (CALLstatic [argwid] {target} mem)
|
||||
for {
|
||||
argwid := v.AuxInt
|
||||
target := v.Aux
|
||||
mem := v.Args[0]
|
||||
v.reset(OpARMCALLstatic)
|
||||
v.AuxInt = argwid
|
||||
v.Aux = target
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpStore(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Store [4] ptr val mem)
|
||||
// cond:
|
||||
// result: (MOVWstore ptr val mem)
|
||||
for {
|
||||
if v.AuxInt != 4 {
|
||||
break
|
||||
}
|
||||
ptr := v.Args[0]
|
||||
val := v.Args[1]
|
||||
mem := v.Args[2]
|
||||
v.reset(OpARMMOVWstore)
|
||||
v.AddArg(ptr)
|
||||
v.AddArg(val)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteBlockARM(b *Block) bool {
|
||||
switch b.Kind {
|
||||
case BlockIf:
|
||||
// match: (If (LessThan cc) yes no)
|
||||
// cond:
|
||||
// result: (LT cc yes no)
|
||||
for {
|
||||
v := b.Control
|
||||
if v.Op != OpARMLessThan {
|
||||
break
|
||||
}
|
||||
cc := v.Args[0]
|
||||
yes := b.Succs[0]
|
||||
no := b.Succs[1]
|
||||
b.Kind = BlockARMLT
|
||||
b.SetControl(cc)
|
||||
b.Succs[0] = yes
|
||||
b.Succs[1] = no
|
||||
return true
|
||||
}
|
||||
}
|
||||
return false
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user