diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s index 1bb52e997d..f833ab62ad 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64.s @@ -937,6 +937,230 @@ start: VNCLIPWI $16, V2, V3 // d73128be VNCLIPWI $16, V2, V0, V3 // d73128bc + // 31.13.2: Vector Single-Width Floating-Point Add/Subtract Instructions + VFADDVV V1, V2, V3 // d7912002 + VFADDVV V1, V2, V0, V3 // d7912000 + VFADDVF F10, V2, V3 // d7512502 + VFADDVF F10, V2, V0, V3 // d7512500 + VFSUBVV V1, V2, V3 // d791200a + VFSUBVV V1, V2, V0, V3 // d7912008 + VFSUBVF F10, V2, V3 // d751250a + VFSUBVF F10, V2, V0, V3 // d7512508 + VFRSUBVF F10, V2, V3 // d751259e + VFRSUBVF F10, V2, V0, V3 // d751259c + + // 31.13.3: Vector Widening Floating-Point Add/Subtract Instructions + VFWADDVV V1, V2, V3 // d79120c2 + VFWADDVV V1, V2, V0, V3 // d79120c0 + VFWADDVF F10, V2, V3 // d75125c2 + VFWADDVF F10, V2, V0, V3 // d75125c0 + VFWSUBVV V1, V2, V3 // d79120ca + VFWSUBVV V1, V2, V0, V3 // d79120c8 + VFWSUBVF F10, V2, V3 // d75125ca + VFWSUBVF F10, V2, V0, V3 // d75125c8 + VFWADDWV V1, V2, V3 // d79120d2 + VFWADDWV V1, V2, V0, V3 // d79120d0 + VFWADDWF F10, V2, V3 // d75125d2 + VFWADDWF F10, V2, V0, V3 // d75125d0 + VFWSUBWV V1, V2, V3 // d79120da + VFWSUBWV V1, V2, V0, V3 // d79120d8 + VFWSUBWF F10, V2, V3 // d75125da + VFWSUBWF F10, V2, V0, V3 // d75125d8 + + // 31.13.4: Vector Single-Width Floating-Point Multiply/Divide Instructions + VFMULVV V1, V2, V3 // d7912092 + VFMULVV V1, V2, V0, V3 // d7912090 + VFMULVF F10, V2, V3 // d7512592 + VFMULVF F10, V2, V0, V3 // d7512590 + VFDIVVV V1, V2, V3 // d7912082 + VFDIVVV V1, V2, V0, V3 // d7912080 + VFDIVVF F10, V2, V3 // d7512582 + VFDIVVF F10, V2, V0, V3 // d7512580 + VFRDIVVF F10, V2, V3 // d7512586 + VFRDIVVF F10, V2, V0, V3 // d7512584 + + // 31.13.5: Vector Widening Floating-Point Multiply + VFWMULVV V1, V2, V3 // d79120e2 + VFWMULVV V1, V2, V0, V3 // d79120e0 + VFWMULVF F10, V2, V3 // d75125e2 + VFWMULVF F10, V2, V0, V3 // d75125e0 + + // 31.13.6: Vector Single-Width Floating-Point Fused Multiply-Add Instructions + VFMACCVV V2, V1, V3 // d79120b2 + VFMACCVV V2, V1, V0, V3 // d79120b0 + VFMACCVF V2, F10, V3 // d75125b2 + VFMACCVF V2, F10, V0, V3 // d75125b0 + VFNMACCVV V2, V1, V3 // d79120b6 + VFNMACCVV V2, V1, V0, V3 // d79120b4 + VFNMACCVF V2, F10, V3 // d75125b6 + VFNMACCVF V2, F10, V0, V3 // d75125b4 + VFMSACVV V2, V1, V3 // d79120ba + VFMSACVV V2, V1, V0, V3 // d79120b8 + VFMSACVF V2, F10, V3 // d75125ba + VFMSACVF V2, F10, V0, V3 // d75125b8 + VFNMSACVV V2, V1, V3 // d79120be + VFNMSACVV V2, V1, V0, V3 // d79120bc + VFNMSACVF V2, F10, V3 // d75125be + VFNMSACVF V2, F10, V0, V3 // d75125bc + VFMADDVV V2, V1, V3 // d79120a2 + VFMADDVV V2, V1, V0, V3 // d79120a0 + VFMADDVF V2, F10, V3 // d75125a2 + VFMADDVF V2, F10, V0, V3 // d75125a0 + VFNMADDVV V2, V1, V3 // d79120a6 + VFNMADDVV V2, V1, V0, V3 // d79120a4 + VFNMADDVF V2, F10, V3 // d75125a6 + VFNMADDVF V2, F10, V0, V3 // d75125a4 + VFMSUBVV V2, V1, V3 // d79120aa + VFMSUBVV V2, V1, V0, V3 // d79120a8 + VFMSUBVF V2, F10, V3 // d75125aa + VFMSUBVF V2, F10, V0, V3 // d75125a8 + VFNMSUBVV V2, V1, V3 // d79120ae + VFNMSUBVV V2, V1, V0, V3 // d79120ac + VFNMSUBVF V2, F10, V3 // d75125ae + VFNMSUBVF V2, F10, V0, V3 // d75125ac + + // 31.13.7: Vector Widening Floating-Point Fused Multiply-Add Instructions + VFWMACCVV V2, V1, V3 // d79120f2 + VFWMACCVV V2, V1, V0, V3 // d79120f0 + VFWMACCVF V2, F10, V3 // d75125f2 + VFWMACCVF V2, F10, V0, V3 // d75125f0 + VFWNMACCVV V2, V1, V3 // d79120f6 + VFWNMACCVV V2, V1, V0, V3 // d79120f4 + VFWNMACCVF V2, F10, V3 // d75125f6 + VFWNMACCVF V2, F10, V0, V3 // d75125f4 + VFWMSACVV V2, V1, V3 // d79120fa + VFWMSACVV V2, V1, V0, V3 // d79120f8 + VFWMSACVF V2, F10, V3 // d75125fa + VFWMSACVF V2, F10, V0, V3 // d75125f8 + VFWNMSACVV V2, V1, V3 // d79120fe + VFWNMSACVV V2, V1, V0, V3 // d79120fc + VFWNMSACVF V2, F10, V3 // d75125fe + VFWNMSACVF V2, F10, V0, V3 // d75125fc + + // 31.13.8: Vector Floating-Point Square-Root Instruction + VFSQRTV V2, V3 // d711204e + VFSQRTV V2, V0, V3 // d711204c + + // 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction + VFRSQRT7V V2, V3 // d711224e + VFRSQRT7V V2, V0, V3 // d711224c + + // 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction + VFREC7V V2, V3 // d791224e + VFREC7V V2, V0, V3 // d791224c + + // 31.13.11: Vector Floating-Point MIN/MAX Instructions + VFMINVV V1, V2, V3 // d7912012 + VFMINVV V1, V2, V0, V3 // d7912010 + VFMINVF F10, V2, V3 // d7512512 + VFMINVF F10, V2, V0, V3 // d7512510 + VFMAXVV V1, V2, V3 // d791201a + VFMAXVV V1, V2, V0, V3 // d7912018 + VFMAXVF F10, V2, V3 // d751251a + VFMAXVF F10, V2, V0, V3 // d7512518 + + // 31.13.12: Vector Floating-Point Sign-Injection Instructions + VFSGNJVV V1, V2, V3 // d7912022 + VFSGNJVV V1, V2, V0, V3 // d7912020 + VFSGNJVF F10, V2, V3 // d7512522 + VFSGNJVF F10, V2, V0, V3 // d7512520 + VFSGNJNVV V1, V2, V3 // d7912026 + VFSGNJNVV V1, V2, V0, V3 // d7912024 + VFSGNJNVF F10, V2, V3 // d7512526 + VFSGNJNVF F10, V2, V0, V3 // d7512524 + VFSGNJXVV V1, V2, V3 // d791202a + VFSGNJXVV V1, V2, V0, V3 // d7912028 + VFSGNJXVF F10, V2, V3 // d751252a + VFSGNJXVF F10, V2, V0, V3 // d7512528 + VFNEGV V2, V3 // d7112126 + VFNEGV V2, V0, V3 // d7112124 + VFABSV V2, V3 // d711212a + VFABSV V2, V0, V3 // d7112128 + + // 31.13.13: Vector Floating-Point Compare Instructions + VMFEQVV V1, V2, V3 // d7912062 + VMFEQVV V1, V2, V0, V3 // d7912060 + VMFEQVF F10, V2, V3 // d7512562 + VMFEQVF F10, V2, V0, V3 // d7512560 + VMFNEVV V1, V2, V3 // d7912072 + VMFNEVV V1, V2, V0, V3 // d7912070 + VMFNEVF F10, V2, V3 // d7512572 + VMFNEVF F10, V2, V0, V3 // d7512570 + VMFLTVV V1, V2, V3 // d791206e + VMFLTVV V1, V2, V0, V3 // d791206c + VMFLTVF F10, V2, V3 // d751256e + VMFLTVF F10, V2, V0, V3 // d751256c + VMFLEVV V1, V2, V3 // d7912066 + VMFLEVV V1, V2, V0, V3 // d7912064 + VMFLEVF F10, V2, V3 // d7512566 + VMFLEVF F10, V2, V0, V3 // d7512564 + VMFGTVF F10, V2, V3 // d7512576 + VMFGTVF F10, V2, V0, V3 // d7512574 + VMFGEVF F10, V2, V3 // d751257e + VMFGEVF F10, V2, V0, V3 // d751257c + VMFGTVV V1, V2, V3 // d711116e + VMFGTVV V1, V2, V0, V3 // d711116c + VMFGEVV V1, V2, V3 // d7111166 + VMFGEVV V1, V2, V0, V3 // d7111164 + + // 31.13.14: Vector Floating-Point Classify Instruction + VFCLASSV V2, V3 // d711284e + VFCLASSV V2, V0, V3 // d711284c + + // 31.13.15: Vector Floating-Point Merge Instruction + VFMERGEVFM F10, V2, V0, V3 // d751255c + + // 31.13.16: Vector Floating-Point Move Instruction + VFMVVF F10, V3 // d751055e + + // 31.13.17: Single-Width Floating-Point/Integer Type-Convert Instructions + VFCVTXUFV V2, V3 // d711204a + VFCVTXUFV V2, V0, V3 // d7112048 + VFCVTXFV V2, V3 // d791204a + VFCVTXFV V2, V0, V3 // d7912048 + VFCVTRTZXUFV V2, V3 // d711234a + VFCVTRTZXUFV V2, V0, V3 // d7112348 + VFCVTRTZXFV V2, V3 // d791234a + VFCVTRTZXFV V2, V0, V3 // d7912348 + VFCVTFXUV V2, V3 // d711214a + VFCVTFXUV V2, V0, V3 // d7112148 + VFCVTFXV V2, V3 // d791214a + VFCVTFXV V2, V0, V3 // d7912148 + + // 31.13.18: Widening Floating-Point/Integer Type-Convert Instructions + VFWCVTXUFV V2, V3 // d711244a + VFWCVTXUFV V2, V0, V3 // d7112448 + VFWCVTXFV V2, V3 // d791244a + VFWCVTXFV V2, V0, V3 // d7912448 + VFWCVTRTZXUFV V2, V3 // d711274a + VFWCVTRTZXUFV V2, V0, V3 // d7112748 + VFWCVTRTZXFV V2, V3 // d791274a + VFWCVTRTZXFV V2, V0, V3 // d7912748 + VFWCVTFXUV V2, V3 // d711254a + VFWCVTFXUV V2, V0, V3 // d7112548 + VFWCVTFXV V2, V3 // d791254a + VFWCVTFXV V2, V0, V3 // d7912548 + VFWCVTFFV V2, V3 // d711264a + VFWCVTFFV V2, V0, V3 // d7112648 + + // 31.13.19: Narrowing Floating-Point/Integer Type-Convert Instructions + VFNCVTXUFW V2, V3 // d711284a + VFNCVTXUFW V2, V0, V3 // d7112848 + VFNCVTXFW V2, V3 // d791284a + VFNCVTXFW V2, V0, V3 // d7912848 + VFNCVTRTZXUFW V2, V3 // d7112b4a + VFNCVTRTZXUFW V2, V0, V3 // d7112b48 + VFNCVTRTZXFW V2, V3 // d7912b4a + VFNCVTRTZXFW V2, V0, V3 // d7912b48 + VFNCVTFXUW V2, V3 // d711294a + VFNCVTFXUW V2, V0, V3 // d7112948 + VFNCVTFXW V2, V3 // d791294a + VFNCVTFXW V2, V0, V3 // d7912948 + VFNCVTFFW V2, V3 // d7112a4a + VFNCVTFFW V2, V0, V3 // d7112a48 + VFNCVTRODFFW V2, V3 // d7912a4a + VFNCVTRODFFW V2, V0, V3 // d7912a48 + // // Privileged ISA // diff --git a/src/cmd/asm/internal/asm/testdata/riscv64error.s b/src/cmd/asm/internal/asm/testdata/riscv64error.s index 6a7c9b9444..3aeeadf848 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64error.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64error.s @@ -50,208 +50,302 @@ TEXT errors(SB),$0 // // "V" Standard Extension for Vector Operations, Version 1.0 // - VSETIVLI X10, E32, M2, TA, MA, X12 // ERROR "expected immediate value" - VLE8V (X10), V1, V3 // ERROR "invalid vector mask register" - VSE8V V3, V1, (X10) // ERROR "invalid vector mask register" - VLSE8V (X10), X10, V1, V3 // ERROR "invalid vector mask register" - VSSE8V V3, X11, V1, (X10) // ERROR "invalid vector mask register" - VLUXEI8V (X10), V2, V1, V3 // ERROR "invalid vector mask register" - VSUXEI8V V3, V2, V1, (X10) // ERROR "invalid vector mask register" - VLOXEI8V (X10), V2, V1, V3 // ERROR "invalid vector mask register" - VSOXEI8V V3, V2, V1, (X10) // ERROR "invalid vector mask register" - VL1RV (X10), V0, V3 // ERROR "too many operands for instruction" - VS1RV V3, V0, (X11) // ERROR "too many operands for instruction" - VADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VADDVX X10, V2, V1, V3 // ERROR "invalid vector mask register" - VADDVI $15, V4, V1, V2 // ERROR "invalid vector mask register" - VSUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSUBVX X10, V2, V1, V3 // ERROR "invalid vector mask register" - VRSUBVX X10, V2, V1, V3 // ERROR "invalid vector mask register" - VRSUBVI $15, V4, V1, V2 // ERROR "invalid vector mask register" - VNEGV V2, V3, V4 // ERROR "invalid vector mask register" - VWADDUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWADDUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWSUBUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWSUBUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWADDVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWSUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWSUBVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWADDUWV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWADDUWX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWSUBUWV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWSUBUWX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWADDWV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWADDWX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWSUBWV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWSUBWX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWCVTXXV V2, V1, V3 // ERROR "invalid vector mask register" - VWCVTUXXV V2, V1, V3 // ERROR "invalid vector mask register" - VZEXTVF2 V2, V3, V4 // ERROR "invalid vector mask register" - VSEXTVF2 V2, V3, V4 // ERROR "invalid vector mask register" - VZEXTVF4 V2, V3, V4 // ERROR "invalid vector mask register" - VSEXTVF4 V2, V3, V4 // ERROR "invalid vector mask register" - VZEXTVF8 V2, V3, V4 // ERROR "invalid vector mask register" - VSEXTVF8 V2, V3, V4 // ERROR "invalid vector mask register" - VADCVVM V1, V2, V4, V3 // ERROR "invalid vector mask register" - VADCVVM V1, V2, V3 // ERROR "invalid vector mask register" - VADCVXM X10, V2, V4, V3 // ERROR "invalid vector mask register" - VADCVXM X10, V2, V3 // ERROR "invalid vector mask register" - VADCVIM $15, V2, V1, V3 // ERROR "invalid vector mask register" - VADCVIM $15, V2, V3 // ERROR "invalid vector mask register" - VMADCVVM V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMADCVVM V1, V2, V3 // ERROR "invalid vector mask register" - VMADCVXM X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMADCVXM X10, V2, V3 // ERROR "invalid vector mask register" - VMADCVIM $15, V2, V1, V3 // ERROR "invalid vector mask register" - VMADCVIM $15, V2, V3 // ERROR "invalid vector mask register" - VSBCVVM V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSBCVVM V1, V2, V3 // ERROR "invalid vector mask register" - VSBCVXM X10, V2, V4, V3 // ERROR "invalid vector mask register" - VSBCVXM X10, V2, V3 // ERROR "invalid vector mask register" - VMSBCVVM V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMSBCVVM V1, V2, V3 // ERROR "invalid vector mask register" - VMSBCVXM X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMSBCVXM X10, V2, V3 // ERROR "invalid vector mask register" - VANDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VANDVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VANDVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VORVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VORVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VORVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VXORVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VXORVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VXORVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VNOTV V1, V2, V3 // ERROR "invalid vector mask register" - VSLLVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSLLVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VSLLVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VSRLVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSRLVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VSRLVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VSRAVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSRAVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VSRAVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VNSRLWV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VNSRLWX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VNSRLWI $31, V2, V4, V3 // ERROR "invalid vector mask register" - VNSRAWV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VNSRAWX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VNSRAWI $31, V2, V4, V3 // ERROR "invalid vector mask register" - VNCVTXXW V2, V4, V3 // ERROR "invalid vector mask register" - VMSEQVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMSEQVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMSEQVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VMSNEVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMSNEVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMSNEVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLTUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLTUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLTVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLTVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLEUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLEUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLEUVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLEVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLEVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLEVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VMSGTUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMSGTUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMSGTUVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VMSGTVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMSGTVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMSGTVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VMSGEVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMSGEUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLTVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VMSLTUVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VMSGEVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VMSGEUVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VMINUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMINUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMINVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMINVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMAXUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMAXUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMAXVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMAXVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMULVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMULVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMULHVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMULHVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMULHUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMULHUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMULHSUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMULHSUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VDIVUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VDIVUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VDIVVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VDIVVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VREMUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VREMUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VREMVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VREMVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWMULVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWMULVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWMULUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWMULUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWMULSUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWMULSUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMACCVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMACCVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VNMSACVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VNMSACVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMADDVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VNMSUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VNMSUBVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWMACCUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWMACCUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWMACCVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWMACCVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWMACCSUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VWMACCSUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VWMACCUSVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMERGEVVM V1, V2, V3 // ERROR "invalid vector mask register" - VMERGEVVM V1, V2, V4, V3 // ERROR "invalid vector mask register" - VMERGEVXM X10, V2, V3 // ERROR "invalid vector mask register" - VMERGEVXM X10, V2, V4, V3 // ERROR "invalid vector mask register" - VMERGEVIM $15, V2, V3 // ERROR "invalid vector mask register" - VMERGEVIM $15, V2, V4, V3 // ERROR "invalid vector mask register" - VMVVV V1, V2, V3 // ERROR "too many operands for instruction" - VMVVX X10, V2, V3 // ERROR "too many operands for instruction" - VMVVI $15, V2, V3 // ERROR "too many operands for instruction" - VSADDUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSADDUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VSADDUVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VSADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSADDVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VSADDVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VSSUBUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSSUBUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VSSUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSSUBVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VAADDUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VAADDUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VAADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VAADDVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VASUBUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VASUBUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VASUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VASUBVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VSMULVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSMULVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VSSRLVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSSRLVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VSSRLVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VSSRAVV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VSSRAVX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VSSRAVI $15, V2, V4, V3 // ERROR "invalid vector mask register" - VNCLIPUWV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VNCLIPUWX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VNCLIPUWI $16, V2, V4, V3 // ERROR "invalid vector mask register" - VNCLIPWV V1, V2, V4, V3 // ERROR "invalid vector mask register" - VNCLIPWX X10, V2, V4, V3 // ERROR "invalid vector mask register" - VNCLIPWI $16, V2, V4, V3 // ERROR "invalid vector mask register" + VSETIVLI X10, E32, M2, TA, MA, X12 // ERROR "expected immediate value" + VLE8V (X10), V1, V3 // ERROR "invalid vector mask register" + VSE8V V3, V1, (X10) // ERROR "invalid vector mask register" + VLSE8V (X10), X10, V1, V3 // ERROR "invalid vector mask register" + VSSE8V V3, X11, V1, (X10) // ERROR "invalid vector mask register" + VLUXEI8V (X10), V2, V1, V3 // ERROR "invalid vector mask register" + VSUXEI8V V3, V2, V1, (X10) // ERROR "invalid vector mask register" + VLOXEI8V (X10), V2, V1, V3 // ERROR "invalid vector mask register" + VSOXEI8V V3, V2, V1, (X10) // ERROR "invalid vector mask register" + VL1RV (X10), V0, V3 // ERROR "too many operands for instruction" + VS1RV V3, V0, (X11) // ERROR "too many operands for instruction" + VADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VADDVX X10, V2, V1, V3 // ERROR "invalid vector mask register" + VADDVI $15, V4, V1, V2 // ERROR "invalid vector mask register" + VSUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSUBVX X10, V2, V1, V3 // ERROR "invalid vector mask register" + VRSUBVX X10, V2, V1, V3 // ERROR "invalid vector mask register" + VRSUBVI $15, V4, V1, V2 // ERROR "invalid vector mask register" + VNEGV V2, V3, V4 // ERROR "invalid vector mask register" + VWADDUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWADDUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWSUBUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWSUBUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWADDVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWSUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWSUBVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWADDUWV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWADDUWX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWSUBUWV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWSUBUWX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWADDWV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWADDWX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWSUBWV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWSUBWX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWCVTXXV V2, V1, V3 // ERROR "invalid vector mask register" + VWCVTUXXV V2, V1, V3 // ERROR "invalid vector mask register" + VZEXTVF2 V2, V3, V4 // ERROR "invalid vector mask register" + VSEXTVF2 V2, V3, V4 // ERROR "invalid vector mask register" + VZEXTVF4 V2, V3, V4 // ERROR "invalid vector mask register" + VSEXTVF4 V2, V3, V4 // ERROR "invalid vector mask register" + VZEXTVF8 V2, V3, V4 // ERROR "invalid vector mask register" + VSEXTVF8 V2, V3, V4 // ERROR "invalid vector mask register" + VADCVVM V1, V2, V4, V3 // ERROR "invalid vector mask register" + VADCVVM V1, V2, V3 // ERROR "invalid vector mask register" + VADCVXM X10, V2, V4, V3 // ERROR "invalid vector mask register" + VADCVXM X10, V2, V3 // ERROR "invalid vector mask register" + VADCVIM $15, V2, V1, V3 // ERROR "invalid vector mask register" + VADCVIM $15, V2, V3 // ERROR "invalid vector mask register" + VMADCVVM V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMADCVVM V1, V2, V3 // ERROR "invalid vector mask register" + VMADCVXM X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMADCVXM X10, V2, V3 // ERROR "invalid vector mask register" + VMADCVIM $15, V2, V1, V3 // ERROR "invalid vector mask register" + VMADCVIM $15, V2, V3 // ERROR "invalid vector mask register" + VSBCVVM V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSBCVVM V1, V2, V3 // ERROR "invalid vector mask register" + VSBCVXM X10, V2, V4, V3 // ERROR "invalid vector mask register" + VSBCVXM X10, V2, V3 // ERROR "invalid vector mask register" + VMSBCVVM V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMSBCVVM V1, V2, V3 // ERROR "invalid vector mask register" + VMSBCVXM X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMSBCVXM X10, V2, V3 // ERROR "invalid vector mask register" + VANDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VANDVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VANDVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VORVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VORVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VORVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VXORVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VXORVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VXORVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VNOTV V1, V2, V3 // ERROR "invalid vector mask register" + VSLLVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSLLVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VSLLVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VSRLVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSRLVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VSRLVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VSRAVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSRAVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VSRAVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VNSRLWV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VNSRLWX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VNSRLWI $31, V2, V4, V3 // ERROR "invalid vector mask register" + VNSRAWV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VNSRAWX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VNSRAWI $31, V2, V4, V3 // ERROR "invalid vector mask register" + VNCVTXXW V2, V4, V3 // ERROR "invalid vector mask register" + VMSEQVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMSEQVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMSEQVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VMSNEVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMSNEVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMSNEVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLTUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLTUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLTVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLTVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLEUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLEUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLEUVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLEVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLEVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLEVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VMSGTUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMSGTUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMSGTUVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VMSGTVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMSGTVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMSGTVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VMSGEVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMSGEUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLTVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VMSLTUVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VMSGEVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VMSGEUVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VMINUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMINUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMINVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMINVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMAXUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMAXUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMAXVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMAXVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMULVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMULVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMULHVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMULHVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMULHUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMULHUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMULHSUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMULHSUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VDIVUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VDIVUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VDIVVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VDIVVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VREMUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VREMUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VREMVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VREMVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWMULVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWMULVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWMULUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWMULUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWMULSUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWMULSUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMACCVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMACCVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VNMSACVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VNMSACVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMADDVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VNMSUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VNMSUBVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWMACCUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWMACCUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWMACCVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWMACCVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWMACCSUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VWMACCSUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VWMACCUSVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMERGEVVM V1, V2, V3 // ERROR "invalid vector mask register" + VMERGEVVM V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMERGEVXM X10, V2, V3 // ERROR "invalid vector mask register" + VMERGEVXM X10, V2, V4, V3 // ERROR "invalid vector mask register" + VMERGEVIM $15, V2, V3 // ERROR "invalid vector mask register" + VMERGEVIM $15, V2, V4, V3 // ERROR "invalid vector mask register" + VMVVV V1, V2, V3 // ERROR "too many operands for instruction" + VMVVX X10, V2, V3 // ERROR "too many operands for instruction" + VMVVI $15, V2, V3 // ERROR "too many operands for instruction" + VSADDUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSADDUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VSADDUVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VSADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSADDVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VSADDVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VSSUBUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSSUBUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VSSUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSSUBVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VAADDUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VAADDUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VAADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VAADDVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VASUBUVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VASUBUVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VASUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VASUBVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VSMULVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSMULVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VSSRLVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSSRLVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VSSRLVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VSSRAVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VSSRAVX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VSSRAVI $15, V2, V4, V3 // ERROR "invalid vector mask register" + VNCLIPUWV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VNCLIPUWX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VNCLIPUWI $16, V2, V4, V3 // ERROR "invalid vector mask register" + VNCLIPWV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VNCLIPWX X10, V2, V4, V3 // ERROR "invalid vector mask register" + VNCLIPWI $16, V2, V4, V3 // ERROR "invalid vector mask register" + VFADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFADDVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFSUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFSUBVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFRSUBVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFWADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFWADDVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFWSUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFWSUBVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFWADDWV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFWADDWF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFWSUBWV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFWSUBWF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFMULVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFMULVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFDIVVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFDIVVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFRDIVVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFWMULVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFWMULVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFMACCVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFMACCVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFNMACCVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFNMACCVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFMSACVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFMSACVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFNMSACVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFNMSACVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFMADDVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFMADDVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFNMADDVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFNMADDVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFMSUBVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFMSUBVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFNMSUBVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFNMSUBVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFWMACCVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFWMACCVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFWNMACCVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFWNMACCVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFWMSACVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFWMSACVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFWNMSACVV V2, V1, V4, V3 // ERROR "invalid vector mask register" + VFWNMSACVF V2, F10, V4, V3 // ERROR "invalid vector mask register" + VFSQRTV V2, V4, V3 // ERROR "invalid vector mask register" + VFRSQRT7V V2, V4, V3 // ERROR "invalid vector mask register" + VFREC7V V2, V4, V3 // ERROR "invalid vector mask register" + VFMINVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFMINVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFMAXVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFMAXVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFSGNJVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFSGNJVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFSGNJNVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFSGNJNVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFSGNJXVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFSGNJXVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFNEGV V2, V4, V3 // ERROR "invalid vector mask register" + VFABSV V2, V4, V3 // ERROR "invalid vector mask register" + VMFEQVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMFEQVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VMFNEVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMFNEVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VMFLTVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMFLTVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VMFLEVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMFLEVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VMFGTVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VMFGEVF F10, V2, V4, V3 // ERROR "invalid vector mask register" + VMFGTVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VMFGEVV V1, V2, V4, V3 // ERROR "invalid vector mask register" + VFMERGEVFM X10, V2, V3 // ERROR "invalid vector mask register" + VFMERGEVFM F10, V2, V4, V3 // ERROR "invalid vector mask register" + VFCVTXUFV V2, V4, V3 // ERROR "invalid vector mask register" + VFCVTXFV V2, V4, V3 // ERROR "invalid vector mask register" + VFCVTRTZXUFV V2, V4, V3 // ERROR "invalid vector mask register" + VFCVTRTZXFV V2, V4, V3 // ERROR "invalid vector mask register" + VFCVTFXUV V2, V4, V3 // ERROR "invalid vector mask register" + VFCVTFXV V2, V4, V3 // ERROR "invalid vector mask register" + VFWCVTXUFV V2, V4, V3 // ERROR "invalid vector mask register" + VFWCVTXFV V2, V4, V3 // ERROR "invalid vector mask register" + VFWCVTRTZXUFV V2, V4, V3 // ERROR "invalid vector mask register" + VFWCVTRTZXFV V2, V4, V3 // ERROR "invalid vector mask register" + VFWCVTFXUV V2, V4, V3 // ERROR "invalid vector mask register" + VFWCVTFXV V2, V4, V3 // ERROR "invalid vector mask register" + VFWCVTFFV V2, V4, V3 // ERROR "invalid vector mask register" + VFNCVTXUFW V2, V4, V3 // ERROR "invalid vector mask register" + VFNCVTXFW V2, V4, V3 // ERROR "invalid vector mask register" + VFNCVTRTZXUFW V2, V4, V3 // ERROR "invalid vector mask register" + VFNCVTRTZXFW V2, V4, V3 // ERROR "invalid vector mask register" + VFNCVTFXUW V2, V4, V3 // ERROR "invalid vector mask register" + VFNCVTFXW V2, V4, V3 // ERROR "invalid vector mask register" + VFNCVTFFW V2, V4, V3 // ERROR "invalid vector mask register" + VFNCVTRODFFW V2, V4, V3 // ERROR "invalid vector mask register" RET diff --git a/src/cmd/asm/internal/asm/testdata/riscv64validation.s b/src/cmd/asm/internal/asm/testdata/riscv64validation.s index c6f71e64fb..2c509a1e91 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64validation.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64validation.s @@ -15,259 +15,354 @@ TEXT validation(SB),$0 // // "V" Standard Extension for Vector Operations, Version 1.0 // - VSETVLI $32, E16, M1, TU, MU, X12 // ERROR "must be in range [0, 31] (5 bits)" - VSETVLI $-1, E32, M2, TA, MA, X12 // ERROR "must be in range [0, 31] (5 bits)" - VSETVL X10, X11 // ERROR "expected integer register in rs1 position" - VLE8V (X10), X10 // ERROR "expected vector register in vd position" - VLE8V (V1), V3 // ERROR "expected integer register in rs1 position" - VSE8V X10, (X10) // ERROR "expected vector register in vs1 position" - VSE8V V3, (V1) // ERROR "expected integer register in rd position" - VLSE8V (X10), V3 // ERROR "expected integer register in rs2 position" - VLSE8V (X10), X10, X11 // ERROR "expected vector register in vd position" - VLSE8V (V1), X10, V3 // ERROR "expected integer register in rs1 position" - VLSE8V (X10), V1, V0, V3 // ERROR "expected integer register in rs2 position" - VSSE8V V3, (X10) // ERROR "expected integer register in rs2 position" - VSSE8V X10, X11, (X10) // ERROR "expected vector register in vd position" - VSSE8V V3, X11, (V1) // ERROR "expected integer register in rs1 position" - VSSE8V V3, V1, V0, (X10) // ERROR "expected integer register in rs2 position" - VLUXEI8V (X10), V2, X11 // ERROR "expected vector register in vd position" - VLUXEI8V (X10), V2, X11 // ERROR "expected vector register in vd position" - VLUXEI8V (V1), V2, V3 // ERROR "expected integer register in rs1 position" - VLUXEI8V (X10), X11, V0, V3 // ERROR "expected vector register in vs2 position" - VSUXEI8V X10, V2, (X10) // ERROR "expected vector register in vd position" - VSUXEI8V V3, V2, (V1) // ERROR "expected integer register in rs1 position" - VSUXEI8V V3, X11, V0, (X10) // ERROR "expected vector register in vs2 position" - VLOXEI8V (X10), V2, X11 // ERROR "expected vector register in vd position" - VLOXEI8V (V1), V2, V3 // ERROR "expected integer register in rs1 position" - VLOXEI8V (X10), X11, V0, V3 // ERROR "expected vector register in vs2 position" - VSOXEI8V X10, V2, (X10) // ERROR "expected vector register in vd position" - VSOXEI8V V3, V2, (V1) // ERROR "expected integer register in rs1 position" - VSOXEI8V V3, X11, V0, (X10) // ERROR "expected vector register in vs2 position" - VL1RV (X10), X10 // ERROR "expected vector register in vd position" - VL1RV (V1), V3 // ERROR "expected integer register in rs1 position" - VS1RV X11, (X11) // ERROR "expected vector register in vs1 position" - VS1RV V3, (V1) // ERROR "expected integer register in rd position" - VADDVV V1, X10, V3 // ERROR "expected vector register in vs2 position" - VADDVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VADDVI $16, V4, V2 // ERROR "signed immediate 16 must be in range [-16, 15] (5 bits)" - VADDVI $-17, V4, V2 // ERROR "signed immediate -17 must be in range [-16, 15] (5 bits)" - VSUBVV V1, X10, V3 // ERROR "expected vector register in vs2 position" - VSUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VRSUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VRSUBVI $16, V4, V2 // ERROR "signed immediate 16 must be in range [-16, 15] (5 bits)" - VRSUBVI $-17, V4, V2 // ERROR "signed immediate -17 must be in range [-16, 15] (5 bits)" - VNEGV X10, V3 // ERROR "expected vector register in vs2 position" - VNEGV V2 // ERROR "expected vector register in vd position" - VWADDUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWADDUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWSUBUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWSUBUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWADDVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWADDVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWSUBVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWSUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWADDUWV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWADDUWX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWSUBUWV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWSUBUWX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWADDWV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWADDWX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWSUBWV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWSUBWX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWCVTXXV X10, V3 // ERROR "expected vector register in vs2 position" - VWCVTUXXV X10, V3 // ERROR "expected vector register in vs2 position" - VZEXTVF2 V2, V0, V3, V4 // ERROR "expected no register in rs3" - VZEXTVF2 X10, V3 // ERROR "expected vector register in vs2 position" - VSEXTVF2 V2, V0, V3, V4 // ERROR "expected no register in rs3" - VSEXTVF2 X10, V3 // ERROR "expected vector register in vs2 position" - VZEXTVF4 V2, V0, V3, V4 // ERROR "expected no register in rs3" - VZEXTVF4 X10, V3 // ERROR "expected vector register in vs2 position" - VSEXTVF4 V2, V0, V3, V4 // ERROR "expected no register in rs3" - VSEXTVF4 X10, V3 // ERROR "expected vector register in vs2 position" - VZEXTVF8 V2, V0, V3, V4 // ERROR "expected no register in rs3" - VZEXTVF8 X10, V3 // ERROR "expected vector register in vs2 position" - VSEXTVF8 V2, V0, V3, V4 // ERROR "expected no register in rs3" - VSEXTVF8 X10, V3 // ERROR "expected vector register in vs2 position" - VADCVVM X10, V2, V0, V3 // ERROR "expected vector register in vs1 position" - VADCVXM V1, V2, V0, V3 // ERROR "expected integer register in rs1 position" - VADCVIM $16, V2, V0, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VADCVIM $-17, V2, V0, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMADCVVM X10, V2, V0, V3 // ERROR "expected vector register in vs1 position" - VMADCVXM V1, V2, V0, V3 // ERROR "expected integer register in rs1 position" - VMADCVIM $16, V2, V0, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMADCVIM $-17, V2, V0, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMADCVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMADCVV V1, V2, V0, V3 // ERROR "expected no register in rs3" - VMADCVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMADCVX X10, V2, V0, V3 // ERROR "expected no register in rs3" - VMADCVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMADCVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMADCVI $15, V2, V0, V3 // ERROR "expected no register in rs3" - VSBCVVM X10, V2, V0, V3 // ERROR "expected vector register in vs1 position" - VSBCVXM V1, V2, V0, V3 // ERROR "expected integer register in rs1 position" - VMSBCVVM X10, V2, V0, V3 // ERROR "expected vector register in vs1 position" - VMSBCVXM V1, V2, V0, V3 // ERROR "expected integer register in rs1 position" - VMSBCVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMSBCVV V1, V2, V0, V3 // ERROR "expected no register in rs3" - VMSBCVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMSBCVX X10, V2, V0, V3 // ERROR "expected no register in rs3" - VANDVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VANDVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VANDVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VANDVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VORVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VORVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VORVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VORVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VXORVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VXORVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VXORVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VXORVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VNOTV V3 // ERROR "expected vector register in vd position" - VNOTV X10, V3 // ERROR "expected vector register in vs2 position" - VSLLVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VSLLVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VSLLVI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]" - VSLLVI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]" - VSRLVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VSRLVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VSRLVI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]" - VSRLVI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]" - VSRAVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VSRAVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VSRAVI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]" - VSRAVI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]" - VNSRLWV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VNSRLWX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VNSRLWI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]" - VNSRLWI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]" - VNSRAWV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VNSRAWX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VNSRAWI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]" - VNSRAWI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]" - VNCVTXXW X10, V3 // ERROR "expected vector register in vs2 position" - VMSEQVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMSEQVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMSEQVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMSEQVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMSNEVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMSNEVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMSNEVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMSNEVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMSLTUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMSLTUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMSLTVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMSLTVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMSLEUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMSLEUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMSLEUVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMSLEUVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMSLEVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMSLEVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMSLEVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMSLEVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMSGTUVV X10, V2, V3 // ERROR "expected vector register in vs2 position" - VMSGTUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMSGTUVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMSGTUVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMSGTVV X10, V2, V3 // ERROR "expected vector register in vs2 position" - VMSGTVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMSGTVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMSGTVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMSGEVV X10, V2, V3 // ERROR "expected vector register in vs2 position" - VMSGEUVV X10, V2, V3 // ERROR "expected vector register in vs2 position" - VMSLTVI $17, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMSLTVI $-16, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMSLTUVI $17, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMSLTUVI $-16, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMSGEVI $17, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMSGEVI $-16, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMSGEUVI $17, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMSGEUVI $-16, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMINUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMINUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMINVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMINVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMAXUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMAXUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMAXVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMAXVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMULVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMULVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMULHVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMULHVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMULHUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMULHUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMULHSUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMULHSUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VDIVUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VDIVUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VDIVVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VDIVVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VREMUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VREMUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VREMVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VREMVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWMULVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWMULVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWMULUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWMULUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWMULSUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWMULSUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMACCVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMACCVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VNMSACVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VNMSACVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMADDVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VMADDVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VNMSUBVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VNMSUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWMACCUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWMACCUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWMACCVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWMACCVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWMACCSUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VWMACCSUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VWMACCUSVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VMERGEVVM X10, V2, V0, V3 // ERROR "expected vector register in vs1 position" - VMERGEVXM V1, V2, V0, V3 // ERROR "expected integer register in rs1 position" - VMERGEVIM $16, V2, V0, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMERGEVIM $-17, V2, V0, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VMVVV X10, V3 // ERROR "expected vector register in vs1 position" - VMVVX V1, V2 // ERROR "expected integer register in rs1 position" - VMVVI $16, V2 // ERROR "signed immediate 16 must be in range [-16, 15]" - VMVVI $-17, V2 // ERROR "signed immediate -17 must be in range [-16, 15]" - VSADDUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VSADDUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VSADDUVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" - VSADDUVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" - VSSUBUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VSSUBUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VAADDUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VAADDUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VAADDVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VAADDVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VASUBUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VASUBUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VASUBVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VASUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VSMULVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VSMULVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VSSRLVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VSSRLVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VSSRLVI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]" - VSSRLVI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]" - VSSRAVV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VSSRAVX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VSSRAVI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]" - VSSRAVI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]" - VNCLIPUWV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VNCLIPUWX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VNCLIPUWI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]" - VNCLIPUWI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]" - VNCLIPWV X10, V2, V3 // ERROR "expected vector register in vs1 position" - VNCLIPWX V1, V2, V3 // ERROR "expected integer register in rs1 position" - VNCLIPWI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]" - VNCLIPWI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]" + VSETVLI $32, E16, M1, TU, MU, X12 // ERROR "must be in range [0, 31] (5 bits)" + VSETVLI $-1, E32, M2, TA, MA, X12 // ERROR "must be in range [0, 31] (5 bits)" + VSETVL X10, X11 // ERROR "expected integer register in rs1 position" + VLE8V (X10), X10 // ERROR "expected vector register in vd position" + VLE8V (V1), V3 // ERROR "expected integer register in rs1 position" + VSE8V X10, (X10) // ERROR "expected vector register in vs1 position" + VSE8V V3, (V1) // ERROR "expected integer register in rd position" + VLSE8V (X10), V3 // ERROR "expected integer register in rs2 position" + VLSE8V (X10), X10, X11 // ERROR "expected vector register in vd position" + VLSE8V (V1), X10, V3 // ERROR "expected integer register in rs1 position" + VLSE8V (X10), V1, V0, V3 // ERROR "expected integer register in rs2 position" + VSSE8V V3, (X10) // ERROR "expected integer register in rs2 position" + VSSE8V X10, X11, (X10) // ERROR "expected vector register in vd position" + VSSE8V V3, X11, (V1) // ERROR "expected integer register in rs1 position" + VSSE8V V3, V1, V0, (X10) // ERROR "expected integer register in rs2 position" + VLUXEI8V (X10), V2, X11 // ERROR "expected vector register in vd position" + VLUXEI8V (X10), V2, X11 // ERROR "expected vector register in vd position" + VLUXEI8V (V1), V2, V3 // ERROR "expected integer register in rs1 position" + VLUXEI8V (X10), X11, V0, V3 // ERROR "expected vector register in vs2 position" + VSUXEI8V X10, V2, (X10) // ERROR "expected vector register in vd position" + VSUXEI8V V3, V2, (V1) // ERROR "expected integer register in rs1 position" + VSUXEI8V V3, X11, V0, (X10) // ERROR "expected vector register in vs2 position" + VLOXEI8V (X10), V2, X11 // ERROR "expected vector register in vd position" + VLOXEI8V (V1), V2, V3 // ERROR "expected integer register in rs1 position" + VLOXEI8V (X10), X11, V0, V3 // ERROR "expected vector register in vs2 position" + VSOXEI8V X10, V2, (X10) // ERROR "expected vector register in vd position" + VSOXEI8V V3, V2, (V1) // ERROR "expected integer register in rs1 position" + VSOXEI8V V3, X11, V0, (X10) // ERROR "expected vector register in vs2 position" + VL1RV (X10), X10 // ERROR "expected vector register in vd position" + VL1RV (V1), V3 // ERROR "expected integer register in rs1 position" + VS1RV X11, (X11) // ERROR "expected vector register in vs1 position" + VS1RV V3, (V1) // ERROR "expected integer register in rd position" + VADDVV V1, X10, V3 // ERROR "expected vector register in vs2 position" + VADDVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VADDVI $16, V4, V2 // ERROR "signed immediate 16 must be in range [-16, 15] (5 bits)" + VADDVI $-17, V4, V2 // ERROR "signed immediate -17 must be in range [-16, 15] (5 bits)" + VSUBVV V1, X10, V3 // ERROR "expected vector register in vs2 position" + VSUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VRSUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VRSUBVI $16, V4, V2 // ERROR "signed immediate 16 must be in range [-16, 15] (5 bits)" + VRSUBVI $-17, V4, V2 // ERROR "signed immediate -17 must be in range [-16, 15] (5 bits)" + VNEGV X10, V3 // ERROR "expected vector register in vs2 position" + VNEGV V2 // ERROR "expected vector register in vd position" + VWADDUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWADDUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWSUBUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWSUBUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWADDVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWADDVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWSUBVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWSUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWADDUWV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWADDUWX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWSUBUWV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWSUBUWX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWADDWV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWADDWX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWSUBWV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWSUBWX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWCVTXXV X10, V3 // ERROR "expected vector register in vs2 position" + VWCVTUXXV X10, V3 // ERROR "expected vector register in vs2 position" + VZEXTVF2 V2, V0, V3, V4 // ERROR "expected no register in rs3" + VZEXTVF2 X10, V3 // ERROR "expected vector register in vs2 position" + VSEXTVF2 V2, V0, V3, V4 // ERROR "expected no register in rs3" + VSEXTVF2 X10, V3 // ERROR "expected vector register in vs2 position" + VZEXTVF4 V2, V0, V3, V4 // ERROR "expected no register in rs3" + VZEXTVF4 X10, V3 // ERROR "expected vector register in vs2 position" + VSEXTVF4 V2, V0, V3, V4 // ERROR "expected no register in rs3" + VSEXTVF4 X10, V3 // ERROR "expected vector register in vs2 position" + VZEXTVF8 V2, V0, V3, V4 // ERROR "expected no register in rs3" + VZEXTVF8 X10, V3 // ERROR "expected vector register in vs2 position" + VSEXTVF8 V2, V0, V3, V4 // ERROR "expected no register in rs3" + VSEXTVF8 X10, V3 // ERROR "expected vector register in vs2 position" + VADCVVM X10, V2, V0, V3 // ERROR "expected vector register in vs1 position" + VADCVXM V1, V2, V0, V3 // ERROR "expected integer register in rs1 position" + VADCVIM $16, V2, V0, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VADCVIM $-17, V2, V0, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMADCVVM X10, V2, V0, V3 // ERROR "expected vector register in vs1 position" + VMADCVXM V1, V2, V0, V3 // ERROR "expected integer register in rs1 position" + VMADCVIM $16, V2, V0, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMADCVIM $-17, V2, V0, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMADCVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMADCVV V1, V2, V0, V3 // ERROR "expected no register in rs3" + VMADCVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMADCVX X10, V2, V0, V3 // ERROR "expected no register in rs3" + VMADCVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMADCVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMADCVI $15, V2, V0, V3 // ERROR "expected no register in rs3" + VSBCVVM X10, V2, V0, V3 // ERROR "expected vector register in vs1 position" + VSBCVXM V1, V2, V0, V3 // ERROR "expected integer register in rs1 position" + VMSBCVVM X10, V2, V0, V3 // ERROR "expected vector register in vs1 position" + VMSBCVXM V1, V2, V0, V3 // ERROR "expected integer register in rs1 position" + VMSBCVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMSBCVV V1, V2, V0, V3 // ERROR "expected no register in rs3" + VMSBCVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMSBCVX X10, V2, V0, V3 // ERROR "expected no register in rs3" + VANDVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VANDVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VANDVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VANDVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VORVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VORVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VORVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VORVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VXORVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VXORVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VXORVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VXORVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VNOTV V3 // ERROR "expected vector register in vd position" + VNOTV X10, V3 // ERROR "expected vector register in vs2 position" + VSLLVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VSLLVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VSLLVI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]" + VSLLVI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]" + VSRLVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VSRLVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VSRLVI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]" + VSRLVI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]" + VSRAVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VSRAVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VSRAVI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]" + VSRAVI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]" + VNSRLWV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VNSRLWX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VNSRLWI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]" + VNSRLWI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]" + VNSRAWV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VNSRAWX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VNSRAWI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]" + VNSRAWI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]" + VNCVTXXW X10, V3 // ERROR "expected vector register in vs2 position" + VMSEQVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMSEQVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMSEQVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMSEQVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMSNEVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMSNEVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMSNEVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMSNEVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMSLTUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMSLTUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMSLTVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMSLTVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMSLEUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMSLEUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMSLEUVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMSLEUVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMSLEVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMSLEVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMSLEVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMSLEVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMSGTUVV X10, V2, V3 // ERROR "expected vector register in vs2 position" + VMSGTUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMSGTUVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMSGTUVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMSGTVV X10, V2, V3 // ERROR "expected vector register in vs2 position" + VMSGTVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMSGTVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMSGTVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMSGEVV X10, V2, V3 // ERROR "expected vector register in vs2 position" + VMSGEUVV X10, V2, V3 // ERROR "expected vector register in vs2 position" + VMSLTVI $17, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMSLTVI $-16, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMSLTUVI $17, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMSLTUVI $-16, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMSGEVI $17, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMSGEVI $-16, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMSGEUVI $17, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMSGEUVI $-16, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMINUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMINUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMINVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMINVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMAXUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMAXUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMAXVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMAXVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMULVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMULVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMULHVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMULHVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMULHUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMULHUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMULHSUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMULHSUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VDIVUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VDIVUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VDIVVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VDIVVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VREMUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VREMUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VREMVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VREMVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWMULVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWMULVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWMULUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWMULUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWMULSUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWMULSUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMACCVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMACCVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VNMSACVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VNMSACVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMADDVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMADDVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VNMSUBVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VNMSUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWMACCUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWMACCUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWMACCVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWMACCVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWMACCSUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VWMACCSUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VWMACCUSVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VMERGEVVM X10, V2, V0, V3 // ERROR "expected vector register in vs1 position" + VMERGEVXM V1, V2, V0, V3 // ERROR "expected integer register in rs1 position" + VMERGEVIM $16, V2, V0, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMERGEVIM $-17, V2, V0, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VMVVV X10, V3 // ERROR "expected vector register in vs1 position" + VMVVX V1, V2 // ERROR "expected integer register in rs1 position" + VMVVI $16, V2 // ERROR "signed immediate 16 must be in range [-16, 15]" + VMVVI $-17, V2 // ERROR "signed immediate -17 must be in range [-16, 15]" + VSADDUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VSADDUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VSADDUVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" + VSADDUVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" + VSSUBUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VSSUBUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VAADDUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VAADDUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VAADDVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VAADDVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VASUBUVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VASUBUVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VASUBVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VASUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VSMULVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VSMULVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VSSRLVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VSSRLVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VSSRLVI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]" + VSSRLVI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]" + VSSRAVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VSSRAVX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VSSRAVI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]" + VSSRAVI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]" + VNCLIPUWV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VNCLIPUWX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VNCLIPUWI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]" + VNCLIPUWI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]" + VNCLIPWV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VNCLIPWX V1, V2, V3 // ERROR "expected integer register in rs1 position" + VNCLIPWI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]" + VNCLIPWI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]" + VFADDVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFADDVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFSUBVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFSUBVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFRSUBVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFWADDVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFWADDVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFWSUBVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFWSUBVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFWADDWV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFWADDWF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFWSUBWV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFWSUBWF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFMULVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFMULVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFDIVVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFDIVVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFRDIVVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFWMULVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFWMULVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFMACCVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFMACCVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFNMACCVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFNMACCVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFMSACVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFMSACVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFNMSACVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFNMSACVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFMADDVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFMADDVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFNMADDVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFNMADDVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFMSUBVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFMSUBVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFNMSUBVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFNMSUBVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFWMACCVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFWMACCVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFWNMACCVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFWNMACCVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFWMSACVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFWMSACVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFWNMSACVV V2, X10, V3 // ERROR "expected vector register in vs1 position" + VFWNMSACVF V2, X10, V3 // ERROR "expected float register in rs1 position" + VFSQRTV X10, V3 // ERROR "expected vector register in vs2 position" + VFRSQRT7V X10, V3 // ERROR "expected vector register in vs2 position" + VFREC7V X10, V3 // ERROR "expected vector register in vs2 position" + VFMINVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFMINVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFMAXVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFMAXVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFSGNJVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFSGNJVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFSGNJNVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFSGNJNVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFSGNJXVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VFSGNJXVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VFNEGV V2, X10 // ERROR "expected vector register in vd position" + VFABSV V2, X10 // ERROR "expected vector register in vd position" + VMFEQVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMFEQVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VMFNEVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMFNEVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VMFLTVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMFLTVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VMFLEVV X10, V2, V3 // ERROR "expected vector register in vs1 position" + VMFLEVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VMFGTVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VMFGEVF X10, V2, V3 // ERROR "expected float register in rs1 position" + VMFGTVV X10, V2, V3 // ERROR "expected vector register in vs2 position" + VMFGEVV X10, V2, V3 // ERROR "expected vector register in vs2 position" + VFCLASSV X10, V3 // ERROR "expected vector register in vs2 position" + VFMERGEVFM X10, V2, V0, V3 // ERROR "expected float register in rs1 position" + VFMVVF X10, V3 // ERROR "expected float register in rs1 position" + VFCVTXUFV X10, V3 // ERROR "expected vector register in vs2 position" + VFCVTXFV X10, V3 // ERROR "expected vector register in vs2 position" + VFCVTRTZXUFV X10, V3 // ERROR "expected vector register in vs2 position" + VFCVTRTZXFV X10, V3 // ERROR "expected vector register in vs2 position" + VFCVTFXUV X10, V3 // ERROR "expected vector register in vs2 position" + VFCVTFXV X10, V3 // ERROR "expected vector register in vs2 position" + VFWCVTXUFV X10, V3 // ERROR "expected vector register in vs2 position" + VFWCVTXFV X10, V3 // ERROR "expected vector register in vs2 position" + VFWCVTRTZXUFV X10, V3 // ERROR "expected vector register in vs2 position" + VFWCVTRTZXFV X10, V3 // ERROR "expected vector register in vs2 position" + VFWCVTFXUV X10, V3 // ERROR "expected vector register in vs2 position" + VFWCVTFXV X10, V3 // ERROR "expected vector register in vs2 position" + VFWCVTFFV X10, V3 // ERROR "expected vector register in vs2 position" + VFNCVTXUFW X10, V3 // ERROR "expected vector register in vs2 position" + VFNCVTXFW X10, V3 // ERROR "expected vector register in vs2 position" + VFNCVTRTZXUFW X10, V3 // ERROR "expected vector register in vs2 position" + VFNCVTRTZXFW X10, V3 // ERROR "expected vector register in vs2 position" + VFNCVTFXUW X10, V3 // ERROR "expected vector register in vs2 position" + VFNCVTFXW X10, V3 // ERROR "expected vector register in vs2 position" + VFNCVTFFW X10, V3 // ERROR "expected vector register in vs2 position" + VFNCVTRODFFW X10, V3 // ERROR "expected vector register in vs2 position" RET diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go index a65dfceea9..bf1fdb8b88 100644 --- a/src/cmd/internal/obj/riscv/anames.go +++ b/src/cmd/internal/obj/riscv/anames.go @@ -650,6 +650,10 @@ var Anames = []string{ "RDTIME", "SEQZ", "SNEZ", + "VFABSV", + "VFNEGV", + "VMFGEVV", + "VMFGTVV", "VL1RV", "VL2RV", "VL4RV", diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go index fa4c2cf372..3cad4f9d94 100644 --- a/src/cmd/internal/obj/riscv/cpu.go +++ b/src/cmd/internal/obj/riscv/cpu.go @@ -1178,6 +1178,10 @@ const ( ARDTIME ASEQZ ASNEZ + AVFABSV + AVFNEGV + AVMFGEVV + AVMFGTVV AVL1RV AVL2RV AVL4RV diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go index f8ad3bb104..5563af9129 100644 --- a/src/cmd/internal/obj/riscv/obj.go +++ b/src/cmd/internal/obj/riscv/obj.go @@ -1307,6 +1307,13 @@ func validateRFI(ctxt *obj.Link, ins *instruction) { wantNoneReg(ctxt, ins, "rs3", ins.rs3) } +func validateRFF(ctxt *obj.Link, ins *instruction) { + wantFloatReg(ctxt, ins, "rd", ins.rd) + wantNoneReg(ctxt, ins, "rs1", ins.rs1) + wantFloatReg(ctxt, ins, "rs2", ins.rs2) + wantNoneReg(ctxt, ins, "rs3", ins.rs3) +} + func validateRIF(ctxt *obj.Link, ins *instruction) { wantFloatReg(ctxt, ins, "rd", ins.rd) wantNoneReg(ctxt, ins, "rs1", ins.rs1) @@ -1314,10 +1321,10 @@ func validateRIF(ctxt *obj.Link, ins *instruction) { wantNoneReg(ctxt, ins, "rs3", ins.rs3) } -func validateRFF(ctxt *obj.Link, ins *instruction) { - wantFloatReg(ctxt, ins, "rd", ins.rd) - wantNoneReg(ctxt, ins, "rs1", ins.rs1) - wantFloatReg(ctxt, ins, "rs2", ins.rs2) +func validateRVFV(ctxt *obj.Link, ins *instruction) { + wantVectorReg(ctxt, ins, "vd", ins.rd) + wantFloatReg(ctxt, ins, "rs1", ins.rs1) + wantVectorReg(ctxt, ins, "vs2", ins.rs2) wantNoneReg(ctxt, ins, "rs3", ins.rs3) } @@ -1558,12 +1565,20 @@ func encodeRFI(ins *instruction) uint32 { return encodeR(ins.as, regF(ins.rs2), 0, regI(ins.rd), ins.funct3, ins.funct7) } +func encodeRFF(ins *instruction) uint32 { + return encodeR(ins.as, regF(ins.rs2), 0, regF(ins.rd), ins.funct3, ins.funct7) +} + func encodeRIF(ins *instruction) uint32 { return encodeR(ins.as, regI(ins.rs2), 0, regF(ins.rd), ins.funct3, ins.funct7) } -func encodeRFF(ins *instruction) uint32 { - return encodeR(ins.as, regF(ins.rs2), 0, regF(ins.rd), ins.funct3, ins.funct7) +func encodeRVFV(ins *instruction) uint32 { + return encodeR(ins.as, regF(ins.rs1), regV(ins.rs2), regV(ins.rd), ins.funct3, ins.funct7) +} + +func encodeRVIV(ins *instruction) uint32 { + return encodeR(ins.as, regI(ins.rs1), regV(ins.rs2), regV(ins.rd), ins.funct3, ins.funct7) } func encodeRVV(ins *instruction) uint32 { @@ -1578,10 +1593,6 @@ func encodeRVVu(ins *instruction) uint32 { return encodeR(ins.as, immU(ins.as, ins.imm, 5), regV(ins.rs2), regV(ins.rd), ins.funct3, ins.funct7) } -func encodeRVIV(ins *instruction) uint32 { - return encodeR(ins.as, regI(ins.rs1), regV(ins.rs2), regV(ins.rd), ins.funct3, ins.funct7) -} - func encodeRVVV(ins *instruction) uint32 { return encodeR(ins.as, regV(ins.rs1), regV(ins.rs2), regV(ins.rd), ins.funct3, ins.funct7) } @@ -1869,10 +1880,11 @@ var ( rFIEncoding = encoding{encode: encodeRFI, validate: validateRFI, length: 4} rIFEncoding = encoding{encode: encodeRIF, validate: validateRIF, length: 4} rFFEncoding = encoding{encode: encodeRFF, validate: validateRFF, length: 4} + rVFVEncoding = encoding{encode: encodeRVFV, validate: validateRVFV, length: 4} + rVIVEncoding = encoding{encode: encodeRVIV, validate: validateRVIV, length: 4} rVVEncoding = encoding{encode: encodeRVV, validate: validateRVV, length: 4} rVViEncoding = encoding{encode: encodeRVVi, validate: validateRVVi, length: 4} rVVuEncoding = encoding{encode: encodeRVVu, validate: validateRVVu, length: 4} - rVIVEncoding = encoding{encode: encodeRVIV, validate: validateRVIV, length: 4} rVVVEncoding = encoding{encode: encodeRVVV, validate: validateRVVV, length: 4} iIIEncoding = encoding{encode: encodeIII, validate: validateIII, length: 4} @@ -2446,6 +2458,133 @@ var instructions = [ALAST & obj.AMask]instructionData{ AVNCLIPWX & obj.AMask: {enc: rVIVEncoding}, AVNCLIPWI & obj.AMask: {enc: rVVuEncoding}, + // 31.13.2: Vector Single-Width Floating-Point Add/Subtract Instructions + AVFADDVV & obj.AMask: {enc: rVVVEncoding}, + AVFADDVF & obj.AMask: {enc: rVFVEncoding}, + AVFSUBVV & obj.AMask: {enc: rVVVEncoding}, + AVFSUBVF & obj.AMask: {enc: rVFVEncoding}, + AVFRSUBVF & obj.AMask: {enc: rVFVEncoding}, + + // 31.13.3: Vector Widening Floating-Point Add/Subtract Instructions + AVFWADDVV & obj.AMask: {enc: rVVVEncoding}, + AVFWADDVF & obj.AMask: {enc: rVFVEncoding}, + AVFWSUBVV & obj.AMask: {enc: rVVVEncoding}, + AVFWSUBVF & obj.AMask: {enc: rVFVEncoding}, + AVFWADDWV & obj.AMask: {enc: rVVVEncoding}, + AVFWADDWF & obj.AMask: {enc: rVFVEncoding}, + AVFWSUBWV & obj.AMask: {enc: rVVVEncoding}, + AVFWSUBWF & obj.AMask: {enc: rVFVEncoding}, + + // 31.13.4: Vector Single-Width Floating-Point Multiply/Divide Instructions + AVFMULVV & obj.AMask: {enc: rVVVEncoding}, + AVFMULVF & obj.AMask: {enc: rVFVEncoding}, + AVFDIVVV & obj.AMask: {enc: rVVVEncoding}, + AVFDIVVF & obj.AMask: {enc: rVFVEncoding}, + AVFRDIVVF & obj.AMask: {enc: rVFVEncoding}, + + // 31.13.5: Vector Widening Floating-Point Multiply + AVFWMULVV & obj.AMask: {enc: rVVVEncoding}, + AVFWMULVF & obj.AMask: {enc: rVFVEncoding}, + + // 31.13.6: Vector Single-Width Floating-Point Fused Multiply-Add Instructions + AVFMACCVV & obj.AMask: {enc: rVVVEncoding}, + AVFMACCVF & obj.AMask: {enc: rVFVEncoding}, + AVFNMACCVV & obj.AMask: {enc: rVVVEncoding}, + AVFNMACCVF & obj.AMask: {enc: rVFVEncoding}, + AVFMSACVV & obj.AMask: {enc: rVVVEncoding}, + AVFMSACVF & obj.AMask: {enc: rVFVEncoding}, + AVFNMSACVV & obj.AMask: {enc: rVVVEncoding}, + AVFNMSACVF & obj.AMask: {enc: rVFVEncoding}, + AVFMADDVV & obj.AMask: {enc: rVVVEncoding}, + AVFMADDVF & obj.AMask: {enc: rVFVEncoding}, + AVFNMADDVV & obj.AMask: {enc: rVVVEncoding}, + AVFNMADDVF & obj.AMask: {enc: rVFVEncoding}, + AVFMSUBVV & obj.AMask: {enc: rVVVEncoding}, + AVFMSUBVF & obj.AMask: {enc: rVFVEncoding}, + AVFNMSUBVV & obj.AMask: {enc: rVVVEncoding}, + AVFNMSUBVF & obj.AMask: {enc: rVFVEncoding}, + + // 31.13.7: Vector Widening Floating-Point Fused Multiply-Add Instructions + AVFWMACCVV & obj.AMask: {enc: rVVVEncoding}, + AVFWMACCVF & obj.AMask: {enc: rVFVEncoding}, + AVFWNMACCVV & obj.AMask: {enc: rVVVEncoding}, + AVFWNMACCVF & obj.AMask: {enc: rVFVEncoding}, + AVFWMSACVV & obj.AMask: {enc: rVVVEncoding}, + AVFWMSACVF & obj.AMask: {enc: rVFVEncoding}, + AVFWNMSACVV & obj.AMask: {enc: rVVVEncoding}, + AVFWNMSACVF & obj.AMask: {enc: rVFVEncoding}, + + // 31.13.8: Vector Floating-Point Square-Root Instruction + AVFSQRTV & obj.AMask: {enc: rVVEncoding}, + + // 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction + AVFRSQRT7V & obj.AMask: {enc: rVVEncoding}, + + // 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction + AVFREC7V & obj.AMask: {enc: rVVEncoding}, + + // 31.13.11: Vector Floating-Point MIN/MAX Instructions + AVFMINVV & obj.AMask: {enc: rVVVEncoding}, + AVFMINVF & obj.AMask: {enc: rVFVEncoding}, + AVFMAXVV & obj.AMask: {enc: rVVVEncoding}, + AVFMAXVF & obj.AMask: {enc: rVFVEncoding}, + + // 31.13.12: Vector Floating-Point Sign-Injection Instructions + AVFSGNJVV & obj.AMask: {enc: rVVVEncoding}, + AVFSGNJVF & obj.AMask: {enc: rVFVEncoding}, + AVFSGNJNVV & obj.AMask: {enc: rVVVEncoding}, + AVFSGNJNVF & obj.AMask: {enc: rVFVEncoding}, + AVFSGNJXVV & obj.AMask: {enc: rVVVEncoding}, + AVFSGNJXVF & obj.AMask: {enc: rVFVEncoding}, + + // 31.13.13: Vector Floating-Point Compare Instructions + AVMFEQVV & obj.AMask: {enc: rVVVEncoding}, + AVMFEQVF & obj.AMask: {enc: rVFVEncoding}, + AVMFNEVV & obj.AMask: {enc: rVVVEncoding}, + AVMFNEVF & obj.AMask: {enc: rVFVEncoding}, + AVMFLTVV & obj.AMask: {enc: rVVVEncoding}, + AVMFLTVF & obj.AMask: {enc: rVFVEncoding}, + AVMFLEVV & obj.AMask: {enc: rVVVEncoding}, + AVMFLEVF & obj.AMask: {enc: rVFVEncoding}, + AVMFGTVF & obj.AMask: {enc: rVFVEncoding}, + AVMFGEVF & obj.AMask: {enc: rVFVEncoding}, + + // 31.13.14: Vector Floating-Point Classify Instruction + AVFCLASSV & obj.AMask: {enc: rVVEncoding}, + + // 31.13.15: Vector Floating-Point Merge Instruction + AVFMERGEVFM & obj.AMask: {enc: rVFVEncoding}, + + // 31.13.16: Vector Floating-Point Move Instruction + AVFMVVF & obj.AMask: {enc: rVFVEncoding}, + + // 31.13.17: Single-Width Floating-Point/Integer Type-Convert Instructions + AVFCVTXUFV & obj.AMask: {enc: rVVEncoding}, + AVFCVTXFV & obj.AMask: {enc: rVVEncoding}, + AVFCVTRTZXUFV & obj.AMask: {enc: rVVEncoding}, + AVFCVTRTZXFV & obj.AMask: {enc: rVVEncoding}, + AVFCVTFXUV & obj.AMask: {enc: rVVEncoding}, + AVFCVTFXV & obj.AMask: {enc: rVVEncoding}, + + // 31.13.18: Widening Floating-Point/Integer Type-Convert Instructions + AVFWCVTXUFV & obj.AMask: {enc: rVVEncoding}, + AVFWCVTXFV & obj.AMask: {enc: rVVEncoding}, + AVFWCVTRTZXUFV & obj.AMask: {enc: rVVEncoding}, + AVFWCVTRTZXFV & obj.AMask: {enc: rVVEncoding}, + AVFWCVTFXUV & obj.AMask: {enc: rVVEncoding}, + AVFWCVTFXV & obj.AMask: {enc: rVVEncoding}, + AVFWCVTFFV & obj.AMask: {enc: rVVEncoding}, + + // 31.13.19: Narrowing Floating-Point/Integer Type-Convert Instructions + AVFNCVTXUFW & obj.AMask: {enc: rVVEncoding}, + AVFNCVTXFW & obj.AMask: {enc: rVVEncoding}, + AVFNCVTRTZXUFW & obj.AMask: {enc: rVVEncoding}, + AVFNCVTRTZXFW & obj.AMask: {enc: rVVEncoding}, + AVFNCVTFXUW & obj.AMask: {enc: rVVEncoding}, + AVFNCVTFXW & obj.AMask: {enc: rVVEncoding}, + AVFNCVTFFW & obj.AMask: {enc: rVVEncoding}, + AVFNCVTRODFFW & obj.AMask: {enc: rVVEncoding}, + // // Privileged ISA // @@ -3433,7 +3572,13 @@ func instructionsForProg(p *obj.Prog) []*instruction { AVSADDUVV, AVSADDUVX, AVSADDUVI, AVSADDVV, AVSADDVX, AVSADDVI, AVSSUBUVV, AVSSUBUVX, AVSSUBVV, AVSSUBVX, AVAADDUVV, AVAADDUVX, AVAADDVV, AVAADDVX, AVASUBUVV, AVASUBUVX, AVASUBVV, AVASUBVX, AVSMULVV, AVSMULVX, AVSSRLVV, AVSSRLVX, AVSSRLVI, AVSSRAVV, AVSSRAVX, AVSSRAVI, - AVNCLIPUWV, AVNCLIPUWX, AVNCLIPUWI, AVNCLIPWV, AVNCLIPWX, AVNCLIPWI: + AVNCLIPUWV, AVNCLIPUWX, AVNCLIPUWI, AVNCLIPWV, AVNCLIPWX, AVNCLIPWI, + AVFADDVV, AVFADDVF, AVFSUBVV, AVFSUBVF, AVFRSUBVF, + AVFWADDVV, AVFWADDVF, AVFWSUBVV, AVFWSUBVF, AVFWADDWV, AVFWADDWF, AVFWSUBWV, AVFWSUBWF, + AVFMULVV, AVFMULVF, AVFDIVVV, AVFDIVVF, AVFRDIVVF, AVFWMULVV, AVFWMULVF, + AVFMINVV, AVFMINVF, AVFMAXVV, AVFMAXVF, + AVFSGNJVV, AVFSGNJVF, AVFSGNJNVV, AVFSGNJNVF, AVFSGNJXVV, AVFSGNJXVF, + AVMFEQVV, AVMFEQVF, AVMFNEVV, AVMFNEVF, AVMFLTVV, AVMFLTVF, AVMFLEVV, AVMFLEVF, AVMFGTVF, AVMFGEVF: // Set mask bit switch { case ins.rs3 == obj.REG_NONE: @@ -3443,6 +3588,17 @@ func instructionsForProg(p *obj.Prog) []*instruction { } ins.rd, ins.rs1, ins.rs2, ins.rs3 = uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), obj.REG_NONE + case AVFMACCVV, AVFMACCVF, AVFNMACCVV, AVFNMACCVF, AVFMSACVV, AVFMSACVF, AVFNMSACVV, AVFNMSACVF, + AVFMADDVV, AVFMADDVF, AVFNMADDVV, AVFNMADDVF, AVFMSUBVV, AVFMSUBVF, AVFNMSUBVV, AVFNMSUBVF, + AVFWMACCVV, AVFWMACCVF, AVFWNMACCVV, AVFWNMACCVF, AVFWMSACVV, AVFWMSACVF, AVFWNMSACVV, AVFWNMSACVF: + switch { + case ins.rs3 == obj.REG_NONE: + ins.funct7 |= 1 // unmasked + case ins.rs3 != REG_V0: + p.Ctxt.Diag("%v: invalid vector mask register", p) + } + ins.rd, ins.rs1, ins.rs2, ins.rs3 = uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), obj.REG_NONE + case AVADDVI, AVRSUBVI, AVANDVI, AVORVI, AVXORVI, AVMSEQVI, AVMSNEVI, AVMSLEUVI, AVMSLEVI, AVMSGTUVI, AVMSGTVI, AVSLLVI, AVSRLVI, AVSRAVI, AVNSRLWI, AVNSRAWI: // Set mask bit @@ -3454,7 +3610,10 @@ func instructionsForProg(p *obj.Prog) []*instruction { } ins.rd, ins.rs1, ins.rs2, ins.rs3 = uint32(p.To.Reg), obj.REG_NONE, uint32(p.Reg), obj.REG_NONE - case AVZEXTVF2, AVSEXTVF2, AVZEXTVF4, AVSEXTVF4, AVZEXTVF8, AVSEXTVF8: + case AVZEXTVF2, AVSEXTVF2, AVZEXTVF4, AVSEXTVF4, AVZEXTVF8, AVSEXTVF8, AVFSQRTV, AVFRSQRT7V, AVFREC7V, AVFCLASSV, + AVFCVTXUFV, AVFCVTXFV, AVFCVTRTZXUFV, AVFCVTRTZXFV, AVFCVTFXUV, AVFCVTFXV, + AVFWCVTXUFV, AVFWCVTXFV, AVFWCVTRTZXUFV, AVFWCVTRTZXFV, AVFWCVTFXUV, AVFWCVTFXV, AVFWCVTFFV, + AVFNCVTXUFW, AVFNCVTXFW, AVFNCVTRTZXUFW, AVFNCVTRTZXFW, AVFNCVTFXUW, AVFNCVTFXW, AVFNCVTFFW, AVFNCVTRODFFW: // Set mask bit switch { case ins.rs1 == obj.REG_NONE: @@ -3476,8 +3635,12 @@ func instructionsForProg(p *obj.Prog) []*instruction { } ins.rd, ins.rs1, ins.rs2 = uint32(p.To.Reg), obj.REG_NONE, REG_V0 + case AVFMVVF: + ins.funct7 |= 1 // unmasked + ins.rd, ins.rs1, ins.rs2 = uint32(p.To.Reg), uint32(p.From.Reg), REG_V0 + case AVADCVVM, AVADCVXM, AVMADCVVM, AVMADCVXM, AVSBCVVM, AVSBCVXM, AVMSBCVVM, AVMSBCVXM, AVADCVIM, AVMADCVIM, - AVMERGEVVM, AVMERGEVXM, AVMERGEVIM: + AVMERGEVVM, AVMERGEVXM, AVMERGEVIM, AVFMERGEVFM: if ins.rs3 != REG_V0 { p.Ctxt.Diag("%v: invalid vector mask register", p) } @@ -3517,7 +3680,7 @@ func instructionsForProg(p *obj.Prog) []*instruction { ins.as = AVXORVI ins.rd, ins.rs1, ins.rs2, ins.imm = uint32(p.To.Reg), obj.REG_NONE, uint32(p.From.Reg), -1 - case AVMSGTVV, AVMSGTUVV, AVMSGEVV, AVMSGEUVV: + case AVMSGTVV, AVMSGTUVV, AVMSGEVV, AVMSGEUVV, AVMFGTVV, AVMFGEVV: // Set mask bit switch { case ins.rs3 == obj.REG_NONE: @@ -3534,6 +3697,10 @@ func instructionsForProg(p *obj.Prog) []*instruction { ins.as = AVMSLEVV case AVMSGEUVV: ins.as = AVMSLEUVV + case AVMFGTVV: + ins.as = AVMFLTVV + case AVMFGEVV: + ins.as = AVMFLEVV } ins.rd, ins.rs1, ins.rs2, ins.rs3 = uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), obj.REG_NONE @@ -3556,6 +3723,22 @@ func instructionsForProg(p *obj.Prog) []*instruction { ins.as = AVMSGTUVI } ins.rd, ins.rs1, ins.rs2, ins.rs3, ins.imm = uint32(p.To.Reg), obj.REG_NONE, uint32(p.Reg), obj.REG_NONE, ins.imm-1 + + case AVFABSV, AVFNEGV: + // Set mask bit + switch { + case ins.rs1 == obj.REG_NONE: + ins.funct7 |= 1 // unmasked + case ins.rs1 != REG_V0: + p.Ctxt.Diag("%v: invalid vector mask register", p) + } + switch ins.as { + case AVFABSV: + ins.as = AVFSGNJXVV + case AVFNEGV: + ins.as = AVFSGNJNVV + } + ins.rd, ins.rs1, ins.rs2 = uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg) } for _, ins := range inss {