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cmd/internal/obj/mips: add a flag field to Optab
The flag field will be used for marking unsafe points. This CL just adds the field, not doing anything with it. The next CL will make use of it. This is for making the diff simpler. Change-Id: I6ff5406ba2e53ae8a882184733d88482a2ca8e2a Reviewed-on: https://go-review.googlesource.com/c/go/+/203938 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Austin Clements <austin@google.com>
This commit is contained in:
Cherry Zhang
parent
11db7e4469
commit
9a0a824456
@ -69,321 +69,322 @@ type Optab struct {
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size int8
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param int16
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family sys.ArchFamily // 0 means both sys.MIPS and sys.MIPS64
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flag uint8
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}
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var optab = []Optab{
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{obj.ATEXT, C_LEXT, C_NONE, C_TEXTSIZE, 0, 0, 0, sys.MIPS64},
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{obj.ATEXT, C_ADDR, C_NONE, C_TEXTSIZE, 0, 0, 0, 0},
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{obj.ATEXT, C_LEXT, C_NONE, C_TEXTSIZE, 0, 0, 0, sys.MIPS64, 0},
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{obj.ATEXT, C_ADDR, C_NONE, C_TEXTSIZE, 0, 0, 0, 0, 0},
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{AMOVW, C_REG, C_NONE, C_REG, 1, 4, 0, 0},
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{AMOVV, C_REG, C_NONE, C_REG, 1, 4, 0, sys.MIPS64},
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{AMOVB, C_REG, C_NONE, C_REG, 12, 8, 0, 0},
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{AMOVBU, C_REG, C_NONE, C_REG, 13, 4, 0, 0},
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{AMOVWU, C_REG, C_NONE, C_REG, 14, 8, 0, sys.MIPS64},
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{AMOVW, C_REG, C_NONE, C_REG, 1, 4, 0, 0, 0},
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{AMOVV, C_REG, C_NONE, C_REG, 1, 4, 0, sys.MIPS64, 0},
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{AMOVB, C_REG, C_NONE, C_REG, 12, 8, 0, 0, 0},
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{AMOVBU, C_REG, C_NONE, C_REG, 13, 4, 0, 0, 0},
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{AMOVWU, C_REG, C_NONE, C_REG, 14, 8, 0, sys.MIPS64, 0},
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{ASUB, C_REG, C_REG, C_REG, 2, 4, 0, 0},
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{ASUBV, C_REG, C_REG, C_REG, 2, 4, 0, sys.MIPS64},
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{AADD, C_REG, C_REG, C_REG, 2, 4, 0, 0},
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{AADDV, C_REG, C_REG, C_REG, 2, 4, 0, sys.MIPS64},
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{AAND, C_REG, C_REG, C_REG, 2, 4, 0, 0},
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{ASUB, C_REG, C_NONE, C_REG, 2, 4, 0, 0},
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{ASUBV, C_REG, C_NONE, C_REG, 2, 4, 0, sys.MIPS64},
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{AADD, C_REG, C_NONE, C_REG, 2, 4, 0, 0},
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{AADDV, C_REG, C_NONE, C_REG, 2, 4, 0, sys.MIPS64},
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{AAND, C_REG, C_NONE, C_REG, 2, 4, 0, 0},
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{ACMOVN, C_REG, C_REG, C_REG, 2, 4, 0, 0},
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{ANEGW, C_REG, C_NONE, C_REG, 2, 4, 0, 0},
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{ANEGV, C_REG, C_NONE, C_REG, 2, 4, 0, sys.MIPS64},
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{ASUB, C_REG, C_REG, C_REG, 2, 4, 0, 0, 0},
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{ASUBV, C_REG, C_REG, C_REG, 2, 4, 0, sys.MIPS64, 0},
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{AADD, C_REG, C_REG, C_REG, 2, 4, 0, 0, 0},
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{AADDV, C_REG, C_REG, C_REG, 2, 4, 0, sys.MIPS64, 0},
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{AAND, C_REG, C_REG, C_REG, 2, 4, 0, 0, 0},
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{ASUB, C_REG, C_NONE, C_REG, 2, 4, 0, 0, 0},
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{ASUBV, C_REG, C_NONE, C_REG, 2, 4, 0, sys.MIPS64, 0},
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{AADD, C_REG, C_NONE, C_REG, 2, 4, 0, 0, 0},
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{AADDV, C_REG, C_NONE, C_REG, 2, 4, 0, sys.MIPS64, 0},
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{AAND, C_REG, C_NONE, C_REG, 2, 4, 0, 0, 0},
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{ACMOVN, C_REG, C_REG, C_REG, 2, 4, 0, 0, 0},
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{ANEGW, C_REG, C_NONE, C_REG, 2, 4, 0, 0, 0},
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{ANEGV, C_REG, C_NONE, C_REG, 2, 4, 0, sys.MIPS64, 0},
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{ASLL, C_REG, C_NONE, C_REG, 9, 4, 0, 0},
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{ASLL, C_REG, C_REG, C_REG, 9, 4, 0, 0},
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{ASLLV, C_REG, C_NONE, C_REG, 9, 4, 0, sys.MIPS64},
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{ASLLV, C_REG, C_REG, C_REG, 9, 4, 0, sys.MIPS64},
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{ACLO, C_REG, C_NONE, C_REG, 9, 4, 0, 0},
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{ASLL, C_REG, C_NONE, C_REG, 9, 4, 0, 0, 0},
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{ASLL, C_REG, C_REG, C_REG, 9, 4, 0, 0, 0},
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{ASLLV, C_REG, C_NONE, C_REG, 9, 4, 0, sys.MIPS64, 0},
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{ASLLV, C_REG, C_REG, C_REG, 9, 4, 0, sys.MIPS64, 0},
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{ACLO, C_REG, C_NONE, C_REG, 9, 4, 0, 0, 0},
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{AADDF, C_FREG, C_NONE, C_FREG, 32, 4, 0, 0},
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{AADDF, C_FREG, C_REG, C_FREG, 32, 4, 0, 0},
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{ACMPEQF, C_FREG, C_REG, C_NONE, 32, 4, 0, 0},
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{AABSF, C_FREG, C_NONE, C_FREG, 33, 4, 0, 0},
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{AMOVVF, C_FREG, C_NONE, C_FREG, 33, 4, 0, sys.MIPS64},
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{AMOVF, C_FREG, C_NONE, C_FREG, 33, 4, 0, 0},
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{AMOVD, C_FREG, C_NONE, C_FREG, 33, 4, 0, 0},
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{AADDF, C_FREG, C_NONE, C_FREG, 32, 4, 0, 0, 0},
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{AADDF, C_FREG, C_REG, C_FREG, 32, 4, 0, 0, 0},
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{ACMPEQF, C_FREG, C_REG, C_NONE, 32, 4, 0, 0, 0},
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{AABSF, C_FREG, C_NONE, C_FREG, 33, 4, 0, 0, 0},
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{AMOVVF, C_FREG, C_NONE, C_FREG, 33, 4, 0, sys.MIPS64, 0},
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{AMOVF, C_FREG, C_NONE, C_FREG, 33, 4, 0, 0, 0},
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{AMOVD, C_FREG, C_NONE, C_FREG, 33, 4, 0, 0, 0},
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{AMOVW, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
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{AMOVWU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
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{AMOVV, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
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{AMOVB, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
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{AMOVBU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
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{AMOVWL, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
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{AMOVVL, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64},
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{AMOVW, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0},
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{AMOVWU, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64},
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{AMOVV, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64},
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{AMOVB, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0},
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{AMOVBU, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0},
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{AMOVWL, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0},
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{AMOVVL, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64},
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{AMOVW, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0},
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{AMOVWU, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64},
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{AMOVV, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64},
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{AMOVB, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0},
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{AMOVBU, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0},
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{AMOVWL, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0},
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{AMOVVL, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64},
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{ASC, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0},
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{ASCV, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64},
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{AMOVW, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0},
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{AMOVWU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0},
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{AMOVV, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0},
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{AMOVB, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0},
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{AMOVBU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0},
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{AMOVWL, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0},
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{AMOVVL, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0},
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{AMOVW, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0, 0},
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{AMOVWU, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64, 0},
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{AMOVV, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64, 0},
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{AMOVB, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0, 0},
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{AMOVBU, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0, 0},
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{AMOVWL, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, 0, 0},
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{AMOVVL, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64, 0},
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{AMOVW, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0, 0},
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{AMOVWU, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64, 0},
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{AMOVV, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64, 0},
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{AMOVB, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0, 0},
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{AMOVBU, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0, 0},
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{AMOVWL, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0, 0},
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{AMOVVL, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64, 0},
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{ASC, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, 0, 0},
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{ASCV, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64, 0},
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{AMOVW, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
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{AMOVWU, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
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{AMOVV, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
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{AMOVB, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
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{AMOVBU, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
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{AMOVWL, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
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{AMOVVL, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64},
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{AMOVW, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0},
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{AMOVWU, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, sys.MIPS64},
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{AMOVV, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, sys.MIPS64},
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{AMOVB, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0},
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{AMOVBU, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0},
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{AMOVWL, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0},
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{AMOVVL, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, sys.MIPS64},
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{AMOVW, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0},
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{AMOVWU, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, sys.MIPS64},
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{AMOVV, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, sys.MIPS64},
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{AMOVB, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0},
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{AMOVBU, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0},
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{AMOVWL, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0},
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{AMOVVL, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, sys.MIPS64},
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{ALL, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0},
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{ALLV, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, sys.MIPS64},
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{AMOVW, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64, 0},
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{AMOVWU, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64, 0},
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{AMOVV, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64, 0},
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{AMOVB, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64, 0},
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{AMOVBU, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64, 0},
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{AMOVWL, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64, 0},
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{AMOVVL, C_SEXT, C_NONE, C_REG, 8, 4, REGSB, sys.MIPS64, 0},
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{AMOVW, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0, 0},
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{AMOVWU, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, sys.MIPS64, 0},
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{AMOVV, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, sys.MIPS64, 0},
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{AMOVB, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0, 0},
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{AMOVBU, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0, 0},
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{AMOVWL, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, 0, 0},
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{AMOVVL, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP, sys.MIPS64, 0},
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{AMOVW, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0, 0},
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{AMOVWU, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, sys.MIPS64, 0},
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{AMOVV, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, sys.MIPS64, 0},
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{AMOVB, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0, 0},
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{AMOVBU, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0, 0},
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{AMOVWL, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0, 0},
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{AMOVVL, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, sys.MIPS64, 0},
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{ALL, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, 0, 0},
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{ALLV, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO, sys.MIPS64, 0},
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{AMOVW, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64},
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{AMOVWU, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64},
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{AMOVV, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64},
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{AMOVB, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64},
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{AMOVBU, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64},
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{AMOVW, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, 0},
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{AMOVWU, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, sys.MIPS64},
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{AMOVV, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, sys.MIPS64},
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{AMOVB, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, 0},
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{AMOVBU, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, 0},
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{AMOVW, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0},
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{AMOVWU, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, sys.MIPS64},
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{AMOVV, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, sys.MIPS64},
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{AMOVB, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0},
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{AMOVBU, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0},
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{ASC, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0},
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{AMOVW, C_REG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS},
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{AMOVW, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
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{AMOVWU, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
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{AMOVV, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
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{AMOVB, C_REG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS},
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{AMOVB, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
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{AMOVBU, C_REG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS},
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{AMOVBU, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
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{AMOVW, C_REG, C_NONE, C_TLS, 53, 8, 0, 0},
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{AMOVWU, C_REG, C_NONE, C_TLS, 53, 8, 0, sys.MIPS64},
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{AMOVV, C_REG, C_NONE, C_TLS, 53, 8, 0, sys.MIPS64},
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{AMOVB, C_REG, C_NONE, C_TLS, 53, 8, 0, 0},
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{AMOVBU, C_REG, C_NONE, C_TLS, 53, 8, 0, 0},
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{AMOVW, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64, 0},
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{AMOVWU, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64, 0},
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{AMOVV, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64, 0},
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{AMOVB, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64, 0},
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{AMOVBU, C_REG, C_NONE, C_LEXT, 35, 12, REGSB, sys.MIPS64, 0},
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{AMOVW, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, 0, 0},
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{AMOVWU, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, sys.MIPS64, 0},
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{AMOVV, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, sys.MIPS64, 0},
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{AMOVB, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, 0, 0},
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{AMOVBU, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP, 0, 0},
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{AMOVW, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0, 0},
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{AMOVWU, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, sys.MIPS64, 0},
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{AMOVV, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, sys.MIPS64, 0},
|
||||
{AMOVB, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0, 0},
|
||||
{AMOVBU, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0, 0},
|
||||
{ASC, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO, 0, 0},
|
||||
{AMOVW, C_REG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS, 0},
|
||||
{AMOVW, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVWU, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVB, C_REG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS, 0},
|
||||
{AMOVB, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVBU, C_REG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS, 0},
|
||||
{AMOVBU, C_REG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVW, C_REG, C_NONE, C_TLS, 53, 8, 0, 0, 0},
|
||||
{AMOVWU, C_REG, C_NONE, C_TLS, 53, 8, 0, sys.MIPS64, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_TLS, 53, 8, 0, sys.MIPS64, 0},
|
||||
{AMOVB, C_REG, C_NONE, C_TLS, 53, 8, 0, 0, 0},
|
||||
{AMOVBU, C_REG, C_NONE, C_TLS, 53, 8, 0, 0, 0},
|
||||
|
||||
{AMOVW, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64},
|
||||
{AMOVWU, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64},
|
||||
{AMOVV, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64},
|
||||
{AMOVB, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64},
|
||||
{AMOVBU, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64},
|
||||
{AMOVW, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, 0},
|
||||
{AMOVWU, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, sys.MIPS64},
|
||||
{AMOVV, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, sys.MIPS64},
|
||||
{AMOVB, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, 0},
|
||||
{AMOVBU, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, 0},
|
||||
{AMOVW, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, 0},
|
||||
{AMOVWU, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, sys.MIPS64},
|
||||
{AMOVV, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, sys.MIPS64},
|
||||
{AMOVB, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, 0},
|
||||
{AMOVBU, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, 0},
|
||||
{AMOVW, C_ADDR, C_NONE, C_REG, 51, 8, 0, sys.MIPS},
|
||||
{AMOVW, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64},
|
||||
{AMOVWU, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64},
|
||||
{AMOVV, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64},
|
||||
{AMOVB, C_ADDR, C_NONE, C_REG, 51, 8, 0, sys.MIPS},
|
||||
{AMOVB, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64},
|
||||
{AMOVBU, C_ADDR, C_NONE, C_REG, 51, 8, 0, sys.MIPS},
|
||||
{AMOVBU, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64},
|
||||
{AMOVW, C_TLS, C_NONE, C_REG, 54, 8, 0, 0},
|
||||
{AMOVWU, C_TLS, C_NONE, C_REG, 54, 8, 0, sys.MIPS64},
|
||||
{AMOVV, C_TLS, C_NONE, C_REG, 54, 8, 0, sys.MIPS64},
|
||||
{AMOVB, C_TLS, C_NONE, C_REG, 54, 8, 0, 0},
|
||||
{AMOVBU, C_TLS, C_NONE, C_REG, 54, 8, 0, 0},
|
||||
{AMOVW, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVWU, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVV, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVB, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVBU, C_LEXT, C_NONE, C_REG, 36, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVW, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, 0, 0},
|
||||
{AMOVWU, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, sys.MIPS64, 0},
|
||||
{AMOVV, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, sys.MIPS64, 0},
|
||||
{AMOVB, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, 0, 0},
|
||||
{AMOVBU, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP, 0, 0},
|
||||
{AMOVW, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, 0, 0},
|
||||
{AMOVWU, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, sys.MIPS64, 0},
|
||||
{AMOVV, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, sys.MIPS64, 0},
|
||||
{AMOVB, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, 0, 0},
|
||||
{AMOVBU, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO, 0, 0},
|
||||
{AMOVW, C_ADDR, C_NONE, C_REG, 51, 8, 0, sys.MIPS, 0},
|
||||
{AMOVW, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVWU, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVV, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVB, C_ADDR, C_NONE, C_REG, 51, 8, 0, sys.MIPS, 0},
|
||||
{AMOVB, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVBU, C_ADDR, C_NONE, C_REG, 51, 8, 0, sys.MIPS, 0},
|
||||
{AMOVBU, C_ADDR, C_NONE, C_REG, 51, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVW, C_TLS, C_NONE, C_REG, 54, 8, 0, 0, 0},
|
||||
{AMOVWU, C_TLS, C_NONE, C_REG, 54, 8, 0, sys.MIPS64, 0},
|
||||
{AMOVV, C_TLS, C_NONE, C_REG, 54, 8, 0, sys.MIPS64, 0},
|
||||
{AMOVB, C_TLS, C_NONE, C_REG, 54, 8, 0, 0, 0},
|
||||
{AMOVBU, C_TLS, C_NONE, C_REG, 54, 8, 0, 0, 0},
|
||||
|
||||
{AMOVW, C_SECON, C_NONE, C_REG, 3, 4, REGSB, sys.MIPS64},
|
||||
{AMOVV, C_SECON, C_NONE, C_REG, 3, 4, REGSB, sys.MIPS64},
|
||||
{AMOVW, C_SACON, C_NONE, C_REG, 3, 4, REGSP, 0},
|
||||
{AMOVV, C_SACON, C_NONE, C_REG, 3, 4, REGSP, sys.MIPS64},
|
||||
{AMOVW, C_LECON, C_NONE, C_REG, 52, 8, REGSB, sys.MIPS},
|
||||
{AMOVW, C_LECON, C_NONE, C_REG, 52, 12, REGSB, sys.MIPS64},
|
||||
{AMOVV, C_LECON, C_NONE, C_REG, 52, 12, REGSB, sys.MIPS64},
|
||||
{AMOVW, C_SECON, C_NONE, C_REG, 3, 4, REGSB, sys.MIPS64, 0},
|
||||
{AMOVV, C_SECON, C_NONE, C_REG, 3, 4, REGSB, sys.MIPS64, 0},
|
||||
{AMOVW, C_SACON, C_NONE, C_REG, 3, 4, REGSP, 0, 0},
|
||||
{AMOVV, C_SACON, C_NONE, C_REG, 3, 4, REGSP, sys.MIPS64, 0},
|
||||
{AMOVW, C_LECON, C_NONE, C_REG, 52, 8, REGSB, sys.MIPS, 0},
|
||||
{AMOVW, C_LECON, C_NONE, C_REG, 52, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVV, C_LECON, C_NONE, C_REG, 52, 12, REGSB, sys.MIPS64, 0},
|
||||
|
||||
{AMOVW, C_LACON, C_NONE, C_REG, 26, 12, REGSP, 0},
|
||||
{AMOVV, C_LACON, C_NONE, C_REG, 26, 12, REGSP, sys.MIPS64},
|
||||
{AMOVW, C_ADDCON, C_NONE, C_REG, 3, 4, REGZERO, 0},
|
||||
{AMOVV, C_ADDCON, C_NONE, C_REG, 3, 4, REGZERO, sys.MIPS64},
|
||||
{AMOVW, C_ANDCON, C_NONE, C_REG, 3, 4, REGZERO, 0},
|
||||
{AMOVV, C_ANDCON, C_NONE, C_REG, 3, 4, REGZERO, sys.MIPS64},
|
||||
{AMOVW, C_STCON, C_NONE, C_REG, 55, 8, 0, 0},
|
||||
{AMOVV, C_STCON, C_NONE, C_REG, 55, 8, 0, sys.MIPS64},
|
||||
{AMOVW, C_LACON, C_NONE, C_REG, 26, 12, REGSP, 0, 0},
|
||||
{AMOVV, C_LACON, C_NONE, C_REG, 26, 12, REGSP, sys.MIPS64, 0},
|
||||
{AMOVW, C_ADDCON, C_NONE, C_REG, 3, 4, REGZERO, 0, 0},
|
||||
{AMOVV, C_ADDCON, C_NONE, C_REG, 3, 4, REGZERO, sys.MIPS64, 0},
|
||||
{AMOVW, C_ANDCON, C_NONE, C_REG, 3, 4, REGZERO, 0, 0},
|
||||
{AMOVV, C_ANDCON, C_NONE, C_REG, 3, 4, REGZERO, sys.MIPS64, 0},
|
||||
{AMOVW, C_STCON, C_NONE, C_REG, 55, 8, 0, 0, 0},
|
||||
{AMOVV, C_STCON, C_NONE, C_REG, 55, 8, 0, sys.MIPS64, 0},
|
||||
|
||||
{AMOVW, C_UCON, C_NONE, C_REG, 24, 4, 0, 0},
|
||||
{AMOVV, C_UCON, C_NONE, C_REG, 24, 4, 0, sys.MIPS64},
|
||||
{AMOVW, C_LCON, C_NONE, C_REG, 19, 8, 0, 0},
|
||||
{AMOVV, C_LCON, C_NONE, C_REG, 19, 8, 0, sys.MIPS64},
|
||||
{AMOVW, C_UCON, C_NONE, C_REG, 24, 4, 0, 0, 0},
|
||||
{AMOVV, C_UCON, C_NONE, C_REG, 24, 4, 0, sys.MIPS64, 0},
|
||||
{AMOVW, C_LCON, C_NONE, C_REG, 19, 8, 0, 0, 0},
|
||||
{AMOVV, C_LCON, C_NONE, C_REG, 19, 8, 0, sys.MIPS64, 0},
|
||||
|
||||
{AMOVW, C_HI, C_NONE, C_REG, 20, 4, 0, 0},
|
||||
{AMOVV, C_HI, C_NONE, C_REG, 20, 4, 0, sys.MIPS64},
|
||||
{AMOVW, C_LO, C_NONE, C_REG, 20, 4, 0, 0},
|
||||
{AMOVV, C_LO, C_NONE, C_REG, 20, 4, 0, sys.MIPS64},
|
||||
{AMOVW, C_REG, C_NONE, C_HI, 21, 4, 0, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_HI, 21, 4, 0, sys.MIPS64},
|
||||
{AMOVW, C_REG, C_NONE, C_LO, 21, 4, 0, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_LO, 21, 4, 0, sys.MIPS64},
|
||||
{AMOVW, C_HI, C_NONE, C_REG, 20, 4, 0, 0, 0},
|
||||
{AMOVV, C_HI, C_NONE, C_REG, 20, 4, 0, sys.MIPS64, 0},
|
||||
{AMOVW, C_LO, C_NONE, C_REG, 20, 4, 0, 0, 0},
|
||||
{AMOVV, C_LO, C_NONE, C_REG, 20, 4, 0, sys.MIPS64, 0},
|
||||
{AMOVW, C_REG, C_NONE, C_HI, 21, 4, 0, 0, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_HI, 21, 4, 0, sys.MIPS64, 0},
|
||||
{AMOVW, C_REG, C_NONE, C_LO, 21, 4, 0, 0, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_LO, 21, 4, 0, sys.MIPS64, 0},
|
||||
|
||||
{AMUL, C_REG, C_REG, C_NONE, 22, 4, 0, 0},
|
||||
{AMUL, C_REG, C_REG, C_REG, 22, 4, 0, 0},
|
||||
{AMULV, C_REG, C_REG, C_NONE, 22, 4, 0, sys.MIPS64},
|
||||
{AMUL, C_REG, C_REG, C_NONE, 22, 4, 0, 0, 0},
|
||||
{AMUL, C_REG, C_REG, C_REG, 22, 4, 0, 0, 0},
|
||||
{AMULV, C_REG, C_REG, C_NONE, 22, 4, 0, sys.MIPS64, 0},
|
||||
|
||||
{AADD, C_ADD0CON, C_REG, C_REG, 4, 4, 0, 0},
|
||||
{AADD, C_ADD0CON, C_NONE, C_REG, 4, 4, 0, 0},
|
||||
{AADD, C_ANDCON, C_REG, C_REG, 10, 8, 0, 0},
|
||||
{AADD, C_ANDCON, C_NONE, C_REG, 10, 8, 0, 0},
|
||||
{AADD, C_ADD0CON, C_REG, C_REG, 4, 4, 0, 0, 0},
|
||||
{AADD, C_ADD0CON, C_NONE, C_REG, 4, 4, 0, 0, 0},
|
||||
{AADD, C_ANDCON, C_REG, C_REG, 10, 8, 0, 0, 0},
|
||||
{AADD, C_ANDCON, C_NONE, C_REG, 10, 8, 0, 0, 0},
|
||||
|
||||
{AADDV, C_ADD0CON, C_REG, C_REG, 4, 4, 0, sys.MIPS64},
|
||||
{AADDV, C_ADD0CON, C_NONE, C_REG, 4, 4, 0, sys.MIPS64},
|
||||
{AADDV, C_ANDCON, C_REG, C_REG, 10, 8, 0, sys.MIPS64},
|
||||
{AADDV, C_ANDCON, C_NONE, C_REG, 10, 8, 0, sys.MIPS64},
|
||||
{AADDV, C_ADD0CON, C_REG, C_REG, 4, 4, 0, sys.MIPS64, 0},
|
||||
{AADDV, C_ADD0CON, C_NONE, C_REG, 4, 4, 0, sys.MIPS64, 0},
|
||||
{AADDV, C_ANDCON, C_REG, C_REG, 10, 8, 0, sys.MIPS64, 0},
|
||||
{AADDV, C_ANDCON, C_NONE, C_REG, 10, 8, 0, sys.MIPS64, 0},
|
||||
|
||||
{AAND, C_AND0CON, C_REG, C_REG, 4, 4, 0, 0},
|
||||
{AAND, C_AND0CON, C_NONE, C_REG, 4, 4, 0, 0},
|
||||
{AAND, C_ADDCON, C_REG, C_REG, 10, 8, 0, 0},
|
||||
{AAND, C_ADDCON, C_NONE, C_REG, 10, 8, 0, 0},
|
||||
{AAND, C_AND0CON, C_REG, C_REG, 4, 4, 0, 0, 0},
|
||||
{AAND, C_AND0CON, C_NONE, C_REG, 4, 4, 0, 0, 0},
|
||||
{AAND, C_ADDCON, C_REG, C_REG, 10, 8, 0, 0, 0},
|
||||
{AAND, C_ADDCON, C_NONE, C_REG, 10, 8, 0, 0, 0},
|
||||
|
||||
{AADD, C_UCON, C_REG, C_REG, 25, 8, 0, 0},
|
||||
{AADD, C_UCON, C_NONE, C_REG, 25, 8, 0, 0},
|
||||
{AADDV, C_UCON, C_REG, C_REG, 25, 8, 0, sys.MIPS64},
|
||||
{AADDV, C_UCON, C_NONE, C_REG, 25, 8, 0, sys.MIPS64},
|
||||
{AAND, C_UCON, C_REG, C_REG, 25, 8, 0, 0},
|
||||
{AAND, C_UCON, C_NONE, C_REG, 25, 8, 0, 0},
|
||||
{AADD, C_UCON, C_REG, C_REG, 25, 8, 0, 0, 0},
|
||||
{AADD, C_UCON, C_NONE, C_REG, 25, 8, 0, 0, 0},
|
||||
{AADDV, C_UCON, C_REG, C_REG, 25, 8, 0, sys.MIPS64, 0},
|
||||
{AADDV, C_UCON, C_NONE, C_REG, 25, 8, 0, sys.MIPS64, 0},
|
||||
{AAND, C_UCON, C_REG, C_REG, 25, 8, 0, 0, 0},
|
||||
{AAND, C_UCON, C_NONE, C_REG, 25, 8, 0, 0, 0},
|
||||
|
||||
{AADD, C_LCON, C_NONE, C_REG, 23, 12, 0, 0},
|
||||
{AADDV, C_LCON, C_NONE, C_REG, 23, 12, 0, sys.MIPS64},
|
||||
{AAND, C_LCON, C_NONE, C_REG, 23, 12, 0, 0},
|
||||
{AADD, C_LCON, C_REG, C_REG, 23, 12, 0, 0},
|
||||
{AADDV, C_LCON, C_REG, C_REG, 23, 12, 0, sys.MIPS64},
|
||||
{AAND, C_LCON, C_REG, C_REG, 23, 12, 0, 0},
|
||||
{AADD, C_LCON, C_NONE, C_REG, 23, 12, 0, 0, 0},
|
||||
{AADDV, C_LCON, C_NONE, C_REG, 23, 12, 0, sys.MIPS64, 0},
|
||||
{AAND, C_LCON, C_NONE, C_REG, 23, 12, 0, 0, 0},
|
||||
{AADD, C_LCON, C_REG, C_REG, 23, 12, 0, 0, 0},
|
||||
{AADDV, C_LCON, C_REG, C_REG, 23, 12, 0, sys.MIPS64, 0},
|
||||
{AAND, C_LCON, C_REG, C_REG, 23, 12, 0, 0, 0},
|
||||
|
||||
{ASLL, C_SCON, C_REG, C_REG, 16, 4, 0, 0},
|
||||
{ASLL, C_SCON, C_NONE, C_REG, 16, 4, 0, 0},
|
||||
{ASLL, C_SCON, C_REG, C_REG, 16, 4, 0, 0, 0},
|
||||
{ASLL, C_SCON, C_NONE, C_REG, 16, 4, 0, 0, 0},
|
||||
|
||||
{ASLLV, C_SCON, C_REG, C_REG, 16, 4, 0, sys.MIPS64},
|
||||
{ASLLV, C_SCON, C_NONE, C_REG, 16, 4, 0, sys.MIPS64},
|
||||
{ASLLV, C_SCON, C_REG, C_REG, 16, 4, 0, sys.MIPS64, 0},
|
||||
{ASLLV, C_SCON, C_NONE, C_REG, 16, 4, 0, sys.MIPS64, 0},
|
||||
|
||||
{ASYSCALL, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
|
||||
{ASYSCALL, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0, 0},
|
||||
|
||||
{ABEQ, C_REG, C_REG, C_SBRA, 6, 4, 0, 0},
|
||||
{ABEQ, C_REG, C_NONE, C_SBRA, 6, 4, 0, 0},
|
||||
{ABLEZ, C_REG, C_NONE, C_SBRA, 6, 4, 0, 0},
|
||||
{ABFPT, C_NONE, C_NONE, C_SBRA, 6, 8, 0, 0},
|
||||
{ABEQ, C_REG, C_REG, C_SBRA, 6, 4, 0, 0, 0},
|
||||
{ABEQ, C_REG, C_NONE, C_SBRA, 6, 4, 0, 0, 0},
|
||||
{ABLEZ, C_REG, C_NONE, C_SBRA, 6, 4, 0, 0, 0},
|
||||
{ABFPT, C_NONE, C_NONE, C_SBRA, 6, 8, 0, 0, 0},
|
||||
|
||||
{AJMP, C_NONE, C_NONE, C_LBRA, 11, 4, 0, 0},
|
||||
{AJAL, C_NONE, C_NONE, C_LBRA, 11, 4, 0, 0},
|
||||
{AJMP, C_NONE, C_NONE, C_LBRA, 11, 4, 0, 0, 0},
|
||||
{AJAL, C_NONE, C_NONE, C_LBRA, 11, 4, 0, 0, 0},
|
||||
|
||||
{AJMP, C_NONE, C_NONE, C_ZOREG, 18, 4, REGZERO, 0},
|
||||
{AJAL, C_NONE, C_NONE, C_ZOREG, 18, 4, REGLINK, 0},
|
||||
{AJMP, C_NONE, C_NONE, C_ZOREG, 18, 4, REGZERO, 0, 0},
|
||||
{AJAL, C_NONE, C_NONE, C_ZOREG, 18, 4, REGLINK, 0, 0},
|
||||
|
||||
{AMOVW, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, sys.MIPS64},
|
||||
{AMOVF, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, sys.MIPS64},
|
||||
{AMOVD, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, sys.MIPS64},
|
||||
{AMOVW, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP, sys.MIPS64},
|
||||
{AMOVF, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP, 0},
|
||||
{AMOVD, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP, 0},
|
||||
{AMOVW, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO, sys.MIPS64},
|
||||
{AMOVF, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO, 0},
|
||||
{AMOVD, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO, 0},
|
||||
{AMOVW, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, sys.MIPS64, 0},
|
||||
{AMOVF, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, sys.MIPS64, 0},
|
||||
{AMOVD, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB, sys.MIPS64, 0},
|
||||
{AMOVW, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP, sys.MIPS64, 0},
|
||||
{AMOVF, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP, 0, 0},
|
||||
{AMOVD, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP, 0, 0},
|
||||
{AMOVW, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO, sys.MIPS64, 0},
|
||||
{AMOVF, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO, 0, 0},
|
||||
{AMOVD, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO, 0, 0},
|
||||
|
||||
{AMOVW, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, sys.MIPS64},
|
||||
{AMOVF, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, sys.MIPS64},
|
||||
{AMOVD, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, sys.MIPS64},
|
||||
{AMOVW, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP, sys.MIPS64},
|
||||
{AMOVF, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP, 0},
|
||||
{AMOVD, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP, 0},
|
||||
{AMOVW, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO, sys.MIPS64},
|
||||
{AMOVF, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO, 0},
|
||||
{AMOVD, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO, 0},
|
||||
{AMOVF, C_ADDR, C_NONE, C_FREG, 51, 8, 0, sys.MIPS},
|
||||
{AMOVF, C_ADDR, C_NONE, C_FREG, 51, 12, 0, sys.MIPS64},
|
||||
{AMOVD, C_ADDR, C_NONE, C_FREG, 51, 8, 0, sys.MIPS},
|
||||
{AMOVD, C_ADDR, C_NONE, C_FREG, 51, 12, 0, sys.MIPS64},
|
||||
{AMOVW, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVF, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVD, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVW, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP, sys.MIPS64, 0},
|
||||
{AMOVF, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP, 0, 0},
|
||||
{AMOVD, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP, 0, 0},
|
||||
{AMOVW, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO, sys.MIPS64, 0},
|
||||
{AMOVF, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO, 0, 0},
|
||||
{AMOVD, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO, 0, 0},
|
||||
{AMOVF, C_ADDR, C_NONE, C_FREG, 51, 8, 0, sys.MIPS, 0},
|
||||
{AMOVF, C_ADDR, C_NONE, C_FREG, 51, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVD, C_ADDR, C_NONE, C_FREG, 51, 8, 0, sys.MIPS, 0},
|
||||
{AMOVD, C_ADDR, C_NONE, C_FREG, 51, 12, 0, sys.MIPS64, 0},
|
||||
|
||||
{AMOVW, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, sys.MIPS64},
|
||||
{AMOVF, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, sys.MIPS64},
|
||||
{AMOVD, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, sys.MIPS64},
|
||||
{AMOVW, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP, sys.MIPS64},
|
||||
{AMOVF, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP, 0},
|
||||
{AMOVW, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO, sys.MIPS64},
|
||||
{AMOVF, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO, 0},
|
||||
{AMOVW, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, sys.MIPS64, 0},
|
||||
{AMOVF, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, sys.MIPS64, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB, sys.MIPS64, 0},
|
||||
{AMOVW, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP, sys.MIPS64, 0},
|
||||
{AMOVF, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP, 0, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP, 0, 0},
|
||||
{AMOVW, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO, sys.MIPS64, 0},
|
||||
{AMOVF, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO, 0, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO, 0, 0},
|
||||
|
||||
{AMOVW, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, sys.MIPS64},
|
||||
{AMOVF, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, sys.MIPS64},
|
||||
{AMOVD, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, sys.MIPS64},
|
||||
{AMOVW, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP, sys.MIPS64},
|
||||
{AMOVF, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP, 0},
|
||||
{AMOVW, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO, sys.MIPS64},
|
||||
{AMOVF, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO, 0},
|
||||
{AMOVF, C_FREG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS},
|
||||
{AMOVF, C_FREG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
|
||||
{AMOVD, C_FREG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS},
|
||||
{AMOVD, C_FREG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64},
|
||||
{AMOVW, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVF, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB, sys.MIPS64, 0},
|
||||
{AMOVW, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP, sys.MIPS64, 0},
|
||||
{AMOVF, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP, 0, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP, 0, 0},
|
||||
{AMOVW, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO, sys.MIPS64, 0},
|
||||
{AMOVF, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO, 0, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO, 0, 0},
|
||||
{AMOVF, C_FREG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS, 0},
|
||||
{AMOVF, C_FREG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_ADDR, 50, 8, 0, sys.MIPS, 0},
|
||||
{AMOVD, C_FREG, C_NONE, C_ADDR, 50, 12, 0, sys.MIPS64, 0},
|
||||
|
||||
{AMOVW, C_REG, C_NONE, C_FREG, 30, 4, 0, 0},
|
||||
{AMOVW, C_FREG, C_NONE, C_REG, 31, 4, 0, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_FREG, 47, 4, 0, sys.MIPS64},
|
||||
{AMOVV, C_FREG, C_NONE, C_REG, 48, 4, 0, sys.MIPS64},
|
||||
{AMOVW, C_REG, C_NONE, C_FREG, 30, 4, 0, 0, 0},
|
||||
{AMOVW, C_FREG, C_NONE, C_REG, 31, 4, 0, 0, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_FREG, 47, 4, 0, sys.MIPS64, 0},
|
||||
{AMOVV, C_FREG, C_NONE, C_REG, 48, 4, 0, sys.MIPS64, 0},
|
||||
|
||||
{AMOVW, C_ADDCON, C_NONE, C_FREG, 34, 8, 0, sys.MIPS64},
|
||||
{AMOVW, C_ANDCON, C_NONE, C_FREG, 34, 8, 0, sys.MIPS64},
|
||||
{AMOVW, C_ADDCON, C_NONE, C_FREG, 34, 8, 0, sys.MIPS64, 0},
|
||||
{AMOVW, C_ANDCON, C_NONE, C_FREG, 34, 8, 0, sys.MIPS64, 0},
|
||||
|
||||
{AMOVW, C_REG, C_NONE, C_MREG, 37, 4, 0, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_MREG, 37, 4, 0, sys.MIPS64},
|
||||
{AMOVW, C_MREG, C_NONE, C_REG, 38, 4, 0, 0},
|
||||
{AMOVV, C_MREG, C_NONE, C_REG, 38, 4, 0, sys.MIPS64},
|
||||
{AMOVW, C_REG, C_NONE, C_MREG, 37, 4, 0, 0, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_MREG, 37, 4, 0, sys.MIPS64, 0},
|
||||
{AMOVW, C_MREG, C_NONE, C_REG, 38, 4, 0, 0, 0},
|
||||
{AMOVV, C_MREG, C_NONE, C_REG, 38, 4, 0, sys.MIPS64, 0},
|
||||
|
||||
{AWORD, C_LCON, C_NONE, C_NONE, 40, 4, 0, 0},
|
||||
{AWORD, C_LCON, C_NONE, C_NONE, 40, 4, 0, 0, 0},
|
||||
|
||||
{AMOVW, C_REG, C_NONE, C_FCREG, 41, 4, 0, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_FCREG, 41, 4, 0, sys.MIPS64},
|
||||
{AMOVW, C_FCREG, C_NONE, C_REG, 42, 4, 0, 0},
|
||||
{AMOVV, C_FCREG, C_NONE, C_REG, 42, 4, 0, sys.MIPS64},
|
||||
{AMOVW, C_REG, C_NONE, C_FCREG, 41, 4, 0, 0, 0},
|
||||
{AMOVV, C_REG, C_NONE, C_FCREG, 41, 4, 0, sys.MIPS64, 0},
|
||||
{AMOVW, C_FCREG, C_NONE, C_REG, 42, 4, 0, 0, 0},
|
||||
{AMOVV, C_FCREG, C_NONE, C_REG, 42, 4, 0, sys.MIPS64, 0},
|
||||
|
||||
{ATEQ, C_SCON, C_REG, C_REG, 15, 4, 0, 0},
|
||||
{ATEQ, C_SCON, C_NONE, C_REG, 15, 4, 0, 0},
|
||||
{ACMOVT, C_REG, C_NONE, C_REG, 17, 4, 0, 0},
|
||||
{ATEQ, C_SCON, C_REG, C_REG, 15, 4, 0, 0, 0},
|
||||
{ATEQ, C_SCON, C_NONE, C_REG, 15, 4, 0, 0, 0},
|
||||
{ACMOVT, C_REG, C_NONE, C_REG, 17, 4, 0, 0, 0},
|
||||
|
||||
{ABREAK, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64}, /* really CACHE instruction */
|
||||
{ABREAK, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64},
|
||||
{ABREAK, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64},
|
||||
{ABREAK, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
|
||||
{ABREAK, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0}, /* really CACHE instruction */
|
||||
{ABREAK, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64, 0},
|
||||
{ABREAK, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64, 0},
|
||||
{ABREAK, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0, 0},
|
||||
|
||||
{obj.AUNDEF, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0},
|
||||
{obj.APCDATA, C_LCON, C_NONE, C_LCON, 0, 0, 0, 0},
|
||||
{obj.AFUNCDATA, C_SCON, C_NONE, C_ADDR, 0, 0, 0, 0},
|
||||
{obj.ANOP, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
|
||||
{obj.ADUFFZERO, C_NONE, C_NONE, C_LBRA, 11, 4, 0, 0}, // same as AJMP
|
||||
{obj.ADUFFCOPY, C_NONE, C_NONE, C_LBRA, 11, 4, 0, 0}, // same as AJMP
|
||||
{obj.AUNDEF, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0, 0},
|
||||
{obj.APCDATA, C_LCON, C_NONE, C_LCON, 0, 0, 0, 0, 0},
|
||||
{obj.AFUNCDATA, C_SCON, C_NONE, C_ADDR, 0, 0, 0, 0, 0},
|
||||
{obj.ANOP, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0, 0},
|
||||
{obj.ADUFFZERO, C_NONE, C_NONE, C_LBRA, 11, 4, 0, 0, 0}, // same as AJMP
|
||||
{obj.ADUFFCOPY, C_NONE, C_NONE, C_LBRA, 11, 4, 0, 0, 0}, // same as AJMP
|
||||
|
||||
{obj.AXXX, C_NONE, C_NONE, C_NONE, 0, 4, 0, 0},
|
||||
{obj.AXXX, C_NONE, C_NONE, C_NONE, 0, 4, 0, 0, 0},
|
||||
}
|
||||
|
||||
var oprange [ALAST & obj.AMask][]Optab
|
||||
@ -736,7 +737,7 @@ func (c *ctxt0) oplook(p *obj.Prog) *Optab {
|
||||
c.ctxt.Diag("illegal combination %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3))
|
||||
prasm(p)
|
||||
// Turn illegal instruction into an UNDEF, avoid crashing in asmout.
|
||||
return &Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0}
|
||||
return &Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0, 0}
|
||||
}
|
||||
|
||||
func cmp(a int, b int) bool {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user