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test/codegen: add riscv64/rva23u64 specifiers to existing tests

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Tests that exist for riscv64/rva22u64 should also be applied to
riscv64/rva23u64.

Change-Id: Ia529fdf0ac55b8bcb3dcd24fa80efef2351f3842
Reviewed-on: https://go-review.googlesource.com/c/go/+/652315
Reviewed-by: Cherry Mui <cherryyz@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Joel Sing 2025-02-23 22:31:35 +11:00
parent 3c3b8dd4f0
commit c01fa0cc21
2 changed files with 7 additions and 7 deletions
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8
test/codegen/arithmetic.go
View File

@ -647,7 +647,7 @@ func Int64Min(a, b int64) int64 {
// amd64: "CMPQ","CMOVQLT"
// arm64: "CMP","CSEL"
// riscv64/rva20u64:"BLT\t"
// riscv64/rva22u64:"MIN\t"
// riscv64/rva22u64,riscv64/rva23u64:"MIN\t"
return min(a, b)
}
@ -655,7 +655,7 @@ func Int64Max(a, b int64) int64 {
// amd64: "CMPQ","CMOVQGT"
// arm64: "CMP","CSEL"
// riscv64/rva20u64:"BLT\t"
// riscv64/rva22u64:"MAX\t"
// riscv64/rva22u64,riscv64/rva23u64:"MAX\t"
return max(a, b)
}
@ -663,7 +663,7 @@ func Uint64Min(a, b uint64) uint64 {
// amd64: "CMPQ","CMOVQCS"
// arm64: "CMP","CSEL"
// riscv64/rva20u64:"BLTU"
// riscv64/rva22u64:"MINU"
// riscv64/rva22u64,riscv64/rva23u64:"MINU"
return min(a, b)
}
@ -671,6 +671,6 @@ func Uint64Max(a, b uint64) uint64 {
// amd64: "CMPQ","CMOVQHI"
// arm64: "CMP","CSEL"
// riscv64/rva20u64:"BLTU"
// riscv64/rva22u64:"MAXU"
// riscv64/rva22u64,riscv64/rva23u64:"MAXU"
return max(a, b)
}

6
test/codegen/shift.go
View File

@ -582,13 +582,13 @@ func checkShiftToMask(u []uint64, s []int64) {
func checkLeftShiftWithAddition(a int64, b int64) int64 {
// riscv64/rva20u64: "SLLI","ADD"
// riscv64/rva22u64: "SH1ADD"
// riscv64/rva22u64,riscv64/rva23u64: "SH1ADD"
a = a + b<<1
// riscv64/rva20u64: "SLLI","ADD"
// riscv64/rva22u64: "SH2ADD"
// riscv64/rva22u64,riscv64/rva23u64: "SH2ADD"
a = a + b<<2
// riscv64/rva20u64: "SLLI","ADD"
// riscv64/rva22u64: "SH3ADD"
// riscv64/rva22u64,riscv64/rva23u64: "SH3ADD"
a = a + b<<3
return a
}