diff --git a/src/internal/cpu/cpu_loong64.go b/src/internal/cpu/cpu_loong64.go
index d8403d731a..1c90c24fe3 100644
--- a/src/internal/cpu/cpu_loong64.go
+++ b/src/internal/cpu/cpu_loong64.go
@@ -6,6 +6,8 @@
 
 package cpu
 
-const CacheLinePadSize = 32
+// CacheLinePadSize is used to prevent false sharing of cache lines.
+// We choose 64 because Loongson 3A5000 the L1 Dcache is 4-way 256-line 64-byte-per-line.
+const CacheLinePadSize = 64
 
 func doinit() {}