mirror of
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d84cbec890
Update #36468 Change-Id: Idfdb845d097994689be450d6e8a57fa9adb57166 Reviewed-on: https://go-review.googlesource.com/c/go/+/222782 Run-TryBot: Keith Randall <khr@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
226 lines
8.8 KiB
Go
226 lines
8.8 KiB
Go
// Copyright 2020 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package ssa
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// addressingModes combines address calculations into memory operations
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// that can perform complicated addressing modes.
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func addressingModes(f *Func) {
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switch f.Config.arch {
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default:
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// Most architectures can't do this.
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return
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case "amd64", "386":
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// TODO: s390x?
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}
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var tmp []*Value
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for _, b := range f.Blocks {
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for _, v := range b.Values {
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if !combineFirst[v.Op] {
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continue
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}
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// All matched operations have the pointer in arg[0].
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// All results have the pointer in arg[0] and the index in arg[1].
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// *Except* for operations which update a register,
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// which are marked with resultInArg0. Those have
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// the pointer in arg[1], and the corresponding result op
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// has the pointer in arg[1] and the index in arg[2].
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ptrIndex := 0
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if opcodeTable[v.Op].resultInArg0 {
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ptrIndex = 1
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}
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p := v.Args[ptrIndex]
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c, ok := combine[[2]Op{v.Op, p.Op}]
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if !ok {
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continue
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}
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// See if we can combine the Aux/AuxInt values.
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switch [2]auxType{opcodeTable[v.Op].auxType, opcodeTable[p.Op].auxType} {
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case [2]auxType{auxSymOff, auxInt32}:
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// TODO: introduce auxSymOff32
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if !is32Bit(v.AuxInt + p.AuxInt) {
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continue
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}
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v.AuxInt += p.AuxInt
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case [2]auxType{auxSymOff, auxSymOff}:
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if v.Aux != nil && p.Aux != nil {
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continue
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}
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if !is32Bit(v.AuxInt + p.AuxInt) {
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continue
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}
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if p.Aux != nil {
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v.Aux = p.Aux
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}
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v.AuxInt += p.AuxInt
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case [2]auxType{auxSymValAndOff, auxInt32}:
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vo := ValAndOff(v.AuxInt)
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if !vo.canAdd(p.AuxInt) {
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continue
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}
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v.AuxInt = vo.add(p.AuxInt)
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case [2]auxType{auxSymValAndOff, auxSymOff}:
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vo := ValAndOff(v.AuxInt)
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if v.Aux != nil && p.Aux != nil {
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continue
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}
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if !vo.canAdd(p.AuxInt) {
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continue
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}
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if p.Aux != nil {
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v.Aux = p.Aux
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}
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v.AuxInt = vo.add(p.AuxInt)
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case [2]auxType{auxSymOff, auxNone}:
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// nothing to do
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case [2]auxType{auxSymValAndOff, auxNone}:
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// nothing to do
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default:
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f.Fatalf("unknown aux combining for %s and %s\n", v.Op, p.Op)
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}
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// Combine the operations.
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tmp = append(tmp[:0], v.Args[:ptrIndex]...)
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tmp = append(tmp, p.Args...)
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tmp = append(tmp, v.Args[ptrIndex+1:]...)
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v.resetArgs()
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v.Op = c
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v.AddArgs(tmp...)
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}
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}
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}
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// combineFirst contains ops which appear in combine as the
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// first part of the key.
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var combineFirst = map[Op]bool{}
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func init() {
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for k := range combine {
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combineFirst[k[0]] = true
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}
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}
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// For each entry k, v in this map, if we have a value x with:
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// x.Op == k[0]
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// x.Args[0].Op == k[1]
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// then we can set x.Op to v and set x.Args like this:
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// x.Args[0].Args + x.Args[1:]
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// Additionally, the Aux/AuxInt from x.Args[0] is merged into x.
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var combine = map[[2]Op]Op{
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// amd64
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[2]Op{OpAMD64MOVBload, OpAMD64ADDQ}: OpAMD64MOVBloadidx1,
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[2]Op{OpAMD64MOVWload, OpAMD64ADDQ}: OpAMD64MOVWloadidx1,
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[2]Op{OpAMD64MOVLload, OpAMD64ADDQ}: OpAMD64MOVLloadidx1,
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[2]Op{OpAMD64MOVQload, OpAMD64ADDQ}: OpAMD64MOVQloadidx1,
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[2]Op{OpAMD64MOVSSload, OpAMD64ADDQ}: OpAMD64MOVSSloadidx1,
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[2]Op{OpAMD64MOVSDload, OpAMD64ADDQ}: OpAMD64MOVSDloadidx1,
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[2]Op{OpAMD64MOVBstore, OpAMD64ADDQ}: OpAMD64MOVBstoreidx1,
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[2]Op{OpAMD64MOVWstore, OpAMD64ADDQ}: OpAMD64MOVWstoreidx1,
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[2]Op{OpAMD64MOVLstore, OpAMD64ADDQ}: OpAMD64MOVLstoreidx1,
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[2]Op{OpAMD64MOVQstore, OpAMD64ADDQ}: OpAMD64MOVQstoreidx1,
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[2]Op{OpAMD64MOVSSstore, OpAMD64ADDQ}: OpAMD64MOVSSstoreidx1,
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[2]Op{OpAMD64MOVSDstore, OpAMD64ADDQ}: OpAMD64MOVSDstoreidx1,
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[2]Op{OpAMD64MOVBstoreconst, OpAMD64ADDQ}: OpAMD64MOVBstoreconstidx1,
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[2]Op{OpAMD64MOVWstoreconst, OpAMD64ADDQ}: OpAMD64MOVWstoreconstidx1,
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[2]Op{OpAMD64MOVLstoreconst, OpAMD64ADDQ}: OpAMD64MOVLstoreconstidx1,
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[2]Op{OpAMD64MOVQstoreconst, OpAMD64ADDQ}: OpAMD64MOVQstoreconstidx1,
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[2]Op{OpAMD64MOVBload, OpAMD64LEAQ1}: OpAMD64MOVBloadidx1,
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[2]Op{OpAMD64MOVWload, OpAMD64LEAQ1}: OpAMD64MOVWloadidx1,
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[2]Op{OpAMD64MOVWload, OpAMD64LEAQ2}: OpAMD64MOVWloadidx2,
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[2]Op{OpAMD64MOVLload, OpAMD64LEAQ1}: OpAMD64MOVLloadidx1,
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[2]Op{OpAMD64MOVLload, OpAMD64LEAQ4}: OpAMD64MOVLloadidx4,
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[2]Op{OpAMD64MOVLload, OpAMD64LEAQ8}: OpAMD64MOVLloadidx8,
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[2]Op{OpAMD64MOVQload, OpAMD64LEAQ1}: OpAMD64MOVQloadidx1,
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[2]Op{OpAMD64MOVQload, OpAMD64LEAQ8}: OpAMD64MOVQloadidx8,
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[2]Op{OpAMD64MOVSSload, OpAMD64LEAQ1}: OpAMD64MOVSSloadidx1,
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[2]Op{OpAMD64MOVSSload, OpAMD64LEAQ4}: OpAMD64MOVSSloadidx4,
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[2]Op{OpAMD64MOVSDload, OpAMD64LEAQ1}: OpAMD64MOVSDloadidx1,
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[2]Op{OpAMD64MOVSDload, OpAMD64LEAQ8}: OpAMD64MOVSDloadidx8,
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[2]Op{OpAMD64MOVBstore, OpAMD64LEAQ1}: OpAMD64MOVBstoreidx1,
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[2]Op{OpAMD64MOVWstore, OpAMD64LEAQ1}: OpAMD64MOVWstoreidx1,
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[2]Op{OpAMD64MOVWstore, OpAMD64LEAQ2}: OpAMD64MOVWstoreidx2,
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[2]Op{OpAMD64MOVLstore, OpAMD64LEAQ1}: OpAMD64MOVLstoreidx1,
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[2]Op{OpAMD64MOVLstore, OpAMD64LEAQ4}: OpAMD64MOVLstoreidx4,
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[2]Op{OpAMD64MOVLstore, OpAMD64LEAQ8}: OpAMD64MOVLstoreidx8,
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[2]Op{OpAMD64MOVQstore, OpAMD64LEAQ1}: OpAMD64MOVQstoreidx1,
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[2]Op{OpAMD64MOVQstore, OpAMD64LEAQ8}: OpAMD64MOVQstoreidx8,
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[2]Op{OpAMD64MOVSSstore, OpAMD64LEAQ1}: OpAMD64MOVSSstoreidx1,
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[2]Op{OpAMD64MOVSSstore, OpAMD64LEAQ4}: OpAMD64MOVSSstoreidx4,
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[2]Op{OpAMD64MOVSDstore, OpAMD64LEAQ1}: OpAMD64MOVSDstoreidx1,
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[2]Op{OpAMD64MOVSDstore, OpAMD64LEAQ8}: OpAMD64MOVSDstoreidx8,
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[2]Op{OpAMD64MOVBstoreconst, OpAMD64LEAQ1}: OpAMD64MOVBstoreconstidx1,
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[2]Op{OpAMD64MOVWstoreconst, OpAMD64LEAQ1}: OpAMD64MOVWstoreconstidx1,
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[2]Op{OpAMD64MOVWstoreconst, OpAMD64LEAQ2}: OpAMD64MOVWstoreconstidx2,
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[2]Op{OpAMD64MOVLstoreconst, OpAMD64LEAQ1}: OpAMD64MOVLstoreconstidx1,
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[2]Op{OpAMD64MOVLstoreconst, OpAMD64LEAQ4}: OpAMD64MOVLstoreconstidx4,
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[2]Op{OpAMD64MOVQstoreconst, OpAMD64LEAQ1}: OpAMD64MOVQstoreconstidx1,
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[2]Op{OpAMD64MOVQstoreconst, OpAMD64LEAQ8}: OpAMD64MOVQstoreconstidx8,
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// 386
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[2]Op{Op386MOVBload, Op386ADDL}: Op386MOVBloadidx1,
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[2]Op{Op386MOVWload, Op386ADDL}: Op386MOVWloadidx1,
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[2]Op{Op386MOVLload, Op386ADDL}: Op386MOVLloadidx1,
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[2]Op{Op386MOVSSload, Op386ADDL}: Op386MOVSSloadidx1,
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[2]Op{Op386MOVSDload, Op386ADDL}: Op386MOVSDloadidx1,
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[2]Op{Op386MOVBstore, Op386ADDL}: Op386MOVBstoreidx1,
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[2]Op{Op386MOVWstore, Op386ADDL}: Op386MOVWstoreidx1,
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[2]Op{Op386MOVLstore, Op386ADDL}: Op386MOVLstoreidx1,
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[2]Op{Op386MOVSSstore, Op386ADDL}: Op386MOVSSstoreidx1,
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[2]Op{Op386MOVSDstore, Op386ADDL}: Op386MOVSDstoreidx1,
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[2]Op{Op386MOVBstoreconst, Op386ADDL}: Op386MOVBstoreconstidx1,
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[2]Op{Op386MOVWstoreconst, Op386ADDL}: Op386MOVWstoreconstidx1,
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[2]Op{Op386MOVLstoreconst, Op386ADDL}: Op386MOVLstoreconstidx1,
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[2]Op{Op386MOVBload, Op386LEAL1}: Op386MOVBloadidx1,
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[2]Op{Op386MOVWload, Op386LEAL1}: Op386MOVWloadidx1,
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[2]Op{Op386MOVWload, Op386LEAL2}: Op386MOVWloadidx2,
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[2]Op{Op386MOVLload, Op386LEAL1}: Op386MOVLloadidx1,
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[2]Op{Op386MOVLload, Op386LEAL4}: Op386MOVLloadidx4,
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[2]Op{Op386MOVSSload, Op386LEAL1}: Op386MOVSSloadidx1,
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[2]Op{Op386MOVSSload, Op386LEAL4}: Op386MOVSSloadidx4,
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[2]Op{Op386MOVSDload, Op386LEAL1}: Op386MOVSDloadidx1,
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[2]Op{Op386MOVSDload, Op386LEAL8}: Op386MOVSDloadidx8,
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[2]Op{Op386MOVBstore, Op386LEAL1}: Op386MOVBstoreidx1,
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[2]Op{Op386MOVWstore, Op386LEAL1}: Op386MOVWstoreidx1,
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[2]Op{Op386MOVWstore, Op386LEAL2}: Op386MOVWstoreidx2,
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[2]Op{Op386MOVLstore, Op386LEAL1}: Op386MOVLstoreidx1,
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[2]Op{Op386MOVLstore, Op386LEAL4}: Op386MOVLstoreidx4,
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[2]Op{Op386MOVSSstore, Op386LEAL1}: Op386MOVSSstoreidx1,
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[2]Op{Op386MOVSSstore, Op386LEAL4}: Op386MOVSSstoreidx4,
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[2]Op{Op386MOVSDstore, Op386LEAL1}: Op386MOVSDstoreidx1,
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[2]Op{Op386MOVSDstore, Op386LEAL8}: Op386MOVSDstoreidx8,
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[2]Op{Op386MOVBstoreconst, Op386LEAL1}: Op386MOVBstoreconstidx1,
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[2]Op{Op386MOVWstoreconst, Op386LEAL1}: Op386MOVWstoreconstidx1,
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[2]Op{Op386MOVWstoreconst, Op386LEAL2}: Op386MOVWstoreconstidx2,
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[2]Op{Op386MOVLstoreconst, Op386LEAL1}: Op386MOVLstoreconstidx1,
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[2]Op{Op386MOVLstoreconst, Op386LEAL4}: Op386MOVLstoreconstidx4,
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[2]Op{Op386ADDLload, Op386LEAL4}: Op386ADDLloadidx4,
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[2]Op{Op386SUBLload, Op386LEAL4}: Op386SUBLloadidx4,
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[2]Op{Op386MULLload, Op386LEAL4}: Op386MULLloadidx4,
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[2]Op{Op386ANDLload, Op386LEAL4}: Op386ANDLloadidx4,
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[2]Op{Op386ORLload, Op386LEAL4}: Op386ORLloadidx4,
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[2]Op{Op386XORLload, Op386LEAL4}: Op386XORLloadidx4,
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[2]Op{Op386ADDLmodify, Op386LEAL4}: Op386ADDLmodifyidx4,
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[2]Op{Op386SUBLmodify, Op386LEAL4}: Op386SUBLmodifyidx4,
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[2]Op{Op386ANDLmodify, Op386LEAL4}: Op386ANDLmodifyidx4,
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[2]Op{Op386ORLmodify, Op386LEAL4}: Op386ORLmodifyidx4,
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[2]Op{Op386XORLmodify, Op386LEAL4}: Op386XORLmodifyidx4,
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[2]Op{Op386ADDLconstmodify, Op386LEAL4}: Op386ADDLconstmodifyidx4,
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[2]Op{Op386ANDLconstmodify, Op386LEAL4}: Op386ANDLconstmodifyidx4,
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[2]Op{Op386ORLconstmodify, Op386LEAL4}: Op386ORLconstmodifyidx4,
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[2]Op{Op386XORLconstmodify, Op386LEAL4}: Op386XORLconstmodifyidx4,
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}
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