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4c2b1e0feb
For #65355 Change-Id: I65dd090fb99de9b231af2112c5ccb0eb635db2be Reviewed-on: https://go-review.googlesource.com/c/go/+/560155 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Ibrahim Bazoka <ibrahimbazoka729@gmail.com> Auto-Submit: Emmanuel Odeke <emmanuel@orijtech.com>
135 lines
2.8 KiB
ArmAsm
135 lines
2.8 KiB
ArmAsm
// Copyright 2015 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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#include "textflag.h"
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// Linux/ARM atomic operations.
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// Because there is so much variation in ARM devices,
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// the Linux kernel provides an appropriate compare-and-swap
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// implementation at address 0xffff0fc0. Caller sets:
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// R0 = old value
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// R1 = new value
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// R2 = addr
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// LR = return address
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// The function returns with CS true if the swap happened.
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// http://lxr.linux.no/linux+v2.6.37.2/arch/arm/kernel/entry-armv.S#L850
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//
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// https://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=b49c0f24cf6744a3f4fd09289fe7cade349dead5
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//
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TEXT cas<>(SB),NOSPLIT,$0
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MOVW $0xffff0fc0, R15 // R15 is hardware PC.
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TEXT ·Cas(SB),NOSPLIT|NOFRAME,$0
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MOVB runtime·goarm(SB), R11
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CMP $7, R11
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BLT 2(PC)
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JMP ·armcas(SB)
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JMP kernelcas<>(SB)
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TEXT kernelcas<>(SB),NOSPLIT,$0
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MOVW ptr+0(FP), R2
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// trigger potential paging fault here,
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// because we don't know how to traceback through __kuser_cmpxchg
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MOVW (R2), R0
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MOVW old+4(FP), R0
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MOVW new+8(FP), R1
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BL cas<>(SB)
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BCC ret0
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MOVW $1, R0
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MOVB R0, ret+12(FP)
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RET
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ret0:
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MOVW $0, R0
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MOVB R0, ret+12(FP)
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RET
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// As for cas, memory barriers are complicated on ARM, but the kernel
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// provides a user helper. ARMv5 does not support SMP and has no
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// memory barrier instruction at all. ARMv6 added SMP support and has
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// a memory barrier, but it requires writing to a coprocessor
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// register. ARMv7 introduced the DMB instruction, but it's expensive
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// even on single-core devices. The kernel helper takes care of all of
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// this for us.
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// Use kernel helper version of memory_barrier, when compiled with GOARM < 7.
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TEXT memory_barrier<>(SB),NOSPLIT|NOFRAME,$0
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MOVW $0xffff0fa0, R15 // R15 is hardware PC.
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TEXT ·Load(SB),NOSPLIT,$0-8
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MOVW addr+0(FP), R0
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MOVW (R0), R1
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MOVB runtime·goarm(SB), R11
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CMP $7, R11
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BGE native_barrier
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BL memory_barrier<>(SB)
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B end
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native_barrier:
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DMB MB_ISH
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end:
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MOVW R1, ret+4(FP)
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RET
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TEXT ·Store(SB),NOSPLIT,$0-8
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MOVW addr+0(FP), R1
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MOVW v+4(FP), R2
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MOVB runtime·goarm(SB), R8
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CMP $7, R8
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BGE native_barrier
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BL memory_barrier<>(SB)
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B store
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native_barrier:
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DMB MB_ISH
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store:
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MOVW R2, (R1)
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CMP $7, R8
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BGE native_barrier2
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BL memory_barrier<>(SB)
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RET
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native_barrier2:
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DMB MB_ISH
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RET
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TEXT ·Load8(SB),NOSPLIT,$0-5
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MOVW addr+0(FP), R0
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MOVB (R0), R1
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MOVB runtime·goarm(SB), R11
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CMP $7, R11
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BGE native_barrier
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BL memory_barrier<>(SB)
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B end
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native_barrier:
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DMB MB_ISH
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end:
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MOVB R1, ret+4(FP)
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RET
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TEXT ·Store8(SB),NOSPLIT,$0-5
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MOVW addr+0(FP), R1
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MOVB v+4(FP), R2
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MOVB runtime·goarm(SB), R8
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CMP $7, R8
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BGE native_barrier
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BL memory_barrier<>(SB)
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B store
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native_barrier:
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DMB MB_ISH
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store:
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MOVB R2, (R1)
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CMP $7, R8
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BGE native_barrier2
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BL memory_barrier<>(SB)
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RET
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native_barrier2:
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DMB MB_ISH
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RET
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