mirror of
https://github.com/golang/go.git
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be1eb57a8b
Use width-and-signed-specific multiply opcodes. Implement OMUL. A few other cleanups. Fixes #11467 Change-Id: Ib0fe80a1a9b7208dbb8a2b6b652a478847f5d244 Reviewed-on: https://go-review.googlesource.com/12540 Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2826 lines
59 KiB
Go
2826 lines
59 KiB
Go
// autogenerated from gen/AMD64.rules: do not edit!
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// generated with: cd gen; go run *.go
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package ssa
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func rewriteValueAMD64(v *Value, config *Config) bool {
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switch v.Op {
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case OpAMD64ADDQ:
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// match: (ADDQ x (MOVQconst [c]))
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// cond:
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// result: (ADDQconst [c] x)
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{
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x := v.Args[0]
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if v.Args[1].Op != OpAMD64MOVQconst {
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goto endacffd55e74ee0ff59ad58a18ddfc9973
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}
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c := v.Args[1].AuxInt
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v.Op = OpAMD64ADDQconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
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}
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goto endacffd55e74ee0ff59ad58a18ddfc9973
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endacffd55e74ee0ff59ad58a18ddfc9973:
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;
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// match: (ADDQ (MOVQconst [c]) x)
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// cond:
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// result: (ADDQconst [c] x)
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{
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if v.Args[0].Op != OpAMD64MOVQconst {
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goto end7166f476d744ab7a51125959d3d3c7e2
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}
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c := v.Args[0].AuxInt
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x := v.Args[1]
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v.Op = OpAMD64ADDQconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
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}
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goto end7166f476d744ab7a51125959d3d3c7e2
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end7166f476d744ab7a51125959d3d3c7e2:
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;
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// match: (ADDQ x (SHLQconst [3] y))
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// cond:
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// result: (LEAQ8 x y)
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{
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x := v.Args[0]
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if v.Args[1].Op != OpAMD64SHLQconst {
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goto endc02313d35a0525d1d680cd58992e820d
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}
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if v.Args[1].AuxInt != 3 {
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goto endc02313d35a0525d1d680cd58992e820d
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}
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y := v.Args[1].Args[0]
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v.Op = OpAMD64LEAQ8
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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v.AddArg(y)
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return true
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}
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goto endc02313d35a0525d1d680cd58992e820d
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endc02313d35a0525d1d680cd58992e820d:
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;
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case OpAMD64ADDQconst:
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// match: (ADDQconst [c] (LEAQ8 [d] x y))
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// cond:
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// result: (LEAQ8 [addOff(c, d)] x y)
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{
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c := v.AuxInt
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if v.Args[0].Op != OpAMD64LEAQ8 {
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goto ende2cc681c9abf9913288803fb1b39e639
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}
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d := v.Args[0].AuxInt
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x := v.Args[0].Args[0]
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y := v.Args[0].Args[1]
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v.Op = OpAMD64LEAQ8
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = addOff(c, d)
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v.AddArg(x)
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v.AddArg(y)
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return true
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}
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goto ende2cc681c9abf9913288803fb1b39e639
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ende2cc681c9abf9913288803fb1b39e639:
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;
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// match: (ADDQconst [0] x)
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// cond:
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// result: (Copy x)
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{
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if v.AuxInt != 0 {
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goto end288952f259d4a1842f1e8d5c389b3f28
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}
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x := v.Args[0]
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v.Op = OpCopy
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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return true
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}
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goto end288952f259d4a1842f1e8d5c389b3f28
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end288952f259d4a1842f1e8d5c389b3f28:
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;
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case OpAMD64ANDQ:
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// match: (ANDQ x (MOVQconst [c]))
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// cond:
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// result: (ANDQconst [c] x)
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{
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x := v.Args[0]
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if v.Args[1].Op != OpAMD64MOVQconst {
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goto endb98096e3bbb90933e39c88bf41c688a9
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}
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c := v.Args[1].AuxInt
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v.Op = OpAMD64ANDQconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
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}
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goto endb98096e3bbb90933e39c88bf41c688a9
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endb98096e3bbb90933e39c88bf41c688a9:
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;
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// match: (ANDQ (MOVQconst [c]) x)
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// cond:
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// result: (ANDQconst [c] x)
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{
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if v.Args[0].Op != OpAMD64MOVQconst {
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goto endd313fd1897a0d2bc79eff70159a81b6b
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}
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c := v.Args[0].AuxInt
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x := v.Args[1]
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v.Op = OpAMD64ANDQconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
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}
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goto endd313fd1897a0d2bc79eff70159a81b6b
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endd313fd1897a0d2bc79eff70159a81b6b:
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;
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case OpAMD64ANDQconst:
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// match: (ANDQconst [0] _)
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// cond:
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// result: (MOVQconst [0])
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{
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if v.AuxInt != 0 {
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goto endf2afa4d9d31c344d6638dcdced383cf1
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}
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v.Op = OpAMD64MOVQconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = 0
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return true
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}
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goto endf2afa4d9d31c344d6638dcdced383cf1
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endf2afa4d9d31c344d6638dcdced383cf1:
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;
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// match: (ANDQconst [-1] x)
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// cond:
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// result: (Copy x)
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{
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if v.AuxInt != -1 {
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goto end646afc7b328db89ad16ebfa156ae26e5
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}
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x := v.Args[0]
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v.Op = OpCopy
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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return true
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}
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goto end646afc7b328db89ad16ebfa156ae26e5
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end646afc7b328db89ad16ebfa156ae26e5:
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;
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case OpAdd16:
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// match: (Add16 x y)
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// cond:
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// result: (MOVWQSX (ADDW <v.Type> x y))
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{
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x := v.Args[0]
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y := v.Args[1]
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v.Op = OpAMD64MOVWQSX
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v0 := v.Block.NewValue0(v.Line, OpAMD64ADDW, TypeInvalid)
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v0.Type = v.Type
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v0.AddArg(x)
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v0.AddArg(y)
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v.AddArg(v0)
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return true
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}
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goto end2aef2dab49f6b2ca337f58ad0a8209ae
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end2aef2dab49f6b2ca337f58ad0a8209ae:
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;
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case OpAdd16U:
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// match: (Add16U x y)
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// cond:
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// result: (ADDW x y)
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{
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x := v.Args[0]
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y := v.Args[1]
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v.Op = OpAMD64ADDW
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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v.AddArg(y)
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return true
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}
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goto end8ca34beeb0897b0c70352ba90cca4a1d
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end8ca34beeb0897b0c70352ba90cca4a1d:
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;
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case OpAdd32:
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// match: (Add32 x y)
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// cond:
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// result: (MOVLQSX (ADDL <v.Type> x y))
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{
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x := v.Args[0]
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y := v.Args[1]
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v.Op = OpAMD64MOVLQSX
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v0 := v.Block.NewValue0(v.Line, OpAMD64ADDL, TypeInvalid)
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v0.Type = v.Type
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v0.AddArg(x)
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v0.AddArg(y)
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v.AddArg(v0)
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return true
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}
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goto end7f18bca004d8c158f50b04e7511af49f
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end7f18bca004d8c158f50b04e7511af49f:
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;
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case OpAdd32U:
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// match: (Add32U x y)
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// cond:
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// result: (ADDL x y)
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{
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x := v.Args[0]
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y := v.Args[1]
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v.Op = OpAMD64ADDL
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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v.AddArg(y)
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return true
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}
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goto end72ff71aa883fa569307ae06289ac1e30
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end72ff71aa883fa569307ae06289ac1e30:
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;
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case OpAdd64:
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// match: (Add64 x y)
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// cond:
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// result: (ADDQ x y)
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{
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x := v.Args[0]
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y := v.Args[1]
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v.Op = OpAMD64ADDQ
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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v.AddArg(y)
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return true
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}
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goto endd88f18b3f39e3ccc201477a616f0abc0
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endd88f18b3f39e3ccc201477a616f0abc0:
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;
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case OpAdd64U:
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// match: (Add64U x y)
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// cond:
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// result: (ADDQ x y)
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{
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x := v.Args[0]
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y := v.Args[1]
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v.Op = OpAMD64ADDQ
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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v.AddArg(y)
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return true
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}
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goto endee28cc0dbdf2664cb3f6a5ddb3960b1b
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endee28cc0dbdf2664cb3f6a5ddb3960b1b:
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;
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case OpAdd8:
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// match: (Add8 x y)
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// cond:
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// result: (MOVBQSX (ADDB <v.Type> x y))
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{
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x := v.Args[0]
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y := v.Args[1]
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v.Op = OpAMD64MOVBQSX
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v0 := v.Block.NewValue0(v.Line, OpAMD64ADDB, TypeInvalid)
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v0.Type = v.Type
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v0.AddArg(x)
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v0.AddArg(y)
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v.AddArg(v0)
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return true
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}
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goto end7078e2b21b2da3acc80e79ba1386d098
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end7078e2b21b2da3acc80e79ba1386d098:
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;
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case OpAdd8U:
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// match: (Add8U x y)
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// cond:
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// result: (ADDB x y)
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{
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x := v.Args[0]
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y := v.Args[1]
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v.Op = OpAMD64ADDB
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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v.AddArg(y)
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return true
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}
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goto endb5cb0e4b3566464c17acf1df5e4b0543
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endb5cb0e4b3566464c17acf1df5e4b0543:
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;
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case OpAddPtr:
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// match: (AddPtr x y)
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// cond:
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// result: (ADDQ x y)
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{
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x := v.Args[0]
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y := v.Args[1]
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v.Op = OpAMD64ADDQ
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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v.AddArg(y)
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return true
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}
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goto enda1d5640788c7157996f9d4af602dec1c
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enda1d5640788c7157996f9d4af602dec1c:
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;
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case OpAddr:
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// match: (Addr {sym} base)
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// cond:
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// result: (LEAQ {sym} base)
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{
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sym := v.Aux
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base := v.Args[0]
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v.Op = OpAMD64LEAQ
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v.AuxInt = 0
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v.Aux = nil
|
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v.resetArgs()
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v.Aux = sym
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v.AddArg(base)
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return true
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}
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goto end53cad0c3c9daa5575680e77c14e05e72
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end53cad0c3c9daa5575680e77c14e05e72:
|
|
;
|
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case OpAMD64CMOVQCC:
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// match: (CMOVQCC (CMPQconst [c] (MOVQconst [d])) _ x)
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// cond: inBounds(d, c)
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// result: (Copy x)
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|
{
|
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if v.Args[0].Op != OpAMD64CMPQconst {
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goto endd5357f3fd5516dcc859c8c5b3c9efaa4
|
|
}
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c := v.Args[0].AuxInt
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if v.Args[0].Args[0].Op != OpAMD64MOVQconst {
|
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goto endd5357f3fd5516dcc859c8c5b3c9efaa4
|
|
}
|
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d := v.Args[0].Args[0].AuxInt
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x := v.Args[2]
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if !(inBounds(d, c)) {
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goto endd5357f3fd5516dcc859c8c5b3c9efaa4
|
|
}
|
|
v.Op = OpCopy
|
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v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
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goto endd5357f3fd5516dcc859c8c5b3c9efaa4
|
|
endd5357f3fd5516dcc859c8c5b3c9efaa4:
|
|
;
|
|
// match: (CMOVQCC (CMPQconst [c] (MOVQconst [d])) x _)
|
|
// cond: !inBounds(d, c)
|
|
// result: (Copy x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPQconst {
|
|
goto end6ad8b1758415a9afe758272b34970d5d
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVQconst {
|
|
goto end6ad8b1758415a9afe758272b34970d5d
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
x := v.Args[1]
|
|
if !(!inBounds(d, c)) {
|
|
goto end6ad8b1758415a9afe758272b34970d5d
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end6ad8b1758415a9afe758272b34970d5d
|
|
end6ad8b1758415a9afe758272b34970d5d:
|
|
;
|
|
case OpAMD64CMPQ:
|
|
// match: (CMPQ x (MOVQconst [c]))
|
|
// cond:
|
|
// result: (CMPQconst x [c])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end32ef1328af280ac18fa8045a3502dae9
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64CMPQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AuxInt = c
|
|
return true
|
|
}
|
|
goto end32ef1328af280ac18fa8045a3502dae9
|
|
end32ef1328af280ac18fa8045a3502dae9:
|
|
;
|
|
// match: (CMPQ (MOVQconst [c]) x)
|
|
// cond:
|
|
// result: (InvertFlags (CMPQconst <TypeFlags> x [c]))
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto endf8ca12fe79290bc82b11cfa463bc9413
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64InvertFlags
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AuxInt = c
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endf8ca12fe79290bc82b11cfa463bc9413
|
|
endf8ca12fe79290bc82b11cfa463bc9413:
|
|
;
|
|
case OpClosureCall:
|
|
// match: (ClosureCall [argwid] entry closure mem)
|
|
// cond:
|
|
// result: (CALLclosure [argwid] entry closure mem)
|
|
{
|
|
argwid := v.AuxInt
|
|
entry := v.Args[0]
|
|
closure := v.Args[1]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64CALLclosure
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = argwid
|
|
v.AddArg(entry)
|
|
v.AddArg(closure)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endfd75d26316012d86cb71d0dd1214259b
|
|
endfd75d26316012d86cb71d0dd1214259b:
|
|
;
|
|
case OpConst:
|
|
// match: (Const <t> [val])
|
|
// cond: t.IsInteger()
|
|
// result: (MOVQconst [val])
|
|
{
|
|
t := v.Type
|
|
val := v.AuxInt
|
|
if !(t.IsInteger()) {
|
|
goto end4c8bfe9df26fc5aa2bd76b211792732a
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = val
|
|
return true
|
|
}
|
|
goto end4c8bfe9df26fc5aa2bd76b211792732a
|
|
end4c8bfe9df26fc5aa2bd76b211792732a:
|
|
;
|
|
// match: (Const <t>)
|
|
// cond: t.IsPtr()
|
|
// result: (MOVQconst [0])
|
|
{
|
|
t := v.Type
|
|
if !(t.IsPtr()) {
|
|
goto endd23abe8d7061f11c260b162e24eec060
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto endd23abe8d7061f11c260b162e24eec060
|
|
endd23abe8d7061f11c260b162e24eec060:
|
|
;
|
|
// match: (Const <t>)
|
|
// cond: t.IsBoolean() && !v.Aux.(bool)
|
|
// result: (MOVQconst [0])
|
|
{
|
|
t := v.Type
|
|
if !(t.IsBoolean() && !v.Aux.(bool)) {
|
|
goto end7b1347fd0902b990ee1e49145c7e8c31
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end7b1347fd0902b990ee1e49145c7e8c31
|
|
end7b1347fd0902b990ee1e49145c7e8c31:
|
|
;
|
|
// match: (Const <t>)
|
|
// cond: t.IsBoolean() && v.Aux.(bool)
|
|
// result: (MOVQconst [1])
|
|
{
|
|
t := v.Type
|
|
if !(t.IsBoolean() && v.Aux.(bool)) {
|
|
goto ende0d1c954b5ab5af7227bff9635774f1c
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 1
|
|
return true
|
|
}
|
|
goto ende0d1c954b5ab5af7227bff9635774f1c
|
|
ende0d1c954b5ab5af7227bff9635774f1c:
|
|
;
|
|
case OpConvNop:
|
|
// match: (ConvNop <t> x)
|
|
// cond: t == x.Type
|
|
// result: (Copy x)
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
if !(t == x.Type) {
|
|
goto end6c588ed8aedc7dca8c06b4ada77e3ddd
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end6c588ed8aedc7dca8c06b4ada77e3ddd
|
|
end6c588ed8aedc7dca8c06b4ada77e3ddd:
|
|
;
|
|
case OpConvert:
|
|
// match: (Convert <t> x)
|
|
// cond: t.IsInteger() && x.Type.IsInteger()
|
|
// result: (Copy x)
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
if !(t.IsInteger() && x.Type.IsInteger()) {
|
|
goto endcc7894224d4f6b0bcabcece5d0185912
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endcc7894224d4f6b0bcabcece5d0185912
|
|
endcc7894224d4f6b0bcabcece5d0185912:
|
|
;
|
|
case OpEq64:
|
|
// match: (Eq64 x y)
|
|
// cond:
|
|
// result: (SETEQ (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETEQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endae6c62e4e20b4f62694b6ee40dbd9211
|
|
endae6c62e4e20b4f62694b6ee40dbd9211:
|
|
;
|
|
case OpGeq64:
|
|
// match: (Geq64 x y)
|
|
// cond:
|
|
// result: (SETGE (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETGE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end63f44e3fec8d92723b5bde42d6d7eea0
|
|
end63f44e3fec8d92723b5bde42d6d7eea0:
|
|
;
|
|
case OpGreater64:
|
|
// match: (Greater64 x y)
|
|
// cond:
|
|
// result: (SETG (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETG
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endaef0cfa5e27e23cf5e527061cf251069
|
|
endaef0cfa5e27e23cf5e527061cf251069:
|
|
;
|
|
case OpIsInBounds:
|
|
// match: (IsInBounds idx len)
|
|
// cond:
|
|
// result: (SETB (CMPQ <TypeFlags> idx len))
|
|
{
|
|
idx := v.Args[0]
|
|
len := v.Args[1]
|
|
v.Op = OpAMD64SETB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(idx)
|
|
v0.AddArg(len)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endb51d371171154c0f1613b687757e0576
|
|
endb51d371171154c0f1613b687757e0576:
|
|
;
|
|
case OpIsNonNil:
|
|
// match: (IsNonNil p)
|
|
// cond:
|
|
// result: (SETNE (TESTQ <TypeFlags> p p))
|
|
{
|
|
p := v.Args[0]
|
|
v.Op = OpAMD64SETNE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64TESTQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(p)
|
|
v0.AddArg(p)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endff508c3726edfb573abc6128c177e76c
|
|
endff508c3726edfb573abc6128c177e76c:
|
|
;
|
|
case OpLeq64:
|
|
// match: (Leq64 x y)
|
|
// cond:
|
|
// result: (SETLE (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETLE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endf03da5e28dccdb4797671f39e824fb10
|
|
endf03da5e28dccdb4797671f39e824fb10:
|
|
;
|
|
case OpLess64:
|
|
// match: (Less64 x y)
|
|
// cond:
|
|
// result: (SETL (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endf8e7a24c25692045bbcfd2c9356d1a8c
|
|
endf8e7a24c25692045bbcfd2c9356d1a8c:
|
|
;
|
|
case OpLoad:
|
|
// match: (Load <t> ptr mem)
|
|
// cond: (is64BitInt(t) || isPtr(t))
|
|
// result: (MOVQload ptr mem)
|
|
{
|
|
t := v.Type
|
|
ptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(is64BitInt(t) || isPtr(t)) {
|
|
goto end7c4c53acf57ebc5f03273652ba1d5934
|
|
}
|
|
v.Op = OpAMD64MOVQload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end7c4c53acf57ebc5f03273652ba1d5934
|
|
end7c4c53acf57ebc5f03273652ba1d5934:
|
|
;
|
|
// match: (Load <t> ptr mem)
|
|
// cond: is32BitInt(t)
|
|
// result: (MOVLload ptr mem)
|
|
{
|
|
t := v.Type
|
|
ptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(is32BitInt(t)) {
|
|
goto ende1cfcb15bfbcfd448ce303d0882a4057
|
|
}
|
|
v.Op = OpAMD64MOVLload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto ende1cfcb15bfbcfd448ce303d0882a4057
|
|
ende1cfcb15bfbcfd448ce303d0882a4057:
|
|
;
|
|
// match: (Load <t> ptr mem)
|
|
// cond: is16BitInt(t)
|
|
// result: (MOVWload ptr mem)
|
|
{
|
|
t := v.Type
|
|
ptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(is16BitInt(t)) {
|
|
goto end2d0a1304501ed9f4e9e2d288505a9c7c
|
|
}
|
|
v.Op = OpAMD64MOVWload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end2d0a1304501ed9f4e9e2d288505a9c7c
|
|
end2d0a1304501ed9f4e9e2d288505a9c7c:
|
|
;
|
|
// match: (Load <t> ptr mem)
|
|
// cond: (t.IsBoolean() || is8BitInt(t))
|
|
// result: (MOVBload ptr mem)
|
|
{
|
|
t := v.Type
|
|
ptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(t.IsBoolean() || is8BitInt(t)) {
|
|
goto end8f83bf72293670e75b22d6627bd13f0b
|
|
}
|
|
v.Op = OpAMD64MOVBload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end8f83bf72293670e75b22d6627bd13f0b
|
|
end8f83bf72293670e75b22d6627bd13f0b:
|
|
;
|
|
case OpLsh64:
|
|
// match: (Lsh64 <t> x y)
|
|
// cond:
|
|
// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPQconst <TypeFlags> [64] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64SHLQ, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := v.Block.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := v.Block.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 64
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end02b17b9d1aca859d392e527fe6fc58da
|
|
end02b17b9d1aca859d392e527fe6fc58da:
|
|
;
|
|
case OpAMD64MOVBstore:
|
|
// match: (MOVBstore ptr (MOVBQSX x) mem)
|
|
// cond:
|
|
// result: (MOVBstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBQSX {
|
|
goto endc356ef104095b9217b36b594f85171c6
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVBstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endc356ef104095b9217b36b594f85171c6
|
|
endc356ef104095b9217b36b594f85171c6:
|
|
;
|
|
// match: (MOVBstore ptr (MOVBQZX x) mem)
|
|
// cond:
|
|
// result: (MOVBstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBQZX {
|
|
goto end25841a70cce7ac32c6d5e561b992d3df
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVBstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end25841a70cce7ac32c6d5e561b992d3df
|
|
end25841a70cce7ac32c6d5e561b992d3df:
|
|
;
|
|
case OpAMD64MOVLstore:
|
|
// match: (MOVLstore ptr (MOVLQSX x) mem)
|
|
// cond:
|
|
// result: (MOVLstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLQSX {
|
|
goto endf79c699f70cb356abb52dc28f4abf46b
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVLstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endf79c699f70cb356abb52dc28f4abf46b
|
|
endf79c699f70cb356abb52dc28f4abf46b:
|
|
;
|
|
// match: (MOVLstore ptr (MOVLQZX x) mem)
|
|
// cond:
|
|
// result: (MOVLstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLQZX {
|
|
goto end67d1549d16d373e4ad6a89298866d1bc
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVLstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end67d1549d16d373e4ad6a89298866d1bc
|
|
end67d1549d16d373e4ad6a89298866d1bc:
|
|
;
|
|
case OpAMD64MOVQload:
|
|
// match: (MOVQload [off1] (ADDQconst [off2] ptr) mem)
|
|
// cond:
|
|
// result: (MOVQload [addOff(off1, off2)] ptr mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
|
goto end843d29b538c4483b432b632e5666d6e3
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVQload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end843d29b538c4483b432b632e5666d6e3
|
|
end843d29b538c4483b432b632e5666d6e3:
|
|
;
|
|
// match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
|
|
// cond: (sym1 == nil || sym2 == nil)
|
|
// result: (MOVQload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
sym1 := v.Aux
|
|
if v.Args[0].Op != OpAMD64LEAQ {
|
|
goto end227426af95e74caddcf59fdcd30ca8bc
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
sym2 := v.Args[0].Aux
|
|
base := v.Args[0].Args[0]
|
|
mem := v.Args[1]
|
|
if !(sym1 == nil || sym2 == nil) {
|
|
goto end227426af95e74caddcf59fdcd30ca8bc
|
|
}
|
|
v.Op = OpAMD64MOVQload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.Aux = mergeSym(sym1, sym2)
|
|
v.AddArg(base)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end227426af95e74caddcf59fdcd30ca8bc
|
|
end227426af95e74caddcf59fdcd30ca8bc:
|
|
;
|
|
// match: (MOVQload [off1] (LEAQ8 [off2] ptr idx) mem)
|
|
// cond:
|
|
// result: (MOVQloadidx8 [addOff(off1, off2)] ptr idx mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64LEAQ8 {
|
|
goto end02f5ad148292c46463e7c20d3b821735
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
idx := v.Args[0].Args[1]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVQloadidx8
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(idx)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end02f5ad148292c46463e7c20d3b821735
|
|
end02f5ad148292c46463e7c20d3b821735:
|
|
;
|
|
case OpAMD64MOVQloadidx8:
|
|
// match: (MOVQloadidx8 [off1] (ADDQconst [off2] ptr) idx mem)
|
|
// cond:
|
|
// result: (MOVQloadidx8 [addOff(off1, off2)] ptr idx mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
|
goto ende81e44bcfb11f90916ccb440c590121f
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
idx := v.Args[1]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVQloadidx8
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(idx)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto ende81e44bcfb11f90916ccb440c590121f
|
|
ende81e44bcfb11f90916ccb440c590121f:
|
|
;
|
|
case OpAMD64MOVQstore:
|
|
// match: (MOVQstore [off1] (ADDQconst [off2] ptr) val mem)
|
|
// cond:
|
|
// result: (MOVQstore [addOff(off1, off2)] ptr val mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
|
goto end2108c693a43c79aed10b9246c39c80aa
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVQstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end2108c693a43c79aed10b9246c39c80aa
|
|
end2108c693a43c79aed10b9246c39c80aa:
|
|
;
|
|
// match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
|
|
// cond: (sym1 == nil || sym2 == nil)
|
|
// result: (MOVQstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
sym1 := v.Aux
|
|
if v.Args[0].Op != OpAMD64LEAQ {
|
|
goto end5061f48193268a5eb1e1740bdd23c43d
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
sym2 := v.Args[0].Aux
|
|
base := v.Args[0].Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(sym1 == nil || sym2 == nil) {
|
|
goto end5061f48193268a5eb1e1740bdd23c43d
|
|
}
|
|
v.Op = OpAMD64MOVQstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.Aux = mergeSym(sym1, sym2)
|
|
v.AddArg(base)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end5061f48193268a5eb1e1740bdd23c43d
|
|
end5061f48193268a5eb1e1740bdd23c43d:
|
|
;
|
|
// match: (MOVQstore [off1] (LEAQ8 [off2] ptr idx) val mem)
|
|
// cond:
|
|
// result: (MOVQstoreidx8 [addOff(off1, off2)] ptr idx val mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64LEAQ8 {
|
|
goto endce1db8c8d37c8397c500a2068a65c215
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
idx := v.Args[0].Args[1]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVQstoreidx8
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(idx)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endce1db8c8d37c8397c500a2068a65c215
|
|
endce1db8c8d37c8397c500a2068a65c215:
|
|
;
|
|
case OpAMD64MOVQstoreidx8:
|
|
// match: (MOVQstoreidx8 [off1] (ADDQconst [off2] ptr) idx val mem)
|
|
// cond:
|
|
// result: (MOVQstoreidx8 [addOff(off1, off2)] ptr idx val mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
|
goto end01c970657b0fdefeab82458c15022163
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
idx := v.Args[1]
|
|
val := v.Args[2]
|
|
mem := v.Args[3]
|
|
v.Op = OpAMD64MOVQstoreidx8
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(idx)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end01c970657b0fdefeab82458c15022163
|
|
end01c970657b0fdefeab82458c15022163:
|
|
;
|
|
case OpAMD64MOVWstore:
|
|
// match: (MOVWstore ptr (MOVWQSX x) mem)
|
|
// cond:
|
|
// result: (MOVWstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWQSX {
|
|
goto endcc13af07a951a61fcfec3299342f7e1f
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVWstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endcc13af07a951a61fcfec3299342f7e1f
|
|
endcc13af07a951a61fcfec3299342f7e1f:
|
|
;
|
|
// match: (MOVWstore ptr (MOVWQZX x) mem)
|
|
// cond:
|
|
// result: (MOVWstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWQZX {
|
|
goto end4e7df15ee55bdd73d8ecd61b759134d4
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVWstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end4e7df15ee55bdd73d8ecd61b759134d4
|
|
end4e7df15ee55bdd73d8ecd61b759134d4:
|
|
;
|
|
case OpAMD64MULQ:
|
|
// match: (MULQ x (MOVQconst [c]))
|
|
// cond: c == int64(int32(c))
|
|
// result: (MULQconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end680a32a37babfff4bfa7d23be592a131
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
if !(c == int64(int32(c))) {
|
|
goto end680a32a37babfff4bfa7d23be592a131
|
|
}
|
|
v.Op = OpAMD64MULQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end680a32a37babfff4bfa7d23be592a131
|
|
end680a32a37babfff4bfa7d23be592a131:
|
|
;
|
|
// match: (MULQ (MOVQconst [c]) x)
|
|
// cond:
|
|
// result: (MULQconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto endc6e18d6968175d6e58eafa6dcf40c1b8
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64MULQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endc6e18d6968175d6e58eafa6dcf40c1b8
|
|
endc6e18d6968175d6e58eafa6dcf40c1b8:
|
|
;
|
|
case OpAMD64MULQconst:
|
|
// match: (MULQconst [-1] x)
|
|
// cond:
|
|
// result: (NEGQ x)
|
|
{
|
|
if v.AuxInt != -1 {
|
|
goto end82501cca6b5fb121a7f8b197e55f2fec
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NEGQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end82501cca6b5fb121a7f8b197e55f2fec
|
|
end82501cca6b5fb121a7f8b197e55f2fec:
|
|
;
|
|
// match: (MULQconst [0] _)
|
|
// cond:
|
|
// result: (MOVQconst [0])
|
|
{
|
|
if v.AuxInt != 0 {
|
|
goto endcb9faa068e3558ff44daaf1d47d091b5
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto endcb9faa068e3558ff44daaf1d47d091b5
|
|
endcb9faa068e3558ff44daaf1d47d091b5:
|
|
;
|
|
// match: (MULQconst [1] x)
|
|
// cond:
|
|
// result: (Copy x)
|
|
{
|
|
if v.AuxInt != 1 {
|
|
goto endd7217a7c6311fc7a3e0736a1b0b5be73
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endd7217a7c6311fc7a3e0736a1b0b5be73
|
|
endd7217a7c6311fc7a3e0736a1b0b5be73:
|
|
;
|
|
// match: (MULQconst [3] x)
|
|
// cond:
|
|
// result: (LEAQ2 x x)
|
|
{
|
|
if v.AuxInt != 3 {
|
|
goto end34a86f261671b5852bec6c57155fe0da
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64LEAQ2
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end34a86f261671b5852bec6c57155fe0da
|
|
end34a86f261671b5852bec6c57155fe0da:
|
|
;
|
|
// match: (MULQconst [5] x)
|
|
// cond:
|
|
// result: (LEAQ4 x x)
|
|
{
|
|
if v.AuxInt != 5 {
|
|
goto end534601906c45a9171a9fec3e4b82b189
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64LEAQ4
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end534601906c45a9171a9fec3e4b82b189
|
|
end534601906c45a9171a9fec3e4b82b189:
|
|
;
|
|
// match: (MULQconst [9] x)
|
|
// cond:
|
|
// result: (LEAQ8 x x)
|
|
{
|
|
if v.AuxInt != 9 {
|
|
goto end48a2280b6459821289c56073b8354997
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64LEAQ8
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end48a2280b6459821289c56073b8354997
|
|
end48a2280b6459821289c56073b8354997:
|
|
;
|
|
// match: (MULQconst [c] x)
|
|
// cond: isPowerOfTwo(c)
|
|
// result: (SHLQconst [log2(c)] x)
|
|
{
|
|
c := v.AuxInt
|
|
x := v.Args[0]
|
|
if !(isPowerOfTwo(c)) {
|
|
goto end75076953dbfe022526a153eda99b39b2
|
|
}
|
|
v.Op = OpAMD64SHLQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = log2(c)
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end75076953dbfe022526a153eda99b39b2
|
|
end75076953dbfe022526a153eda99b39b2:
|
|
;
|
|
case OpMove:
|
|
// match: (Move [size] dst src mem)
|
|
// cond:
|
|
// result: (REPMOVSB dst src (Const <TypeUInt64> [size]) mem)
|
|
{
|
|
size := v.AuxInt
|
|
dst := v.Args[0]
|
|
src := v.Args[1]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64REPMOVSB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(dst)
|
|
v.AddArg(src)
|
|
v0 := v.Block.NewValue0(v.Line, OpConst, TypeInvalid)
|
|
v0.Type = TypeUInt64
|
|
v0.AuxInt = size
|
|
v.AddArg(v0)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end1b2d226705fd31dbbe74e3286af178ea
|
|
end1b2d226705fd31dbbe74e3286af178ea:
|
|
;
|
|
case OpMul16:
|
|
// match: (Mul16 x y)
|
|
// cond:
|
|
// result: (MOVWQSX (MULW <v.Type> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MOVWQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64MULW, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end395fc5128ed3789326d04b4555ecfd16
|
|
end395fc5128ed3789326d04b4555ecfd16:
|
|
;
|
|
case OpMul16U:
|
|
// match: (Mul16U x y)
|
|
// cond:
|
|
// result: (MULW x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MULW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto endec860875a3c61ac3738fa330a3857bb3
|
|
endec860875a3c61ac3738fa330a3857bb3:
|
|
;
|
|
case OpMul32:
|
|
// match: (Mul32 x y)
|
|
// cond:
|
|
// result: (MOVLQSX (MULL <v.Type> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MOVLQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64MULL, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endb756489a642e438ff6e89e55754334e2
|
|
endb756489a642e438ff6e89e55754334e2:
|
|
;
|
|
case OpMul32U:
|
|
// match: (Mul32U x y)
|
|
// cond:
|
|
// result: (MULL x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MULL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto ende4c566176fb13075292de5ccb016c5fc
|
|
ende4c566176fb13075292de5ccb016c5fc:
|
|
;
|
|
case OpMul64:
|
|
// match: (Mul64 x y)
|
|
// cond:
|
|
// result: (MULQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MULQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end38da21e77ac329eb643b20e7d97d5853
|
|
end38da21e77ac329eb643b20e7d97d5853:
|
|
;
|
|
case OpMul64U:
|
|
// match: (Mul64U x y)
|
|
// cond:
|
|
// result: (MULQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MULQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end3da28ba90850e15f0ed2c37fbce90650
|
|
end3da28ba90850e15f0ed2c37fbce90650:
|
|
;
|
|
case OpMul8:
|
|
// match: (Mul8 x y)
|
|
// cond:
|
|
// result: (MOVBQSX (MULW <TypeInt16> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MOVBQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64MULW, TypeInvalid)
|
|
v0.Type = TypeInt16
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end418ba69107bb1e02d5015c73c9f9a5c9
|
|
end418ba69107bb1e02d5015c73c9f9a5c9:
|
|
;
|
|
case OpMul8U:
|
|
// match: (Mul8U x y)
|
|
// cond:
|
|
// result: (MOVBQZX (MULW <TypeUInt16> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MOVBQZX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64MULW, TypeInvalid)
|
|
v0.Type = TypeUInt16
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end9d0a972d9b8a32b84ed38a32bfeb01b6
|
|
end9d0a972d9b8a32b84ed38a32bfeb01b6:
|
|
;
|
|
case OpMulPtr:
|
|
// match: (MulPtr x y)
|
|
// cond:
|
|
// result: (MULQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MULQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto endbbedad106c011a93243e2062afdcc75f
|
|
endbbedad106c011a93243e2062afdcc75f:
|
|
;
|
|
case OpNeg16:
|
|
// match: (Neg16 x)
|
|
// cond:
|
|
// result: (MOVWQSX (NEGW <v.Type> x))
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVWQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64NEGW, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end089988d857b555c3065177bcad1eface
|
|
end089988d857b555c3065177bcad1eface:
|
|
;
|
|
case OpNeg16U:
|
|
// match: (Neg16U x)
|
|
// cond:
|
|
// result: (NEGW x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NEGW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end8f43be5b376227e92d70b382bded232b
|
|
end8f43be5b376227e92d70b382bded232b:
|
|
;
|
|
case OpNeg32:
|
|
// match: (Neg32 x)
|
|
// cond:
|
|
// result: (MOVLQSX (NEGL <v.Type> x))
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVLQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64NEGL, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end2217d3f168126b2ee157cb33befba76d
|
|
end2217d3f168126b2ee157cb33befba76d:
|
|
;
|
|
case OpNeg32U:
|
|
// match: (Neg32U x)
|
|
// cond:
|
|
// result: (NEGL x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NEGL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end1fe0112076c436ffceabac066776cd18
|
|
end1fe0112076c436ffceabac066776cd18:
|
|
;
|
|
case OpNeg64:
|
|
// match: (Neg64 x)
|
|
// cond:
|
|
// result: (NEGQ x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NEGQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enda06c5b1718f2b96aba10bf5a5c437c6c
|
|
enda06c5b1718f2b96aba10bf5a5c437c6c:
|
|
;
|
|
case OpNeg64U:
|
|
// match: (Neg64U x)
|
|
// cond:
|
|
// result: (NEGQ x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NEGQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endbc6beca972ff7f28273a1cdd146e3959
|
|
endbc6beca972ff7f28273a1cdd146e3959:
|
|
;
|
|
case OpNeg8:
|
|
// match: (Neg8 x)
|
|
// cond:
|
|
// result: (MOVBQSX (NEGB <v.Type> x))
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVBQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64NEGB, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end9cfacf0b7d826b85041092625ed494c1
|
|
end9cfacf0b7d826b85041092625ed494c1:
|
|
;
|
|
case OpNeg8U:
|
|
// match: (Neg8U x)
|
|
// cond:
|
|
// result: (NEGB x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NEGB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enda1ffb93a68702148c5fd18e2b72964d0
|
|
enda1ffb93a68702148c5fd18e2b72964d0:
|
|
;
|
|
case OpNeq64:
|
|
// match: (Neq64 x y)
|
|
// cond:
|
|
// result: (SETNE (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETNE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end8ab0bcb910c0d3213dd8726fbcc4848e
|
|
end8ab0bcb910c0d3213dd8726fbcc4848e:
|
|
;
|
|
case OpNot:
|
|
// match: (Not x)
|
|
// cond:
|
|
// result: (XORQconst [1] x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64XORQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 1
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endaabd7f5e27417cf3182cd5e4f4360410
|
|
endaabd7f5e27417cf3182cd5e4f4360410:
|
|
;
|
|
case OpOffPtr:
|
|
// match: (OffPtr [off] ptr)
|
|
// cond:
|
|
// result: (ADDQconst [off] ptr)
|
|
{
|
|
off := v.AuxInt
|
|
ptr := v.Args[0]
|
|
v.Op = OpAMD64ADDQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = off
|
|
v.AddArg(ptr)
|
|
return true
|
|
}
|
|
goto end0429f947ee7ac49ff45a243e461a5290
|
|
end0429f947ee7ac49ff45a243e461a5290:
|
|
;
|
|
case OpRsh64:
|
|
// match: (Rsh64 <t> x y)
|
|
// cond:
|
|
// result: (SARQ <t> x (CMOVQCC <t> (CMPQconst <TypeFlags> [64] y) (Const <t> [63]) y))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64CMOVQCC, TypeInvalid)
|
|
v0.Type = t
|
|
v1 := v.Block.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v1.Type = TypeFlags
|
|
v1.AuxInt = 64
|
|
v1.AddArg(y)
|
|
v0.AddArg(v1)
|
|
v2 := v.Block.NewValue0(v.Line, OpConst, TypeInvalid)
|
|
v2.Type = t
|
|
v2.AuxInt = 63
|
|
v0.AddArg(v2)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end831ac9db492245c5e6c83d0b2a96b2d3
|
|
end831ac9db492245c5e6c83d0b2a96b2d3:
|
|
;
|
|
case OpRsh64U:
|
|
// match: (Rsh64U <t> x y)
|
|
// cond:
|
|
// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPQconst <TypeFlags> [64] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64SHRQ, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := v.Block.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := v.Block.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 64
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end90c34fa7de598170ea23d23d9a03ebfc
|
|
end90c34fa7de598170ea23d23d9a03ebfc:
|
|
;
|
|
case OpAMD64SARQ:
|
|
// match: (SARQ x (MOVQconst [c]))
|
|
// cond:
|
|
// result: (SARQconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end031712b4008075e25a5827dcb8dd3ebb
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SARQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end031712b4008075e25a5827dcb8dd3ebb
|
|
end031712b4008075e25a5827dcb8dd3ebb:
|
|
;
|
|
case OpAMD64SBBQcarrymask:
|
|
// match: (SBBQcarrymask (CMPQconst [c] (MOVQconst [d])))
|
|
// cond: inBounds(d, c)
|
|
// result: (Const [-1])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPQconst {
|
|
goto endf67d323ecef000dbcd15d7e031c3475e
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVQconst {
|
|
goto endf67d323ecef000dbcd15d7e031c3475e
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(inBounds(d, c)) {
|
|
goto endf67d323ecef000dbcd15d7e031c3475e
|
|
}
|
|
v.Op = OpConst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto endf67d323ecef000dbcd15d7e031c3475e
|
|
endf67d323ecef000dbcd15d7e031c3475e:
|
|
;
|
|
// match: (SBBQcarrymask (CMPQconst [c] (MOVQconst [d])))
|
|
// cond: !inBounds(d, c)
|
|
// result: (Const [0])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPQconst {
|
|
goto end4157ddea9c4f71bfabfd6fa50e1208ed
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVQconst {
|
|
goto end4157ddea9c4f71bfabfd6fa50e1208ed
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(!inBounds(d, c)) {
|
|
goto end4157ddea9c4f71bfabfd6fa50e1208ed
|
|
}
|
|
v.Op = OpConst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end4157ddea9c4f71bfabfd6fa50e1208ed
|
|
end4157ddea9c4f71bfabfd6fa50e1208ed:
|
|
;
|
|
case OpAMD64SETG:
|
|
// match: (SETG (InvertFlags x))
|
|
// cond:
|
|
// result: (SETL x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto endf7586738694c9cd0b74ae28bbadb649f
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endf7586738694c9cd0b74ae28bbadb649f
|
|
endf7586738694c9cd0b74ae28bbadb649f:
|
|
;
|
|
case OpAMD64SETL:
|
|
// match: (SETL (InvertFlags x))
|
|
// cond:
|
|
// result: (SETG x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto ende33160cd86b9d4d3b77e02fb4658d5d3
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETG
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto ende33160cd86b9d4d3b77e02fb4658d5d3
|
|
ende33160cd86b9d4d3b77e02fb4658d5d3:
|
|
;
|
|
case OpAMD64SHLQ:
|
|
// match: (SHLQ x (MOVQconst [c]))
|
|
// cond:
|
|
// result: (SHLQconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto endcca412bead06dc3d56ef034a82d184d6
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SHLQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endcca412bead06dc3d56ef034a82d184d6
|
|
endcca412bead06dc3d56ef034a82d184d6:
|
|
;
|
|
case OpAMD64SHRQ:
|
|
// match: (SHRQ x (MOVQconst [c]))
|
|
// cond:
|
|
// result: (SHRQconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto endbb0d3a04dd2b810cb3dbdf7ef665f22b
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SHRQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endbb0d3a04dd2b810cb3dbdf7ef665f22b
|
|
endbb0d3a04dd2b810cb3dbdf7ef665f22b:
|
|
;
|
|
case OpAMD64SUBQ:
|
|
// match: (SUBQ x (MOVQconst [c]))
|
|
// cond:
|
|
// result: (SUBQconst x [c])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end5a74a63bd9ad15437717c6df3b25eebb
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SUBQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AuxInt = c
|
|
return true
|
|
}
|
|
goto end5a74a63bd9ad15437717c6df3b25eebb
|
|
end5a74a63bd9ad15437717c6df3b25eebb:
|
|
;
|
|
// match: (SUBQ <t> (MOVQconst [c]) x)
|
|
// cond:
|
|
// result: (NEGQ (SUBQconst <t> x [c]))
|
|
{
|
|
t := v.Type
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end78e66b6fc298684ff4ac8aec5ce873c9
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64NEGQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64SUBQconst, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AuxInt = c
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end78e66b6fc298684ff4ac8aec5ce873c9
|
|
end78e66b6fc298684ff4ac8aec5ce873c9:
|
|
;
|
|
case OpStaticCall:
|
|
// match: (StaticCall [argwid] {target} mem)
|
|
// cond:
|
|
// result: (CALLstatic [argwid] {target} mem)
|
|
{
|
|
argwid := v.AuxInt
|
|
target := v.Aux
|
|
mem := v.Args[0]
|
|
v.Op = OpAMD64CALLstatic
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = argwid
|
|
v.Aux = target
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end32c5cbec813d1c2ae94fc9b1090e4b2a
|
|
end32c5cbec813d1c2ae94fc9b1090e4b2a:
|
|
;
|
|
case OpStore:
|
|
// match: (Store ptr val mem)
|
|
// cond: (is64BitInt(val.Type) || isPtr(val.Type))
|
|
// result: (MOVQstore ptr val mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(is64BitInt(val.Type) || isPtr(val.Type)) {
|
|
goto endbaeb60123806948cd2433605820d5af1
|
|
}
|
|
v.Op = OpAMD64MOVQstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endbaeb60123806948cd2433605820d5af1
|
|
endbaeb60123806948cd2433605820d5af1:
|
|
;
|
|
// match: (Store ptr val mem)
|
|
// cond: is32BitInt(val.Type)
|
|
// result: (MOVLstore ptr val mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(is32BitInt(val.Type)) {
|
|
goto end582e895008657c728c141c6b95070de7
|
|
}
|
|
v.Op = OpAMD64MOVLstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end582e895008657c728c141c6b95070de7
|
|
end582e895008657c728c141c6b95070de7:
|
|
;
|
|
// match: (Store ptr val mem)
|
|
// cond: is16BitInt(val.Type)
|
|
// result: (MOVWstore ptr val mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(is16BitInt(val.Type)) {
|
|
goto enda3f6a985b6ebb277665f80ad30b178df
|
|
}
|
|
v.Op = OpAMD64MOVWstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto enda3f6a985b6ebb277665f80ad30b178df
|
|
enda3f6a985b6ebb277665f80ad30b178df:
|
|
;
|
|
// match: (Store ptr val mem)
|
|
// cond: is8BitInt(val.Type)
|
|
// result: (MOVBstore ptr val mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(is8BitInt(val.Type)) {
|
|
goto ende2dee0bc82f631e3c6b0031bf8d224c1
|
|
}
|
|
v.Op = OpAMD64MOVBstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto ende2dee0bc82f631e3c6b0031bf8d224c1
|
|
ende2dee0bc82f631e3c6b0031bf8d224c1:
|
|
;
|
|
// match: (Store ptr val mem)
|
|
// cond: val.Type.IsBoolean()
|
|
// result: (MOVBstore ptr val mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(val.Type.IsBoolean()) {
|
|
goto end6f343b676bf49740054e459f972b24f5
|
|
}
|
|
v.Op = OpAMD64MOVBstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end6f343b676bf49740054e459f972b24f5
|
|
end6f343b676bf49740054e459f972b24f5:
|
|
;
|
|
case OpSub16:
|
|
// match: (Sub16 x y)
|
|
// cond:
|
|
// result: (MOVWQSX (SUBW <v.Type> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MOVWQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64SUBW, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endf9d14f07ce4212200662acd073b77a79
|
|
endf9d14f07ce4212200662acd073b77a79:
|
|
;
|
|
case OpSub16U:
|
|
// match: (Sub16U x y)
|
|
// cond:
|
|
// result: (SUBW x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SUBW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end1d72e18fad1c22bb770963f167b98c96
|
|
end1d72e18fad1c22bb770963f167b98c96:
|
|
;
|
|
case OpSub32:
|
|
// match: (Sub32 x y)
|
|
// cond:
|
|
// result: (MOVLQSX (SUBL <v.Type> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MOVLQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64SUBL, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end4c091fbf93fb9599a70c001845424614
|
|
end4c091fbf93fb9599a70c001845424614:
|
|
;
|
|
case OpSub32U:
|
|
// match: (Sub32U x y)
|
|
// cond:
|
|
// result: (SUBL x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SUBL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end281d1020f0e75fce9df321580f07c4d5
|
|
end281d1020f0e75fce9df321580f07c4d5:
|
|
;
|
|
case OpSub64:
|
|
// match: (Sub64 x y)
|
|
// cond:
|
|
// result: (SUBQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SUBQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto endd88d5646309fd9174584888ecc8aca2c
|
|
endd88d5646309fd9174584888ecc8aca2c:
|
|
;
|
|
case OpSub64U:
|
|
// match: (Sub64U x y)
|
|
// cond:
|
|
// result: (SUBQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SUBQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end288f94a53865cdb00a0290d8358bb7da
|
|
end288f94a53865cdb00a0290d8358bb7da:
|
|
;
|
|
case OpSub8:
|
|
// match: (Sub8 x y)
|
|
// cond:
|
|
// result: (MOVBQSX (SUBB <v.Type> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MOVBQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64SUBB, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endfa3ef95107dcb01ae343f2243e485e80
|
|
endfa3ef95107dcb01ae343f2243e485e80:
|
|
;
|
|
case OpSub8U:
|
|
// match: (Sub8U x y)
|
|
// cond:
|
|
// result: (SUBB x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SUBB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end8f5160f898dfa43da7d7d9f8cbaf9615
|
|
end8f5160f898dfa43da7d7d9f8cbaf9615:
|
|
;
|
|
case OpZero:
|
|
// match: (Zero [0] _ mem)
|
|
// cond:
|
|
// result: (Copy mem)
|
|
{
|
|
if v.AuxInt != 0 {
|
|
goto endb85a34a7d102b0e0d801454f437db5bf
|
|
}
|
|
mem := v.Args[1]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endb85a34a7d102b0e0d801454f437db5bf
|
|
endb85a34a7d102b0e0d801454f437db5bf:
|
|
;
|
|
// match: (Zero [1] destptr mem)
|
|
// cond:
|
|
// result: (MOVBstore destptr (Const <TypeInt8> [0]) mem)
|
|
{
|
|
if v.AuxInt != 1 {
|
|
goto end09ec7b1fc5ad40534e0e25c896323f5c
|
|
}
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVBstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(destptr)
|
|
v0 := v.Block.NewValue0(v.Line, OpConst, TypeInvalid)
|
|
v0.Type = TypeInt8
|
|
v0.AuxInt = 0
|
|
v.AddArg(v0)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end09ec7b1fc5ad40534e0e25c896323f5c
|
|
end09ec7b1fc5ad40534e0e25c896323f5c:
|
|
;
|
|
// match: (Zero [2] destptr mem)
|
|
// cond:
|
|
// result: (MOVWstore destptr (Const <TypeInt16> [0]) mem)
|
|
{
|
|
if v.AuxInt != 2 {
|
|
goto end2dee246789dbd305bb1eaec768bdae14
|
|
}
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVWstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(destptr)
|
|
v0 := v.Block.NewValue0(v.Line, OpConst, TypeInvalid)
|
|
v0.Type = TypeInt16
|
|
v0.AuxInt = 0
|
|
v.AddArg(v0)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end2dee246789dbd305bb1eaec768bdae14
|
|
end2dee246789dbd305bb1eaec768bdae14:
|
|
;
|
|
// match: (Zero [4] destptr mem)
|
|
// cond:
|
|
// result: (MOVLstore destptr (Const <TypeInt32> [0]) mem)
|
|
{
|
|
if v.AuxInt != 4 {
|
|
goto ende2bf4ecf21bc9e76700a9c5f62546e78
|
|
}
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVLstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(destptr)
|
|
v0 := v.Block.NewValue0(v.Line, OpConst, TypeInvalid)
|
|
v0.Type = TypeInt32
|
|
v0.AuxInt = 0
|
|
v.AddArg(v0)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto ende2bf4ecf21bc9e76700a9c5f62546e78
|
|
ende2bf4ecf21bc9e76700a9c5f62546e78:
|
|
;
|
|
// match: (Zero [8] destptr mem)
|
|
// cond:
|
|
// result: (MOVQstore destptr (Const <TypeInt64> [0]) mem)
|
|
{
|
|
if v.AuxInt != 8 {
|
|
goto enda65d5d60783daf9b9405f04c44f7adaf
|
|
}
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVQstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(destptr)
|
|
v0 := v.Block.NewValue0(v.Line, OpConst, TypeInvalid)
|
|
v0.Type = TypeInt64
|
|
v0.AuxInt = 0
|
|
v.AddArg(v0)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto enda65d5d60783daf9b9405f04c44f7adaf
|
|
enda65d5d60783daf9b9405f04c44f7adaf:
|
|
;
|
|
// match: (Zero [size] destptr mem)
|
|
// cond: size < 4*8
|
|
// result: (MOVXzero [size] destptr mem)
|
|
{
|
|
size := v.AuxInt
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(size < 4*8) {
|
|
goto endf0a22f1506977610ac0a310eee152075
|
|
}
|
|
v.Op = OpAMD64MOVXzero
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = size
|
|
v.AddArg(destptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endf0a22f1506977610ac0a310eee152075
|
|
endf0a22f1506977610ac0a310eee152075:
|
|
;
|
|
// match: (Zero [size] destptr mem)
|
|
// cond: size >= 4*8
|
|
// result: (Zero [size%8] (OffPtr <TypeUInt64> [size-(size%8)] destptr) (REPSTOSQ <TypeMem> destptr (Const <TypeUInt64> [size/8]) mem))
|
|
{
|
|
size := v.AuxInt
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(size >= 4*8) {
|
|
goto end7a358169d20d6834b21f2e03fbf351b2
|
|
}
|
|
v.Op = OpZero
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = size % 8
|
|
v0 := v.Block.NewValue0(v.Line, OpOffPtr, TypeInvalid)
|
|
v0.Type = TypeUInt64
|
|
v0.AuxInt = size - (size % 8)
|
|
v0.AddArg(destptr)
|
|
v.AddArg(v0)
|
|
v1 := v.Block.NewValue0(v.Line, OpAMD64REPSTOSQ, TypeInvalid)
|
|
v1.Type = TypeMem
|
|
v1.AddArg(destptr)
|
|
v2 := v.Block.NewValue0(v.Line, OpConst, TypeInvalid)
|
|
v2.Type = TypeUInt64
|
|
v2.AuxInt = size / 8
|
|
v1.AddArg(v2)
|
|
v1.AddArg(mem)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end7a358169d20d6834b21f2e03fbf351b2
|
|
end7a358169d20d6834b21f2e03fbf351b2:
|
|
}
|
|
return false
|
|
}
|
|
func rewriteBlockAMD64(b *Block) bool {
|
|
switch b.Kind {
|
|
case BlockAMD64EQ:
|
|
// match: (EQ (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (EQ cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end6b8e9afc73b1c4d528f31a60d2575fae
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64EQ
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end6b8e9afc73b1c4d528f31a60d2575fae
|
|
end6b8e9afc73b1c4d528f31a60d2575fae:
|
|
;
|
|
case BlockAMD64GE:
|
|
// match: (GE (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (LE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end0610f000a6988ee8310307ec2ea138f8
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64LE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end0610f000a6988ee8310307ec2ea138f8
|
|
end0610f000a6988ee8310307ec2ea138f8:
|
|
;
|
|
case BlockAMD64GT:
|
|
// match: (GT (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (LT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto endf60c0660b6a8aa9565c97fc87f04eb34
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64LT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endf60c0660b6a8aa9565c97fc87f04eb34
|
|
endf60c0660b6a8aa9565c97fc87f04eb34:
|
|
;
|
|
case BlockIf:
|
|
// match: (If (SETL cmp) yes no)
|
|
// cond:
|
|
// result: (LT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETL {
|
|
goto ende4d36879bb8e1bd8facaa8c91ba99dcc
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64LT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto ende4d36879bb8e1bd8facaa8c91ba99dcc
|
|
ende4d36879bb8e1bd8facaa8c91ba99dcc:
|
|
;
|
|
// match: (If (SETEQ cmp) yes no)
|
|
// cond:
|
|
// result: (EQ cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETEQ {
|
|
goto endf113deb06abc88613840e6282942921a
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64EQ
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endf113deb06abc88613840e6282942921a
|
|
endf113deb06abc88613840e6282942921a:
|
|
;
|
|
// match: (If (SETNE cmp) yes no)
|
|
// cond:
|
|
// result: (NE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETNE {
|
|
goto end5ff1403aaf7b543bc454177ab584e4f5
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64NE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end5ff1403aaf7b543bc454177ab584e4f5
|
|
end5ff1403aaf7b543bc454177ab584e4f5:
|
|
;
|
|
// match: (If (SETB cmp) yes no)
|
|
// cond:
|
|
// result: (ULT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETB {
|
|
goto end04935012db9defeafceef8175f803ea2
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64ULT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end04935012db9defeafceef8175f803ea2
|
|
end04935012db9defeafceef8175f803ea2:
|
|
;
|
|
// match: (If cond yes no)
|
|
// cond: cond.Op == OpAMD64MOVBload
|
|
// result: (NE (TESTB <TypeFlags> cond cond) yes no)
|
|
{
|
|
v := b.Control
|
|
cond := v
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
if !(cond.Op == OpAMD64MOVBload) {
|
|
goto end7e22019fb0effc80f85c05ea30bdb5d9
|
|
}
|
|
b.Kind = BlockAMD64NE
|
|
v0 := v.Block.NewValue0(v.Line, OpAMD64TESTB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(cond)
|
|
v0.AddArg(cond)
|
|
b.Control = v0
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end7e22019fb0effc80f85c05ea30bdb5d9
|
|
end7e22019fb0effc80f85c05ea30bdb5d9:
|
|
;
|
|
case BlockAMD64LE:
|
|
// match: (LE (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (GE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end0d49d7d087fe7578e8015cf13dae37e3
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64GE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end0d49d7d087fe7578e8015cf13dae37e3
|
|
end0d49d7d087fe7578e8015cf13dae37e3:
|
|
;
|
|
case BlockAMD64LT:
|
|
// match: (LT (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (GT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end6a408cde0fee0ae7b7da0443c8d902bf
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64GT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end6a408cde0fee0ae7b7da0443c8d902bf
|
|
end6a408cde0fee0ae7b7da0443c8d902bf:
|
|
;
|
|
case BlockAMD64NE:
|
|
// match: (NE (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (NE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end713001aba794e50b582fbff930e110af
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64NE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end713001aba794e50b582fbff930e110af
|
|
end713001aba794e50b582fbff930e110af:
|
|
;
|
|
case BlockAMD64UGE:
|
|
// match: (UGE (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (ULE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto ende3e4ddc183ca1a46598b11c2d0d13966
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64ULE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto ende3e4ddc183ca1a46598b11c2d0d13966
|
|
ende3e4ddc183ca1a46598b11c2d0d13966:
|
|
;
|
|
case BlockAMD64UGT:
|
|
// match: (UGT (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (ULT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end49818853af2e5251175d06c62768cae7
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64ULT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end49818853af2e5251175d06c62768cae7
|
|
end49818853af2e5251175d06c62768cae7:
|
|
;
|
|
case BlockAMD64ULE:
|
|
// match: (ULE (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (UGE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto endd6698aac0d67261293b558c95ea17b4f
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64UGE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endd6698aac0d67261293b558c95ea17b4f
|
|
endd6698aac0d67261293b558c95ea17b4f:
|
|
;
|
|
case BlockAMD64ULT:
|
|
// match: (ULT (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (UGT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end35105dbc9646f02577167e45ae2f2fd2
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64UGT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end35105dbc9646f02577167e45ae2f2fd2
|
|
end35105dbc9646f02577167e45ae2f2fd2:
|
|
}
|
|
return false
|
|
}
|