mirror of
https://github.com/golang/go.git
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Generating logging code every time causes large diffs for small changes. Since the intent is to use this for debugging only, generate logging code only when requested. Committed generated code will be logging free. Change-Id: I9ef9e29c88b76c2557bad4c6b424b9db1255ec8b Reviewed-on: https://go-review.googlesource.com/13623 Reviewed-by: Keith Randall <khr@golang.org>
8888 lines
190 KiB
Go
8888 lines
190 KiB
Go
// autogenerated from gen/AMD64.rules: do not edit!
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// generated with: cd gen; go run *.go
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package ssa
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func rewriteValueAMD64(v *Value, config *Config) bool {
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b := v.Block
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switch v.Op {
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case OpAMD64ADDB:
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// match: (ADDB x (MOVBconst [c]))
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// cond:
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// result: (ADDBconst [c] x)
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{
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x := v.Args[0]
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if v.Args[1].Op != OpAMD64MOVBconst {
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goto endab690db69bfd8192eea57a2f9f76bf84
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}
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c := v.Args[1].AuxInt
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v.Op = OpAMD64ADDBconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
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}
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goto endab690db69bfd8192eea57a2f9f76bf84
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endab690db69bfd8192eea57a2f9f76bf84:
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;
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// match: (ADDB (MOVBconst [c]) x)
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// cond:
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// result: (ADDBconst [c] x)
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{
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if v.Args[0].Op != OpAMD64MOVBconst {
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goto end28aa1a4abe7e1abcdd64135e9967d39d
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}
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c := v.Args[0].AuxInt
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x := v.Args[1]
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v.Op = OpAMD64ADDBconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
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}
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goto end28aa1a4abe7e1abcdd64135e9967d39d
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end28aa1a4abe7e1abcdd64135e9967d39d:
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;
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// match: (ADDB x (NEGB y))
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// cond:
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// result: (SUBB x y)
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{
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x := v.Args[0]
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if v.Args[1].Op != OpAMD64NEGB {
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goto end9464509b8874ffb00b43b843da01f0bc
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}
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y := v.Args[1].Args[0]
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v.Op = OpAMD64SUBB
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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v.AddArg(y)
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return true
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}
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goto end9464509b8874ffb00b43b843da01f0bc
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end9464509b8874ffb00b43b843da01f0bc:
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;
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case OpAMD64ADDBconst:
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// match: (ADDBconst [c] (MOVBconst [d]))
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// cond:
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// result: (MOVBconst [c+d])
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{
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c := v.AuxInt
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if v.Args[0].Op != OpAMD64MOVBconst {
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goto enda9b1e9e31ccdf0af5f4fe57bf4b1343f
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}
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d := v.Args[0].AuxInt
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v.Op = OpAMD64MOVBconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c + d
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return true
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}
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goto enda9b1e9e31ccdf0af5f4fe57bf4b1343f
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enda9b1e9e31ccdf0af5f4fe57bf4b1343f:
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;
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// match: (ADDBconst [c] (ADDBconst [d] x))
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// cond:
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// result: (ADDBconst [c+d] x)
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{
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c := v.AuxInt
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if v.Args[0].Op != OpAMD64ADDBconst {
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goto end9b1e6890adbf9d9e447d591b4148cbd0
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}
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d := v.Args[0].AuxInt
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x := v.Args[0].Args[0]
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v.Op = OpAMD64ADDBconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c + d
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v.AddArg(x)
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return true
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}
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goto end9b1e6890adbf9d9e447d591b4148cbd0
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end9b1e6890adbf9d9e447d591b4148cbd0:
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;
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case OpAMD64ADDL:
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// match: (ADDL x (MOVLconst [c]))
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// cond:
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// result: (ADDLconst [c] x)
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{
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x := v.Args[0]
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if v.Args[1].Op != OpAMD64MOVLconst {
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goto end8d6d3b99a7be8da6b7a254b7e709cc95
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}
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c := v.Args[1].AuxInt
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v.Op = OpAMD64ADDLconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
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}
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goto end8d6d3b99a7be8da6b7a254b7e709cc95
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end8d6d3b99a7be8da6b7a254b7e709cc95:
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;
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// match: (ADDL (MOVLconst [c]) x)
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// cond:
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// result: (ADDLconst [c] x)
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{
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if v.Args[0].Op != OpAMD64MOVLconst {
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goto end739561e08a561e26ce3634dc0d5ec733
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}
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c := v.Args[0].AuxInt
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x := v.Args[1]
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v.Op = OpAMD64ADDLconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
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}
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goto end739561e08a561e26ce3634dc0d5ec733
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end739561e08a561e26ce3634dc0d5ec733:
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;
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// match: (ADDL x (NEGL y))
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// cond:
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// result: (SUBL x y)
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{
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x := v.Args[0]
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if v.Args[1].Op != OpAMD64NEGL {
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goto end9596df31f2685a49df67c6fb912a521d
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}
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y := v.Args[1].Args[0]
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v.Op = OpAMD64SUBL
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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v.AddArg(y)
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return true
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}
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goto end9596df31f2685a49df67c6fb912a521d
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end9596df31f2685a49df67c6fb912a521d:
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;
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case OpAMD64ADDLconst:
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// match: (ADDLconst [c] (MOVLconst [d]))
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// cond:
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// result: (MOVLconst [c+d])
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{
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c := v.AuxInt
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if v.Args[0].Op != OpAMD64MOVLconst {
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goto ende04850e987890abf1d66199042a19c23
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}
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d := v.Args[0].AuxInt
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v.Op = OpAMD64MOVLconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c + d
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return true
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}
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goto ende04850e987890abf1d66199042a19c23
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ende04850e987890abf1d66199042a19c23:
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;
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// match: (ADDLconst [c] (ADDLconst [d] x))
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// cond:
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// result: (ADDLconst [c+d] x)
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{
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c := v.AuxInt
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if v.Args[0].Op != OpAMD64ADDLconst {
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goto endf1dd8673b2fef4950aec87aa7523a236
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}
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d := v.Args[0].AuxInt
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x := v.Args[0].Args[0]
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v.Op = OpAMD64ADDLconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c + d
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v.AddArg(x)
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return true
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}
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goto endf1dd8673b2fef4950aec87aa7523a236
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endf1dd8673b2fef4950aec87aa7523a236:
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;
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case OpAMD64ADDQ:
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// match: (ADDQ x (MOVQconst [c]))
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// cond: is32Bit(c)
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// result: (ADDQconst [c] x)
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{
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x := v.Args[0]
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if v.Args[1].Op != OpAMD64MOVQconst {
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goto end1de8aeb1d043e0dadcffd169a99ce5c0
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}
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c := v.Args[1].AuxInt
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if !(is32Bit(c)) {
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goto end1de8aeb1d043e0dadcffd169a99ce5c0
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}
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v.Op = OpAMD64ADDQconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
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}
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goto end1de8aeb1d043e0dadcffd169a99ce5c0
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end1de8aeb1d043e0dadcffd169a99ce5c0:
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;
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// match: (ADDQ (MOVQconst [c]) x)
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// cond: is32Bit(c)
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// result: (ADDQconst [c] x)
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{
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if v.Args[0].Op != OpAMD64MOVQconst {
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goto endca635e3bdecd9e3aeb892f841021dfaa
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}
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c := v.Args[0].AuxInt
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x := v.Args[1]
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if !(is32Bit(c)) {
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goto endca635e3bdecd9e3aeb892f841021dfaa
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}
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v.Op = OpAMD64ADDQconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
|
|
}
|
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goto endca635e3bdecd9e3aeb892f841021dfaa
|
|
endca635e3bdecd9e3aeb892f841021dfaa:
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;
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// match: (ADDQ x (SHLQconst [3] y))
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// cond:
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// result: (LEAQ8 x y)
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{
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x := v.Args[0]
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if v.Args[1].Op != OpAMD64SHLQconst {
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goto endc02313d35a0525d1d680cd58992e820d
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}
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if v.Args[1].AuxInt != 3 {
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goto endc02313d35a0525d1d680cd58992e820d
|
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}
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y := v.Args[1].Args[0]
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v.Op = OpAMD64LEAQ8
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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v.AddArg(y)
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return true
|
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}
|
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goto endc02313d35a0525d1d680cd58992e820d
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endc02313d35a0525d1d680cd58992e820d:
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;
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// match: (ADDQ x (NEGQ y))
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// cond:
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// result: (SUBQ x y)
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{
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x := v.Args[0]
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if v.Args[1].Op != OpAMD64NEGQ {
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goto endec8f899c6e175a0147a90750f9bfe0a2
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}
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y := v.Args[1].Args[0]
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v.Op = OpAMD64SUBQ
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(x)
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v.AddArg(y)
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return true
|
|
}
|
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goto endec8f899c6e175a0147a90750f9bfe0a2
|
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endec8f899c6e175a0147a90750f9bfe0a2:
|
|
;
|
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case OpAMD64ADDQconst:
|
|
// match: (ADDQconst [c] (LEAQ8 [d] x y))
|
|
// cond:
|
|
// result: (LEAQ8 [addOff(c, d)] x y)
|
|
{
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|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64LEAQ8 {
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|
goto ende2cc681c9abf9913288803fb1b39e639
|
|
}
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d := v.Args[0].AuxInt
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x := v.Args[0].Args[0]
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y := v.Args[0].Args[1]
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v.Op = OpAMD64LEAQ8
|
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v.AuxInt = 0
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v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(c, d)
|
|
v.AddArg(x)
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v.AddArg(y)
|
|
return true
|
|
}
|
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goto ende2cc681c9abf9913288803fb1b39e639
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ende2cc681c9abf9913288803fb1b39e639:
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;
|
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// match: (ADDQconst [0] x)
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// cond:
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|
// result: x
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|
{
|
|
if v.AuxInt != 0 {
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|
goto end03d9f5a3e153048b0afa781401e2a849
|
|
}
|
|
x := v.Args[0]
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|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
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goto end03d9f5a3e153048b0afa781401e2a849
|
|
end03d9f5a3e153048b0afa781401e2a849:
|
|
;
|
|
// match: (ADDQconst [c] (MOVQconst [d]))
|
|
// cond:
|
|
// result: (MOVQconst [c+d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end09dc54395b4e96e8332cf8e4e7481c52
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c + d
|
|
return true
|
|
}
|
|
goto end09dc54395b4e96e8332cf8e4e7481c52
|
|
end09dc54395b4e96e8332cf8e4e7481c52:
|
|
;
|
|
// match: (ADDQconst [c] (ADDQconst [d] x))
|
|
// cond:
|
|
// result: (ADDQconst [c+d] x)
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
|
goto endd4cb539641f0dc40bfd0cb7fbb9b0405
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64ADDQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c + d
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endd4cb539641f0dc40bfd0cb7fbb9b0405
|
|
endd4cb539641f0dc40bfd0cb7fbb9b0405:
|
|
;
|
|
case OpAMD64ADDW:
|
|
// match: (ADDW x (MOVWconst [c]))
|
|
// cond:
|
|
// result: (ADDWconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWconst {
|
|
goto end1aabd2317de77c7dfc4876fd7e4c5011
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64ADDWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end1aabd2317de77c7dfc4876fd7e4c5011
|
|
end1aabd2317de77c7dfc4876fd7e4c5011:
|
|
;
|
|
// match: (ADDW (MOVWconst [c]) x)
|
|
// cond:
|
|
// result: (ADDWconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto ende3aede99966f388afc624f9e86676fd2
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64ADDWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto ende3aede99966f388afc624f9e86676fd2
|
|
ende3aede99966f388afc624f9e86676fd2:
|
|
;
|
|
// match: (ADDW x (NEGW y))
|
|
// cond:
|
|
// result: (SUBW x y)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64NEGW {
|
|
goto end55cf2af0d75f3ec413528eeb799e94d5
|
|
}
|
|
y := v.Args[1].Args[0]
|
|
v.Op = OpAMD64SUBW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end55cf2af0d75f3ec413528eeb799e94d5
|
|
end55cf2af0d75f3ec413528eeb799e94d5:
|
|
;
|
|
case OpAMD64ADDWconst:
|
|
// match: (ADDWconst [c] (MOVWconst [d]))
|
|
// cond:
|
|
// result: (MOVWconst [c+d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto end32541920f2f5a920dfae41d8ebbef00f
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c + d
|
|
return true
|
|
}
|
|
goto end32541920f2f5a920dfae41d8ebbef00f
|
|
end32541920f2f5a920dfae41d8ebbef00f:
|
|
;
|
|
// match: (ADDWconst [c] (ADDWconst [d] x))
|
|
// cond:
|
|
// result: (ADDWconst [c+d] x)
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64ADDWconst {
|
|
goto end73944f6ddda7e4c050f11d17484ff9a5
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64ADDWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c + d
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end73944f6ddda7e4c050f11d17484ff9a5
|
|
end73944f6ddda7e4c050f11d17484ff9a5:
|
|
;
|
|
case OpAMD64ANDB:
|
|
// match: (ANDB x (MOVLconst [c]))
|
|
// cond:
|
|
// result: (ANDBconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLconst {
|
|
goto end01100cd255396e29bfdb130f4fbc9bbc
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64ANDBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end01100cd255396e29bfdb130f4fbc9bbc
|
|
end01100cd255396e29bfdb130f4fbc9bbc:
|
|
;
|
|
// match: (ANDB (MOVLconst [c]) x)
|
|
// cond:
|
|
// result: (ANDBconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto end70830ce2834dc5f8d786fa6789460926
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64ANDBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end70830ce2834dc5f8d786fa6789460926
|
|
end70830ce2834dc5f8d786fa6789460926:
|
|
;
|
|
// match: (ANDB x (MOVBconst [c]))
|
|
// cond:
|
|
// result: (ANDBconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBconst {
|
|
goto endd275ec2e73768cb3d201478fc934e06c
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64ANDBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endd275ec2e73768cb3d201478fc934e06c
|
|
endd275ec2e73768cb3d201478fc934e06c:
|
|
;
|
|
// match: (ANDB (MOVBconst [c]) x)
|
|
// cond:
|
|
// result: (ANDBconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVBconst {
|
|
goto end4068edac2ae0f354cf581db210288b98
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64ANDBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end4068edac2ae0f354cf581db210288b98
|
|
end4068edac2ae0f354cf581db210288b98:
|
|
;
|
|
// match: (ANDB x x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto endb8ff272a1456513da708603abe37541c
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endb8ff272a1456513da708603abe37541c
|
|
endb8ff272a1456513da708603abe37541c:
|
|
;
|
|
case OpAMD64ANDBconst:
|
|
// match: (ANDBconst [c] _)
|
|
// cond: int8(c)==0
|
|
// result: (MOVBconst [0])
|
|
{
|
|
c := v.AuxInt
|
|
if !(int8(c) == 0) {
|
|
goto end2106d410c949da14d7c00041f40eca76
|
|
}
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end2106d410c949da14d7c00041f40eca76
|
|
end2106d410c949da14d7c00041f40eca76:
|
|
;
|
|
// match: (ANDBconst [c] x)
|
|
// cond: int8(c)==-1
|
|
// result: x
|
|
{
|
|
c := v.AuxInt
|
|
x := v.Args[0]
|
|
if !(int8(c) == -1) {
|
|
goto enda0b78503c204c8225de1433949a71fe4
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enda0b78503c204c8225de1433949a71fe4
|
|
enda0b78503c204c8225de1433949a71fe4:
|
|
;
|
|
// match: (ANDBconst [c] (MOVBconst [d]))
|
|
// cond:
|
|
// result: (MOVBconst [c&d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVBconst {
|
|
goto end946312b1f216933da86febe293eb956f
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & d
|
|
return true
|
|
}
|
|
goto end946312b1f216933da86febe293eb956f
|
|
end946312b1f216933da86febe293eb956f:
|
|
;
|
|
case OpAMD64ANDL:
|
|
// match: (ANDL x (MOVLconst [c]))
|
|
// cond:
|
|
// result: (ANDLconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLconst {
|
|
goto end0a4c49d9a26759c0fd21369dafcd7abb
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64ANDLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end0a4c49d9a26759c0fd21369dafcd7abb
|
|
end0a4c49d9a26759c0fd21369dafcd7abb:
|
|
;
|
|
// match: (ANDL (MOVLconst [c]) x)
|
|
// cond:
|
|
// result: (ANDLconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto end0529ba323d9b6f15c41add401ef67959
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64ANDLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end0529ba323d9b6f15c41add401ef67959
|
|
end0529ba323d9b6f15c41add401ef67959:
|
|
;
|
|
// match: (ANDL x x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto enddfb08a0d0c262854db3905cb323388c7
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enddfb08a0d0c262854db3905cb323388c7
|
|
enddfb08a0d0c262854db3905cb323388c7:
|
|
;
|
|
case OpAMD64ANDLconst:
|
|
// match: (ANDLconst [c] _)
|
|
// cond: int32(c)==0
|
|
// result: (MOVLconst [0])
|
|
{
|
|
c := v.AuxInt
|
|
if !(int32(c) == 0) {
|
|
goto end5efb241208aef28c950b7bcf8d85d5de
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end5efb241208aef28c950b7bcf8d85d5de
|
|
end5efb241208aef28c950b7bcf8d85d5de:
|
|
;
|
|
// match: (ANDLconst [c] x)
|
|
// cond: int32(c)==-1
|
|
// result: x
|
|
{
|
|
c := v.AuxInt
|
|
x := v.Args[0]
|
|
if !(int32(c) == -1) {
|
|
goto end0e852ae30bb8289d6ffee0c9267e3e0c
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end0e852ae30bb8289d6ffee0c9267e3e0c
|
|
end0e852ae30bb8289d6ffee0c9267e3e0c:
|
|
;
|
|
// match: (ANDLconst [c] (MOVLconst [d]))
|
|
// cond:
|
|
// result: (MOVLconst [c&d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto end7bfd24059369753eadd235f07e2dd7b8
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & d
|
|
return true
|
|
}
|
|
goto end7bfd24059369753eadd235f07e2dd7b8
|
|
end7bfd24059369753eadd235f07e2dd7b8:
|
|
;
|
|
case OpAMD64ANDQ:
|
|
// match: (ANDQ x (MOVQconst [c]))
|
|
// cond: is32Bit(c)
|
|
// result: (ANDQconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end048fadc69e81103480015b84b9cafff7
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
if !(is32Bit(c)) {
|
|
goto end048fadc69e81103480015b84b9cafff7
|
|
}
|
|
v.Op = OpAMD64ANDQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end048fadc69e81103480015b84b9cafff7
|
|
end048fadc69e81103480015b84b9cafff7:
|
|
;
|
|
// match: (ANDQ (MOVQconst [c]) x)
|
|
// cond: is32Bit(c)
|
|
// result: (ANDQconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end3035a3bf650b708705fd27dd857ab0a4
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
if !(is32Bit(c)) {
|
|
goto end3035a3bf650b708705fd27dd857ab0a4
|
|
}
|
|
v.Op = OpAMD64ANDQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end3035a3bf650b708705fd27dd857ab0a4
|
|
end3035a3bf650b708705fd27dd857ab0a4:
|
|
;
|
|
// match: (ANDQ x x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto end06b5ec19efdd4e79f03a5e4a2c3c3427
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end06b5ec19efdd4e79f03a5e4a2c3c3427
|
|
end06b5ec19efdd4e79f03a5e4a2c3c3427:
|
|
;
|
|
case OpAMD64ANDQconst:
|
|
// match: (ANDQconst [0] _)
|
|
// cond:
|
|
// result: (MOVQconst [0])
|
|
{
|
|
if v.AuxInt != 0 {
|
|
goto end57018c1d0f54fd721521095b4832bab2
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end57018c1d0f54fd721521095b4832bab2
|
|
end57018c1d0f54fd721521095b4832bab2:
|
|
;
|
|
// match: (ANDQconst [-1] x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
if v.AuxInt != -1 {
|
|
goto endb542c4b42ab94a7bedb32dec8f610d67
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endb542c4b42ab94a7bedb32dec8f610d67
|
|
endb542c4b42ab94a7bedb32dec8f610d67:
|
|
;
|
|
// match: (ANDQconst [c] (MOVQconst [d]))
|
|
// cond:
|
|
// result: (MOVQconst [c&d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end67ca66494705b0345a5f22c710225292
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & d
|
|
return true
|
|
}
|
|
goto end67ca66494705b0345a5f22c710225292
|
|
end67ca66494705b0345a5f22c710225292:
|
|
;
|
|
case OpAMD64ANDW:
|
|
// match: (ANDW x (MOVLconst [c]))
|
|
// cond:
|
|
// result: (ANDWconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLconst {
|
|
goto endce6f557823ee2fdd7a8f47b6f925fc7c
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64ANDWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endce6f557823ee2fdd7a8f47b6f925fc7c
|
|
endce6f557823ee2fdd7a8f47b6f925fc7c:
|
|
;
|
|
// match: (ANDW (MOVLconst [c]) x)
|
|
// cond:
|
|
// result: (ANDWconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto endc46af0d9265c08b09f1f1fba24feda80
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64ANDWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endc46af0d9265c08b09f1f1fba24feda80
|
|
endc46af0d9265c08b09f1f1fba24feda80:
|
|
;
|
|
// match: (ANDW x (MOVWconst [c]))
|
|
// cond:
|
|
// result: (ANDWconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWconst {
|
|
goto enda77a39f65a5eb3436a5842eab69a3103
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64ANDWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enda77a39f65a5eb3436a5842eab69a3103
|
|
enda77a39f65a5eb3436a5842eab69a3103:
|
|
;
|
|
// match: (ANDW (MOVWconst [c]) x)
|
|
// cond:
|
|
// result: (ANDWconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto endea2a25eb525a5dbf6d5132d84ea4e7a5
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64ANDWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endea2a25eb525a5dbf6d5132d84ea4e7a5
|
|
endea2a25eb525a5dbf6d5132d84ea4e7a5:
|
|
;
|
|
// match: (ANDW x x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto end3a26cf52dd1b77f07cc9e005760dbb11
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end3a26cf52dd1b77f07cc9e005760dbb11
|
|
end3a26cf52dd1b77f07cc9e005760dbb11:
|
|
;
|
|
case OpAMD64ANDWconst:
|
|
// match: (ANDWconst [c] _)
|
|
// cond: int16(c)==0
|
|
// result: (MOVWconst [0])
|
|
{
|
|
c := v.AuxInt
|
|
if !(int16(c) == 0) {
|
|
goto end336ece33b4f0fb44dfe1f24981df7b74
|
|
}
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end336ece33b4f0fb44dfe1f24981df7b74
|
|
end336ece33b4f0fb44dfe1f24981df7b74:
|
|
;
|
|
// match: (ANDWconst [c] x)
|
|
// cond: int16(c)==-1
|
|
// result: x
|
|
{
|
|
c := v.AuxInt
|
|
x := v.Args[0]
|
|
if !(int16(c) == -1) {
|
|
goto endfb111c3afa8c5c4040fa6000fadee810
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endfb111c3afa8c5c4040fa6000fadee810
|
|
endfb111c3afa8c5c4040fa6000fadee810:
|
|
;
|
|
// match: (ANDWconst [c] (MOVWconst [d]))
|
|
// cond:
|
|
// result: (MOVWconst [c&d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto end250eb27fcac10bf6c0d96ce66a21726e
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & d
|
|
return true
|
|
}
|
|
goto end250eb27fcac10bf6c0d96ce66a21726e
|
|
end250eb27fcac10bf6c0d96ce66a21726e:
|
|
;
|
|
case OpAdd16:
|
|
// match: (Add16 x y)
|
|
// cond:
|
|
// result: (ADDW x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ADDW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto ende604481c6de9fe4574cb2954ba2ddc67
|
|
ende604481c6de9fe4574cb2954ba2ddc67:
|
|
;
|
|
case OpAdd32:
|
|
// match: (Add32 x y)
|
|
// cond:
|
|
// result: (ADDL x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ADDL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto endc445ea2a65385445676cd684ae9a42b5
|
|
endc445ea2a65385445676cd684ae9a42b5:
|
|
;
|
|
case OpAdd64:
|
|
// match: (Add64 x y)
|
|
// cond:
|
|
// result: (ADDQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ADDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto endd88f18b3f39e3ccc201477a616f0abc0
|
|
endd88f18b3f39e3ccc201477a616f0abc0:
|
|
;
|
|
case OpAdd8:
|
|
// match: (Add8 x y)
|
|
// cond:
|
|
// result: (ADDB x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ADDB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end6117c84a6b75c1b816b3fb095bc5f656
|
|
end6117c84a6b75c1b816b3fb095bc5f656:
|
|
;
|
|
case OpAddPtr:
|
|
// match: (AddPtr x y)
|
|
// cond:
|
|
// result: (ADDQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ADDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto enda1d5640788c7157996f9d4af602dec1c
|
|
enda1d5640788c7157996f9d4af602dec1c:
|
|
;
|
|
case OpAddr:
|
|
// match: (Addr {sym} base)
|
|
// cond:
|
|
// result: (LEAQ {sym} base)
|
|
{
|
|
sym := v.Aux
|
|
base := v.Args[0]
|
|
v.Op = OpAMD64LEAQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Aux = sym
|
|
v.AddArg(base)
|
|
return true
|
|
}
|
|
goto end53cad0c3c9daa5575680e77c14e05e72
|
|
end53cad0c3c9daa5575680e77c14e05e72:
|
|
;
|
|
case OpAnd16:
|
|
// match: (And16 x y)
|
|
// cond:
|
|
// result: (ANDW x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end1c01f04a173d86ce1a6d1ef59e753014
|
|
end1c01f04a173d86ce1a6d1ef59e753014:
|
|
;
|
|
case OpAnd32:
|
|
// match: (And32 x y)
|
|
// cond:
|
|
// result: (ANDL x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end6b9eb9375b3a859028a6ba6bf6b8ec88
|
|
end6b9eb9375b3a859028a6ba6bf6b8ec88:
|
|
;
|
|
case OpAnd64:
|
|
// match: (And64 x y)
|
|
// cond:
|
|
// result: (ANDQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto enda0bde5853819d05fa2b7d3b723629552
|
|
enda0bde5853819d05fa2b7d3b723629552:
|
|
;
|
|
case OpAnd8:
|
|
// match: (And8 x y)
|
|
// cond:
|
|
// result: (ANDB x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end0f53bee6291f1229b43aa1b5f977b4f2
|
|
end0f53bee6291f1229b43aa1b5f977b4f2:
|
|
;
|
|
case OpAMD64CMPB:
|
|
// match: (CMPB x (MOVBconst [c]))
|
|
// cond:
|
|
// result: (CMPBconst x [c])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBconst {
|
|
goto end52190c0b8759133aa6c540944965c4c0
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64CMPBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AuxInt = c
|
|
return true
|
|
}
|
|
goto end52190c0b8759133aa6c540944965c4c0
|
|
end52190c0b8759133aa6c540944965c4c0:
|
|
;
|
|
// match: (CMPB (MOVBconst [c]) x)
|
|
// cond:
|
|
// result: (InvertFlags (CMPBconst <TypeFlags> x [c]))
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVBconst {
|
|
goto end6798593f4f9a27e90de089b3248187fd
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64InvertFlags
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AuxInt = c
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end6798593f4f9a27e90de089b3248187fd
|
|
end6798593f4f9a27e90de089b3248187fd:
|
|
;
|
|
case OpAMD64CMPL:
|
|
// match: (CMPL x (MOVLconst [c]))
|
|
// cond:
|
|
// result: (CMPLconst x [c])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLconst {
|
|
goto end49ff4559c4bdecb2aef0c905e2d9a6cf
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64CMPLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AuxInt = c
|
|
return true
|
|
}
|
|
goto end49ff4559c4bdecb2aef0c905e2d9a6cf
|
|
end49ff4559c4bdecb2aef0c905e2d9a6cf:
|
|
;
|
|
// match: (CMPL (MOVLconst [c]) x)
|
|
// cond:
|
|
// result: (InvertFlags (CMPLconst <TypeFlags> x [c]))
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto end3c04e861f07a442be9e2f5e0e0d07cce
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64InvertFlags
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AuxInt = c
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end3c04e861f07a442be9e2f5e0e0d07cce
|
|
end3c04e861f07a442be9e2f5e0e0d07cce:
|
|
;
|
|
case OpAMD64CMPQ:
|
|
// match: (CMPQ x (MOVQconst [c]))
|
|
// cond: is32Bit(c)
|
|
// result: (CMPQconst x [c])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end3bbb2c6caa57853a7561738ce3c0c630
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
if !(is32Bit(c)) {
|
|
goto end3bbb2c6caa57853a7561738ce3c0c630
|
|
}
|
|
v.Op = OpAMD64CMPQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AuxInt = c
|
|
return true
|
|
}
|
|
goto end3bbb2c6caa57853a7561738ce3c0c630
|
|
end3bbb2c6caa57853a7561738ce3c0c630:
|
|
;
|
|
// match: (CMPQ (MOVQconst [c]) x)
|
|
// cond: is32Bit(c)
|
|
// result: (InvertFlags (CMPQconst <TypeFlags> x [c]))
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end5edbe48a495a51ecabd3b2c0ed44a3d3
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
if !(is32Bit(c)) {
|
|
goto end5edbe48a495a51ecabd3b2c0ed44a3d3
|
|
}
|
|
v.Op = OpAMD64InvertFlags
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AuxInt = c
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end5edbe48a495a51ecabd3b2c0ed44a3d3
|
|
end5edbe48a495a51ecabd3b2c0ed44a3d3:
|
|
;
|
|
case OpAMD64CMPW:
|
|
// match: (CMPW x (MOVWconst [c]))
|
|
// cond:
|
|
// result: (CMPWconst x [c])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWconst {
|
|
goto end310a9ba58ac35c97587e08c63fe8a46c
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64CMPWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AuxInt = c
|
|
return true
|
|
}
|
|
goto end310a9ba58ac35c97587e08c63fe8a46c
|
|
end310a9ba58ac35c97587e08c63fe8a46c:
|
|
;
|
|
// match: (CMPW (MOVWconst [c]) x)
|
|
// cond:
|
|
// result: (InvertFlags (CMPWconst <TypeFlags> x [c]))
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto end1ce191aaab0f4dd3b98dafdfbfac13ce
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64InvertFlags
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AuxInt = c
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end1ce191aaab0f4dd3b98dafdfbfac13ce
|
|
end1ce191aaab0f4dd3b98dafdfbfac13ce:
|
|
;
|
|
case OpClosureCall:
|
|
// match: (ClosureCall [argwid] entry closure mem)
|
|
// cond:
|
|
// result: (CALLclosure [argwid] entry closure mem)
|
|
{
|
|
argwid := v.AuxInt
|
|
entry := v.Args[0]
|
|
closure := v.Args[1]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64CALLclosure
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = argwid
|
|
v.AddArg(entry)
|
|
v.AddArg(closure)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endfd75d26316012d86cb71d0dd1214259b
|
|
endfd75d26316012d86cb71d0dd1214259b:
|
|
;
|
|
case OpCom16:
|
|
// match: (Com16 x)
|
|
// cond:
|
|
// result: (NOTW x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NOTW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end1b14ba8d7d7aa585ec0a211827f280ae
|
|
end1b14ba8d7d7aa585ec0a211827f280ae:
|
|
;
|
|
case OpCom32:
|
|
// match: (Com32 x)
|
|
// cond:
|
|
// result: (NOTL x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NOTL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end6eb124ba3bdb3fd6031414370852feb6
|
|
end6eb124ba3bdb3fd6031414370852feb6:
|
|
;
|
|
case OpCom64:
|
|
// match: (Com64 x)
|
|
// cond:
|
|
// result: (NOTQ x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NOTQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endf5f3b355a87779c347e305719dddda05
|
|
endf5f3b355a87779c347e305719dddda05:
|
|
;
|
|
case OpCom8:
|
|
// match: (Com8 x)
|
|
// cond:
|
|
// result: (NOTB x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NOTB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end1c7c5c055d663ccf1f05fbc4883030c6
|
|
end1c7c5c055d663ccf1f05fbc4883030c6:
|
|
;
|
|
case OpConst16:
|
|
// match: (Const16 [val])
|
|
// cond:
|
|
// result: (MOVWconst [val])
|
|
{
|
|
val := v.AuxInt
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = val
|
|
return true
|
|
}
|
|
goto end2c6c92f297873b8ac12bd035d56d001e
|
|
end2c6c92f297873b8ac12bd035d56d001e:
|
|
;
|
|
case OpConst32:
|
|
// match: (Const32 [val])
|
|
// cond:
|
|
// result: (MOVLconst [val])
|
|
{
|
|
val := v.AuxInt
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = val
|
|
return true
|
|
}
|
|
goto enddae5807662af67143a3ac3ad9c63bae5
|
|
enddae5807662af67143a3ac3ad9c63bae5:
|
|
;
|
|
case OpConst64:
|
|
// match: (Const64 [val])
|
|
// cond:
|
|
// result: (MOVQconst [val])
|
|
{
|
|
val := v.AuxInt
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = val
|
|
return true
|
|
}
|
|
goto endc630434ae7f143ab69d5f482a9b52b5f
|
|
endc630434ae7f143ab69d5f482a9b52b5f:
|
|
;
|
|
case OpConst8:
|
|
// match: (Const8 [val])
|
|
// cond:
|
|
// result: (MOVBconst [val])
|
|
{
|
|
val := v.AuxInt
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = val
|
|
return true
|
|
}
|
|
goto end200524c722ed14ca935ba47f8f30327d
|
|
end200524c722ed14ca935ba47f8f30327d:
|
|
;
|
|
case OpConstBool:
|
|
// match: (ConstBool {b})
|
|
// cond: !b.(bool)
|
|
// result: (MOVBconst [0])
|
|
{
|
|
b := v.Aux
|
|
if !(!b.(bool)) {
|
|
goto end876159ea073d2dcefcc251667c1a7780
|
|
}
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end876159ea073d2dcefcc251667c1a7780
|
|
end876159ea073d2dcefcc251667c1a7780:
|
|
;
|
|
// match: (ConstBool {b})
|
|
// cond: b.(bool)
|
|
// result: (MOVBconst [1])
|
|
{
|
|
b := v.Aux
|
|
if !(b.(bool)) {
|
|
goto end0dacad3f7cad53905aad5303391447f6
|
|
}
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 1
|
|
return true
|
|
}
|
|
goto end0dacad3f7cad53905aad5303391447f6
|
|
end0dacad3f7cad53905aad5303391447f6:
|
|
;
|
|
case OpConstNil:
|
|
// match: (ConstNil)
|
|
// cond:
|
|
// result: (MOVQconst [0])
|
|
{
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto endea557d921056c25b945a49649e4b9b91
|
|
endea557d921056c25b945a49649e4b9b91:
|
|
;
|
|
case OpConstPtr:
|
|
// match: (ConstPtr [val])
|
|
// cond:
|
|
// result: (MOVQconst [val])
|
|
{
|
|
val := v.AuxInt
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = val
|
|
return true
|
|
}
|
|
goto endc395c0a53eeccf597e225a07b53047d1
|
|
endc395c0a53eeccf597e225a07b53047d1:
|
|
;
|
|
case OpEq16:
|
|
// match: (Eq16 x y)
|
|
// cond:
|
|
// result: (SETEQ (CMPW <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETEQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end66a03470b5b3e8457ba205ccfcaccea6
|
|
end66a03470b5b3e8457ba205ccfcaccea6:
|
|
;
|
|
case OpEq32:
|
|
// match: (Eq32 x y)
|
|
// cond:
|
|
// result: (SETEQ (CMPL <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETEQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end4d77d0b016f93817fd6e5f60fa0e7ef2
|
|
end4d77d0b016f93817fd6e5f60fa0e7ef2:
|
|
;
|
|
case OpEq64:
|
|
// match: (Eq64 x y)
|
|
// cond:
|
|
// result: (SETEQ (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETEQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endae6c62e4e20b4f62694b6ee40dbd9211
|
|
endae6c62e4e20b4f62694b6ee40dbd9211:
|
|
;
|
|
case OpEq8:
|
|
// match: (Eq8 x y)
|
|
// cond:
|
|
// result: (SETEQ (CMPB <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETEQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end84a692e769900e3adbfe00718d2169e0
|
|
end84a692e769900e3adbfe00718d2169e0:
|
|
;
|
|
case OpEqPtr:
|
|
// match: (EqPtr x y)
|
|
// cond:
|
|
// result: (SETEQ (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETEQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end6de1d39c9d151e5e503d643bd835356e
|
|
end6de1d39c9d151e5e503d643bd835356e:
|
|
;
|
|
case OpGeq16:
|
|
// match: (Geq16 x y)
|
|
// cond:
|
|
// result: (SETGE (CMPW <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETGE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end26084bf821f9e418934fee812632b774
|
|
end26084bf821f9e418934fee812632b774:
|
|
;
|
|
case OpGeq16U:
|
|
// match: (Geq16U x y)
|
|
// cond:
|
|
// result: (SETAE (CMPW <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETAE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end20b00f850ca834cb2013414645c19ad9
|
|
end20b00f850ca834cb2013414645c19ad9:
|
|
;
|
|
case OpGeq32:
|
|
// match: (Geq32 x y)
|
|
// cond:
|
|
// result: (SETGE (CMPL <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETGE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end713c3dfa0f7247dcc232bcfc916fb044
|
|
end713c3dfa0f7247dcc232bcfc916fb044:
|
|
;
|
|
case OpGeq32U:
|
|
// match: (Geq32U x y)
|
|
// cond:
|
|
// result: (SETAE (CMPL <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETAE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endac2cde17ec6ab0107eabbda6407d1004
|
|
endac2cde17ec6ab0107eabbda6407d1004:
|
|
;
|
|
case OpGeq64:
|
|
// match: (Geq64 x y)
|
|
// cond:
|
|
// result: (SETGE (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETGE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end63f44e3fec8d92723b5bde42d6d7eea0
|
|
end63f44e3fec8d92723b5bde42d6d7eea0:
|
|
;
|
|
case OpGeq64U:
|
|
// match: (Geq64U x y)
|
|
// cond:
|
|
// result: (SETAE (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETAE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endd8d2d9faa19457f6a7b0635a756d234f
|
|
endd8d2d9faa19457f6a7b0635a756d234f:
|
|
;
|
|
case OpGeq8:
|
|
// match: (Geq8 x y)
|
|
// cond:
|
|
// result: (SETGE (CMPB <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETGE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endb5f40ee158007e675b2113c3ce962382
|
|
endb5f40ee158007e675b2113c3ce962382:
|
|
;
|
|
case OpGeq8U:
|
|
// match: (Geq8U x y)
|
|
// cond:
|
|
// result: (SETAE (CMPB <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETAE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endd30ee67afc0284c419cef70261f61452
|
|
endd30ee67afc0284c419cef70261f61452:
|
|
;
|
|
case OpGetG:
|
|
// match: (GetG)
|
|
// cond:
|
|
// result: (LoweredGetG)
|
|
{
|
|
v.Op = OpAMD64LoweredGetG
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
return true
|
|
}
|
|
goto endb17140e71dd641aa4d89e14479160260
|
|
endb17140e71dd641aa4d89e14479160260:
|
|
;
|
|
case OpGreater16:
|
|
// match: (Greater16 x y)
|
|
// cond:
|
|
// result: (SETG (CMPW <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETG
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end5bc9fdb7e563a6b949e42d721903cb58
|
|
end5bc9fdb7e563a6b949e42d721903cb58:
|
|
;
|
|
case OpGreater16U:
|
|
// match: (Greater16U x y)
|
|
// cond:
|
|
// result: (SETA (CMPW <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETA
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endd5b646f04fd839d11082a9ff6adb4a3f
|
|
endd5b646f04fd839d11082a9ff6adb4a3f:
|
|
;
|
|
case OpGreater32:
|
|
// match: (Greater32 x y)
|
|
// cond:
|
|
// result: (SETG (CMPL <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETG
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endbf0b2b1368aadff48969a7386eee5795
|
|
endbf0b2b1368aadff48969a7386eee5795:
|
|
;
|
|
case OpGreater32U:
|
|
// match: (Greater32U x y)
|
|
// cond:
|
|
// result: (SETA (CMPL <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETA
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end033c944272dc0af6fafe33f667cf7485
|
|
end033c944272dc0af6fafe33f667cf7485:
|
|
;
|
|
case OpGreater64:
|
|
// match: (Greater64 x y)
|
|
// cond:
|
|
// result: (SETG (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETG
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endaef0cfa5e27e23cf5e527061cf251069
|
|
endaef0cfa5e27e23cf5e527061cf251069:
|
|
;
|
|
case OpGreater64U:
|
|
// match: (Greater64U x y)
|
|
// cond:
|
|
// result: (SETA (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETA
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end2afc16a19fe1073dfa86770a78eba2b4
|
|
end2afc16a19fe1073dfa86770a78eba2b4:
|
|
;
|
|
case OpGreater8:
|
|
// match: (Greater8 x y)
|
|
// cond:
|
|
// result: (SETG (CMPB <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETG
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endbdb1e5f6b760cf02e0fc2f474622e6be
|
|
endbdb1e5f6b760cf02e0fc2f474622e6be:
|
|
;
|
|
case OpGreater8U:
|
|
// match: (Greater8U x y)
|
|
// cond:
|
|
// result: (SETA (CMPB <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETA
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end22eaafbcfe70447f79d9b3e6cc395bbd
|
|
end22eaafbcfe70447f79d9b3e6cc395bbd:
|
|
;
|
|
case OpITab:
|
|
// match: (ITab (Load ptr mem))
|
|
// cond:
|
|
// result: (MOVQload ptr mem)
|
|
{
|
|
if v.Args[0].Op != OpLoad {
|
|
goto enda49fcae3630a097c78aa58189c90a97a
|
|
}
|
|
ptr := v.Args[0].Args[0]
|
|
mem := v.Args[0].Args[1]
|
|
v.Op = OpAMD64MOVQload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto enda49fcae3630a097c78aa58189c90a97a
|
|
enda49fcae3630a097c78aa58189c90a97a:
|
|
;
|
|
case OpIsInBounds:
|
|
// match: (IsInBounds idx len)
|
|
// cond:
|
|
// result: (SETB (CMPQ <TypeFlags> idx len))
|
|
{
|
|
idx := v.Args[0]
|
|
len := v.Args[1]
|
|
v.Op = OpAMD64SETB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(idx)
|
|
v0.AddArg(len)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endb51d371171154c0f1613b687757e0576
|
|
endb51d371171154c0f1613b687757e0576:
|
|
;
|
|
case OpIsNonNil:
|
|
// match: (IsNonNil p)
|
|
// cond:
|
|
// result: (SETNE (TESTQ <TypeFlags> p p))
|
|
{
|
|
p := v.Args[0]
|
|
v.Op = OpAMD64SETNE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64TESTQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(p)
|
|
v0.AddArg(p)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endff508c3726edfb573abc6128c177e76c
|
|
endff508c3726edfb573abc6128c177e76c:
|
|
;
|
|
case OpLeq16:
|
|
// match: (Leq16 x y)
|
|
// cond:
|
|
// result: (SETLE (CMPW <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETLE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endc1916dfcb3eae58ab237e40a57e1ff16
|
|
endc1916dfcb3eae58ab237e40a57e1ff16:
|
|
;
|
|
case OpLeq16U:
|
|
// match: (Leq16U x y)
|
|
// cond:
|
|
// result: (SETBE (CMPW <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETBE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end627e261aea217b5d17177b52711b8c82
|
|
end627e261aea217b5d17177b52711b8c82:
|
|
;
|
|
case OpLeq32:
|
|
// match: (Leq32 x y)
|
|
// cond:
|
|
// result: (SETLE (CMPL <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETLE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endf422ecc8da0033e22242de9c67112537
|
|
endf422ecc8da0033e22242de9c67112537:
|
|
;
|
|
case OpLeq32U:
|
|
// match: (Leq32U x y)
|
|
// cond:
|
|
// result: (SETBE (CMPL <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETBE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end1b39c9661896abdff8a29de509311b96
|
|
end1b39c9661896abdff8a29de509311b96:
|
|
;
|
|
case OpLeq64:
|
|
// match: (Leq64 x y)
|
|
// cond:
|
|
// result: (SETLE (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETLE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endf03da5e28dccdb4797671f39e824fb10
|
|
endf03da5e28dccdb4797671f39e824fb10:
|
|
;
|
|
case OpLeq64U:
|
|
// match: (Leq64U x y)
|
|
// cond:
|
|
// result: (SETBE (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETBE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end37302777dd91a5d0c6f410a5444ccb38
|
|
end37302777dd91a5d0c6f410a5444ccb38:
|
|
;
|
|
case OpLeq8:
|
|
// match: (Leq8 x y)
|
|
// cond:
|
|
// result: (SETLE (CMPB <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETLE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end03be536eea60fdd98d48b17681acaf5a
|
|
end03be536eea60fdd98d48b17681acaf5a:
|
|
;
|
|
case OpLeq8U:
|
|
// match: (Leq8U x y)
|
|
// cond:
|
|
// result: (SETBE (CMPB <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETBE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end661377f6745450bb1fa7fd0608ef0a86
|
|
end661377f6745450bb1fa7fd0608ef0a86:
|
|
;
|
|
case OpLess16:
|
|
// match: (Less16 x y)
|
|
// cond:
|
|
// result: (SETL (CMPW <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endeb09704ef62ba2695a967b6fcb42e562
|
|
endeb09704ef62ba2695a967b6fcb42e562:
|
|
;
|
|
case OpLess16U:
|
|
// match: (Less16U x y)
|
|
// cond:
|
|
// result: (SETB (CMPW <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end2209a57bd887f68ad732aa7da2bc7286
|
|
end2209a57bd887f68ad732aa7da2bc7286:
|
|
;
|
|
case OpLess32:
|
|
// match: (Less32 x y)
|
|
// cond:
|
|
// result: (SETL (CMPL <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end8da8d2030c0a323a84503c1240c566ae
|
|
end8da8d2030c0a323a84503c1240c566ae:
|
|
;
|
|
case OpLess32U:
|
|
// match: (Less32U x y)
|
|
// cond:
|
|
// result: (SETB (CMPL <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto enddcfbbb482eb194146f4f7c8f12029a7a
|
|
enddcfbbb482eb194146f4f7c8f12029a7a:
|
|
;
|
|
case OpLess64:
|
|
// match: (Less64 x y)
|
|
// cond:
|
|
// result: (SETL (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endf8e7a24c25692045bbcfd2c9356d1a8c
|
|
endf8e7a24c25692045bbcfd2c9356d1a8c:
|
|
;
|
|
case OpLess64U:
|
|
// match: (Less64U x y)
|
|
// cond:
|
|
// result: (SETB (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end2fac0a2c2e972b5e04b5062d5786b87d
|
|
end2fac0a2c2e972b5e04b5062d5786b87d:
|
|
;
|
|
case OpLess8:
|
|
// match: (Less8 x y)
|
|
// cond:
|
|
// result: (SETL (CMPB <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end445ad05f8d23dfecf246ce083f1ea167
|
|
end445ad05f8d23dfecf246ce083f1ea167:
|
|
;
|
|
case OpLess8U:
|
|
// match: (Less8U x y)
|
|
// cond:
|
|
// result: (SETB (CMPB <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end816d1dff858c45836dfa337262e04649
|
|
end816d1dff858c45836dfa337262e04649:
|
|
;
|
|
case OpLoad:
|
|
// match: (Load <t> ptr mem)
|
|
// cond: (is64BitInt(t) || isPtr(t))
|
|
// result: (MOVQload ptr mem)
|
|
{
|
|
t := v.Type
|
|
ptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(is64BitInt(t) || isPtr(t)) {
|
|
goto end7c4c53acf57ebc5f03273652ba1d5934
|
|
}
|
|
v.Op = OpAMD64MOVQload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end7c4c53acf57ebc5f03273652ba1d5934
|
|
end7c4c53acf57ebc5f03273652ba1d5934:
|
|
;
|
|
// match: (Load <t> ptr mem)
|
|
// cond: is32BitInt(t)
|
|
// result: (MOVLload ptr mem)
|
|
{
|
|
t := v.Type
|
|
ptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(is32BitInt(t)) {
|
|
goto ende1cfcb15bfbcfd448ce303d0882a4057
|
|
}
|
|
v.Op = OpAMD64MOVLload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto ende1cfcb15bfbcfd448ce303d0882a4057
|
|
ende1cfcb15bfbcfd448ce303d0882a4057:
|
|
;
|
|
// match: (Load <t> ptr mem)
|
|
// cond: is16BitInt(t)
|
|
// result: (MOVWload ptr mem)
|
|
{
|
|
t := v.Type
|
|
ptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(is16BitInt(t)) {
|
|
goto end2d0a1304501ed9f4e9e2d288505a9c7c
|
|
}
|
|
v.Op = OpAMD64MOVWload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end2d0a1304501ed9f4e9e2d288505a9c7c
|
|
end2d0a1304501ed9f4e9e2d288505a9c7c:
|
|
;
|
|
// match: (Load <t> ptr mem)
|
|
// cond: (t.IsBoolean() || is8BitInt(t))
|
|
// result: (MOVBload ptr mem)
|
|
{
|
|
t := v.Type
|
|
ptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(t.IsBoolean() || is8BitInt(t)) {
|
|
goto end8f83bf72293670e75b22d6627bd13f0b
|
|
}
|
|
v.Op = OpAMD64MOVBload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end8f83bf72293670e75b22d6627bd13f0b
|
|
end8f83bf72293670e75b22d6627bd13f0b:
|
|
;
|
|
case OpLrot16:
|
|
// match: (Lrot16 <t> x [c])
|
|
// cond:
|
|
// result: (ROLWconst <t> [c&15] x)
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
c := v.AuxInt
|
|
v.Op = OpAMD64ROLWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AuxInt = c & 15
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endb23dfa24c619d0068f925899d53ee7fd
|
|
endb23dfa24c619d0068f925899d53ee7fd:
|
|
;
|
|
case OpLrot32:
|
|
// match: (Lrot32 <t> x [c])
|
|
// cond:
|
|
// result: (ROLLconst <t> [c&31] x)
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
c := v.AuxInt
|
|
v.Op = OpAMD64ROLLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AuxInt = c & 31
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end38b2215c011896c36845f72ecb72b1b0
|
|
end38b2215c011896c36845f72ecb72b1b0:
|
|
;
|
|
case OpLrot64:
|
|
// match: (Lrot64 <t> x [c])
|
|
// cond:
|
|
// result: (ROLQconst <t> [c&63] x)
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
c := v.AuxInt
|
|
v.Op = OpAMD64ROLQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AuxInt = c & 63
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end5cb355e4f3ca387f252ef4f6a55f9f68
|
|
end5cb355e4f3ca387f252ef4f6a55f9f68:
|
|
;
|
|
case OpLrot8:
|
|
// match: (Lrot8 <t> x [c])
|
|
// cond:
|
|
// result: (ROLBconst <t> [c&7] x)
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
c := v.AuxInt
|
|
v.Op = OpAMD64ROLBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AuxInt = c & 7
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end26bfb3dd5b537cf13ac9f2978d94ed71
|
|
end26bfb3dd5b537cf13ac9f2978d94ed71:
|
|
;
|
|
case OpLsh16x16:
|
|
// match: (Lsh16x16 <t> x y)
|
|
// cond:
|
|
// result: (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPWconst <TypeFlags> [16] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLW, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 16
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end5b63495f0e75ac68c4ce9d4afa1472d4
|
|
end5b63495f0e75ac68c4ce9d4afa1472d4:
|
|
;
|
|
case OpLsh16x32:
|
|
// match: (Lsh16x32 <t> x y)
|
|
// cond:
|
|
// result: (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPLconst <TypeFlags> [16] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLW, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 16
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end6384dd9bdcec3046732d7347250d49f6
|
|
end6384dd9bdcec3046732d7347250d49f6:
|
|
;
|
|
case OpLsh16x64:
|
|
// match: (Lsh16x64 <t> x y)
|
|
// cond:
|
|
// result: (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPQconst <TypeFlags> [16] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLW, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 16
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end0975ca28988350db0ad556c925d8af07
|
|
end0975ca28988350db0ad556c925d8af07:
|
|
;
|
|
case OpLsh16x8:
|
|
// match: (Lsh16x8 <t> x y)
|
|
// cond:
|
|
// result: (ANDW (SHLW <t> x y) (SBBLcarrymask <t> (CMPBconst <TypeFlags> [16] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLW, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 16
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto endd17c913707f29d59cfcb5d57d5f5c6ff
|
|
endd17c913707f29d59cfcb5d57d5f5c6ff:
|
|
;
|
|
case OpLsh32x16:
|
|
// match: (Lsh32x16 <t> x y)
|
|
// cond:
|
|
// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst <TypeFlags> [32] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLL, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 32
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end027b6f888054cc1dd8911fe16a6315a1
|
|
end027b6f888054cc1dd8911fe16a6315a1:
|
|
;
|
|
case OpLsh32x32:
|
|
// match: (Lsh32x32 <t> x y)
|
|
// cond:
|
|
// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst <TypeFlags> [32] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLL, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 32
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto endbcc31e2bd8800d5ddb27c09d37f867b9
|
|
endbcc31e2bd8800d5ddb27c09d37f867b9:
|
|
;
|
|
case OpLsh32x64:
|
|
// match: (Lsh32x64 <t> x y)
|
|
// cond:
|
|
// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst <TypeFlags> [32] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLL, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 32
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end6797e3a3bbb0fe7eda819fe19a4d4b49
|
|
end6797e3a3bbb0fe7eda819fe19a4d4b49:
|
|
;
|
|
case OpLsh32x8:
|
|
// match: (Lsh32x8 <t> x y)
|
|
// cond:
|
|
// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst <TypeFlags> [32] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLL, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 32
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end7dd2c717933f46750e8a0871aab6fc63
|
|
end7dd2c717933f46750e8a0871aab6fc63:
|
|
;
|
|
case OpLsh64x16:
|
|
// match: (Lsh64x16 <t> x y)
|
|
// cond:
|
|
// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPWconst <TypeFlags> [64] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLQ, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 64
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end3a2fda1dddb29e49f46ccde6f5397222
|
|
end3a2fda1dddb29e49f46ccde6f5397222:
|
|
;
|
|
case OpLsh64x32:
|
|
// match: (Lsh64x32 <t> x y)
|
|
// cond:
|
|
// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPLconst <TypeFlags> [64] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLQ, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 64
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end147322aba732027ac2290fd8173d806a
|
|
end147322aba732027ac2290fd8173d806a:
|
|
;
|
|
case OpLsh64x64:
|
|
// match: (Lsh64x64 <t> x y)
|
|
// cond:
|
|
// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPQconst <TypeFlags> [64] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLQ, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 64
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto endeb8e78c9c960fa12e29ea07a8519649b
|
|
endeb8e78c9c960fa12e29ea07a8519649b:
|
|
;
|
|
case OpLsh64x8:
|
|
// match: (Lsh64x8 <t> x y)
|
|
// cond:
|
|
// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPBconst <TypeFlags> [64] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLQ, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 64
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end42cdc11c34c81bbd5e8b4ad19ceec1ef
|
|
end42cdc11c34c81bbd5e8b4ad19ceec1ef:
|
|
;
|
|
case OpLsh8x16:
|
|
// match: (Lsh8x16 <t> x y)
|
|
// cond:
|
|
// result: (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPWconst <TypeFlags> [8] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLB, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 8
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end60bf962bf5256e20b547e18e3c886aa5
|
|
end60bf962bf5256e20b547e18e3c886aa5:
|
|
;
|
|
case OpLsh8x32:
|
|
// match: (Lsh8x32 <t> x y)
|
|
// cond:
|
|
// result: (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPLconst <TypeFlags> [8] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLB, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 8
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end8ed3445f6dbba1a87c80b140371445ce
|
|
end8ed3445f6dbba1a87c80b140371445ce:
|
|
;
|
|
case OpLsh8x64:
|
|
// match: (Lsh8x64 <t> x y)
|
|
// cond:
|
|
// result: (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPQconst <TypeFlags> [8] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLB, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 8
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end0a03c9cc48ef1bfd74973de5f5fb02b0
|
|
end0a03c9cc48ef1bfd74973de5f5fb02b0:
|
|
;
|
|
case OpLsh8x8:
|
|
// match: (Lsh8x8 <t> x y)
|
|
// cond:
|
|
// result: (ANDB (SHLB <t> x y) (SBBLcarrymask <t> (CMPBconst <TypeFlags> [8] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHLB, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 8
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end781e3a47b186cf99fcb7137afd3432b9
|
|
end781e3a47b186cf99fcb7137afd3432b9:
|
|
;
|
|
case OpAMD64MOVBQSX:
|
|
// match: (MOVBQSX (MOVBload ptr mem))
|
|
// cond:
|
|
// result: (MOVBQSXload ptr mem)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVBload {
|
|
goto enda3a5eeb5767e31f42b0b6c1db8311ebb
|
|
}
|
|
ptr := v.Args[0].Args[0]
|
|
mem := v.Args[0].Args[1]
|
|
v.Op = OpAMD64MOVBQSXload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto enda3a5eeb5767e31f42b0b6c1db8311ebb
|
|
enda3a5eeb5767e31f42b0b6c1db8311ebb:
|
|
;
|
|
case OpAMD64MOVBQZX:
|
|
// match: (MOVBQZX (MOVBload ptr mem))
|
|
// cond:
|
|
// result: (MOVBQZXload ptr mem)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVBload {
|
|
goto end9510a482da21d9945d53c4233b19e825
|
|
}
|
|
ptr := v.Args[0].Args[0]
|
|
mem := v.Args[0].Args[1]
|
|
v.Op = OpAMD64MOVBQZXload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end9510a482da21d9945d53c4233b19e825
|
|
end9510a482da21d9945d53c4233b19e825:
|
|
;
|
|
case OpAMD64MOVBstore:
|
|
// match: (MOVBstore ptr (MOVBQSX x) mem)
|
|
// cond:
|
|
// result: (MOVBstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBQSX {
|
|
goto endc356ef104095b9217b36b594f85171c6
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVBstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endc356ef104095b9217b36b594f85171c6
|
|
endc356ef104095b9217b36b594f85171c6:
|
|
;
|
|
// match: (MOVBstore ptr (MOVBQZX x) mem)
|
|
// cond:
|
|
// result: (MOVBstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBQZX {
|
|
goto end25841a70cce7ac32c6d5e561b992d3df
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVBstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end25841a70cce7ac32c6d5e561b992d3df
|
|
end25841a70cce7ac32c6d5e561b992d3df:
|
|
;
|
|
case OpAMD64MOVLstore:
|
|
// match: (MOVLstore ptr (MOVLQSX x) mem)
|
|
// cond:
|
|
// result: (MOVLstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLQSX {
|
|
goto endf79c699f70cb356abb52dc28f4abf46b
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVLstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endf79c699f70cb356abb52dc28f4abf46b
|
|
endf79c699f70cb356abb52dc28f4abf46b:
|
|
;
|
|
// match: (MOVLstore ptr (MOVLQZX x) mem)
|
|
// cond:
|
|
// result: (MOVLstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLQZX {
|
|
goto end67d1549d16d373e4ad6a89298866d1bc
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVLstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end67d1549d16d373e4ad6a89298866d1bc
|
|
end67d1549d16d373e4ad6a89298866d1bc:
|
|
;
|
|
case OpAMD64MOVQload:
|
|
// match: (MOVQload [off1] (ADDQconst [off2] ptr) mem)
|
|
// cond:
|
|
// result: (MOVQload [addOff(off1, off2)] ptr mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
|
goto end843d29b538c4483b432b632e5666d6e3
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVQload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end843d29b538c4483b432b632e5666d6e3
|
|
end843d29b538c4483b432b632e5666d6e3:
|
|
;
|
|
// match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
|
|
// cond: (sym1 == nil || sym2 == nil)
|
|
// result: (MOVQload [addOff(off1,off2)] {mergeSym(sym1,sym2)} base mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
sym1 := v.Aux
|
|
if v.Args[0].Op != OpAMD64LEAQ {
|
|
goto end227426af95e74caddcf59fdcd30ca8bc
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
sym2 := v.Args[0].Aux
|
|
base := v.Args[0].Args[0]
|
|
mem := v.Args[1]
|
|
if !(sym1 == nil || sym2 == nil) {
|
|
goto end227426af95e74caddcf59fdcd30ca8bc
|
|
}
|
|
v.Op = OpAMD64MOVQload
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.Aux = mergeSym(sym1, sym2)
|
|
v.AddArg(base)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end227426af95e74caddcf59fdcd30ca8bc
|
|
end227426af95e74caddcf59fdcd30ca8bc:
|
|
;
|
|
// match: (MOVQload [off1] (LEAQ8 [off2] ptr idx) mem)
|
|
// cond:
|
|
// result: (MOVQloadidx8 [addOff(off1, off2)] ptr idx mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64LEAQ8 {
|
|
goto end02f5ad148292c46463e7c20d3b821735
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
idx := v.Args[0].Args[1]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVQloadidx8
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(idx)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end02f5ad148292c46463e7c20d3b821735
|
|
end02f5ad148292c46463e7c20d3b821735:
|
|
;
|
|
case OpAMD64MOVQloadidx8:
|
|
// match: (MOVQloadidx8 [off1] (ADDQconst [off2] ptr) idx mem)
|
|
// cond:
|
|
// result: (MOVQloadidx8 [addOff(off1, off2)] ptr idx mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
|
goto ende81e44bcfb11f90916ccb440c590121f
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
idx := v.Args[1]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVQloadidx8
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(idx)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto ende81e44bcfb11f90916ccb440c590121f
|
|
ende81e44bcfb11f90916ccb440c590121f:
|
|
;
|
|
case OpAMD64MOVQstore:
|
|
// match: (MOVQstore [off1] (ADDQconst [off2] ptr) val mem)
|
|
// cond:
|
|
// result: (MOVQstore [addOff(off1, off2)] ptr val mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
|
goto end2108c693a43c79aed10b9246c39c80aa
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVQstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end2108c693a43c79aed10b9246c39c80aa
|
|
end2108c693a43c79aed10b9246c39c80aa:
|
|
;
|
|
// match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
|
|
// cond: (sym1 == nil || sym2 == nil)
|
|
// result: (MOVQstore [addOff(off1,off2)] {mergeSym(sym1,sym2)} base val mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
sym1 := v.Aux
|
|
if v.Args[0].Op != OpAMD64LEAQ {
|
|
goto end5061f48193268a5eb1e1740bdd23c43d
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
sym2 := v.Args[0].Aux
|
|
base := v.Args[0].Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(sym1 == nil || sym2 == nil) {
|
|
goto end5061f48193268a5eb1e1740bdd23c43d
|
|
}
|
|
v.Op = OpAMD64MOVQstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.Aux = mergeSym(sym1, sym2)
|
|
v.AddArg(base)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end5061f48193268a5eb1e1740bdd23c43d
|
|
end5061f48193268a5eb1e1740bdd23c43d:
|
|
;
|
|
// match: (MOVQstore [off1] (LEAQ8 [off2] ptr idx) val mem)
|
|
// cond:
|
|
// result: (MOVQstoreidx8 [addOff(off1, off2)] ptr idx val mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64LEAQ8 {
|
|
goto endce1db8c8d37c8397c500a2068a65c215
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
idx := v.Args[0].Args[1]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVQstoreidx8
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(idx)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endce1db8c8d37c8397c500a2068a65c215
|
|
endce1db8c8d37c8397c500a2068a65c215:
|
|
;
|
|
case OpAMD64MOVQstoreidx8:
|
|
// match: (MOVQstoreidx8 [off1] (ADDQconst [off2] ptr) idx val mem)
|
|
// cond:
|
|
// result: (MOVQstoreidx8 [addOff(off1, off2)] ptr idx val mem)
|
|
{
|
|
off1 := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
|
goto end01c970657b0fdefeab82458c15022163
|
|
}
|
|
off2 := v.Args[0].AuxInt
|
|
ptr := v.Args[0].Args[0]
|
|
idx := v.Args[1]
|
|
val := v.Args[2]
|
|
mem := v.Args[3]
|
|
v.Op = OpAMD64MOVQstoreidx8
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = addOff(off1, off2)
|
|
v.AddArg(ptr)
|
|
v.AddArg(idx)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end01c970657b0fdefeab82458c15022163
|
|
end01c970657b0fdefeab82458c15022163:
|
|
;
|
|
case OpAMD64MOVWstore:
|
|
// match: (MOVWstore ptr (MOVWQSX x) mem)
|
|
// cond:
|
|
// result: (MOVWstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWQSX {
|
|
goto endcc13af07a951a61fcfec3299342f7e1f
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVWstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endcc13af07a951a61fcfec3299342f7e1f
|
|
endcc13af07a951a61fcfec3299342f7e1f:
|
|
;
|
|
// match: (MOVWstore ptr (MOVWQZX x) mem)
|
|
// cond:
|
|
// result: (MOVWstore ptr x mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWQZX {
|
|
goto end4e7df15ee55bdd73d8ecd61b759134d4
|
|
}
|
|
x := v.Args[1].Args[0]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64MOVWstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(x)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end4e7df15ee55bdd73d8ecd61b759134d4
|
|
end4e7df15ee55bdd73d8ecd61b759134d4:
|
|
;
|
|
case OpAMD64MULL:
|
|
// match: (MULL x (MOVLconst [c]))
|
|
// cond:
|
|
// result: (MULLconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLconst {
|
|
goto end893477a261bcad6c2821b77c83075c6c
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64MULLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end893477a261bcad6c2821b77c83075c6c
|
|
end893477a261bcad6c2821b77c83075c6c:
|
|
;
|
|
// match: (MULL (MOVLconst [c]) x)
|
|
// cond:
|
|
// result: (MULLconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto end8a0f957c528a54eecb0dbfc5d96e017a
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64MULLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end8a0f957c528a54eecb0dbfc5d96e017a
|
|
end8a0f957c528a54eecb0dbfc5d96e017a:
|
|
;
|
|
case OpAMD64MULLconst:
|
|
// match: (MULLconst [c] (MOVLconst [d]))
|
|
// cond:
|
|
// result: (MOVLconst [c*d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto endd5732835ed1276ef8b728bcfc1289f73
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c * d
|
|
return true
|
|
}
|
|
goto endd5732835ed1276ef8b728bcfc1289f73
|
|
endd5732835ed1276ef8b728bcfc1289f73:
|
|
;
|
|
case OpAMD64MULQ:
|
|
// match: (MULQ x (MOVQconst [c]))
|
|
// cond: is32Bit(c)
|
|
// result: (MULQconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto endb38c6e3e0ddfa25ba0ef9684ac1528c0
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
if !(is32Bit(c)) {
|
|
goto endb38c6e3e0ddfa25ba0ef9684ac1528c0
|
|
}
|
|
v.Op = OpAMD64MULQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endb38c6e3e0ddfa25ba0ef9684ac1528c0
|
|
endb38c6e3e0ddfa25ba0ef9684ac1528c0:
|
|
;
|
|
// match: (MULQ (MOVQconst [c]) x)
|
|
// cond: is32Bit(c)
|
|
// result: (MULQconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end9cb4f29b0bd7141639416735dcbb3b87
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
if !(is32Bit(c)) {
|
|
goto end9cb4f29b0bd7141639416735dcbb3b87
|
|
}
|
|
v.Op = OpAMD64MULQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end9cb4f29b0bd7141639416735dcbb3b87
|
|
end9cb4f29b0bd7141639416735dcbb3b87:
|
|
;
|
|
case OpAMD64MULQconst:
|
|
// match: (MULQconst [-1] x)
|
|
// cond:
|
|
// result: (NEGQ x)
|
|
{
|
|
if v.AuxInt != -1 {
|
|
goto end82501cca6b5fb121a7f8b197e55f2fec
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NEGQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end82501cca6b5fb121a7f8b197e55f2fec
|
|
end82501cca6b5fb121a7f8b197e55f2fec:
|
|
;
|
|
// match: (MULQconst [0] _)
|
|
// cond:
|
|
// result: (MOVQconst [0])
|
|
{
|
|
if v.AuxInt != 0 {
|
|
goto endcb9faa068e3558ff44daaf1d47d091b5
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto endcb9faa068e3558ff44daaf1d47d091b5
|
|
endcb9faa068e3558ff44daaf1d47d091b5:
|
|
;
|
|
// match: (MULQconst [1] x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
if v.AuxInt != 1 {
|
|
goto end0b527e71db2b288b2841a1f757aa580d
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end0b527e71db2b288b2841a1f757aa580d
|
|
end0b527e71db2b288b2841a1f757aa580d:
|
|
;
|
|
// match: (MULQconst [3] x)
|
|
// cond:
|
|
// result: (LEAQ2 x x)
|
|
{
|
|
if v.AuxInt != 3 {
|
|
goto end34a86f261671b5852bec6c57155fe0da
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64LEAQ2
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end34a86f261671b5852bec6c57155fe0da
|
|
end34a86f261671b5852bec6c57155fe0da:
|
|
;
|
|
// match: (MULQconst [5] x)
|
|
// cond:
|
|
// result: (LEAQ4 x x)
|
|
{
|
|
if v.AuxInt != 5 {
|
|
goto end534601906c45a9171a9fec3e4b82b189
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64LEAQ4
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end534601906c45a9171a9fec3e4b82b189
|
|
end534601906c45a9171a9fec3e4b82b189:
|
|
;
|
|
// match: (MULQconst [9] x)
|
|
// cond:
|
|
// result: (LEAQ8 x x)
|
|
{
|
|
if v.AuxInt != 9 {
|
|
goto end48a2280b6459821289c56073b8354997
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64LEAQ8
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end48a2280b6459821289c56073b8354997
|
|
end48a2280b6459821289c56073b8354997:
|
|
;
|
|
// match: (MULQconst [c] x)
|
|
// cond: isPowerOfTwo(c)
|
|
// result: (SHLQconst [log2(c)] x)
|
|
{
|
|
c := v.AuxInt
|
|
x := v.Args[0]
|
|
if !(isPowerOfTwo(c)) {
|
|
goto end75076953dbfe022526a153eda99b39b2
|
|
}
|
|
v.Op = OpAMD64SHLQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = log2(c)
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end75076953dbfe022526a153eda99b39b2
|
|
end75076953dbfe022526a153eda99b39b2:
|
|
;
|
|
// match: (MULQconst [c] (MOVQconst [d]))
|
|
// cond:
|
|
// result: (MOVQconst [c*d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end55c38c5c405101e610d7ba7fc702ddc0
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c * d
|
|
return true
|
|
}
|
|
goto end55c38c5c405101e610d7ba7fc702ddc0
|
|
end55c38c5c405101e610d7ba7fc702ddc0:
|
|
;
|
|
case OpAMD64MULW:
|
|
// match: (MULW x (MOVWconst [c]))
|
|
// cond:
|
|
// result: (MULWconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWconst {
|
|
goto end542112cc08217d4bdffc1a645d290ffb
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64MULWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end542112cc08217d4bdffc1a645d290ffb
|
|
end542112cc08217d4bdffc1a645d290ffb:
|
|
;
|
|
// match: (MULW (MOVWconst [c]) x)
|
|
// cond:
|
|
// result: (MULWconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto endd97b4245ced2b3d27d8c555b06281de4
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64MULWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endd97b4245ced2b3d27d8c555b06281de4
|
|
endd97b4245ced2b3d27d8c555b06281de4:
|
|
;
|
|
case OpAMD64MULWconst:
|
|
// match: (MULWconst [c] (MOVWconst [d]))
|
|
// cond:
|
|
// result: (MOVWconst [c*d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto end61dbc9d9e93dd6946a20a1f475b3f74b
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c * d
|
|
return true
|
|
}
|
|
goto end61dbc9d9e93dd6946a20a1f475b3f74b
|
|
end61dbc9d9e93dd6946a20a1f475b3f74b:
|
|
;
|
|
case OpMove:
|
|
// match: (Move [size] dst src mem)
|
|
// cond:
|
|
// result: (REPMOVSB dst src (MOVQconst <config.Frontend().TypeUInt64()> [size]) mem)
|
|
{
|
|
size := v.AuxInt
|
|
dst := v.Args[0]
|
|
src := v.Args[1]
|
|
mem := v.Args[2]
|
|
v.Op = OpAMD64REPMOVSB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(dst)
|
|
v.AddArg(src)
|
|
v0 := b.NewValue0(v.Line, OpAMD64MOVQconst, TypeInvalid)
|
|
v0.Type = config.Frontend().TypeUInt64()
|
|
v0.AuxInt = size
|
|
v.AddArg(v0)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end4dd156b33beb9981378c91e46f055a56
|
|
end4dd156b33beb9981378c91e46f055a56:
|
|
;
|
|
case OpMul16:
|
|
// match: (Mul16 x y)
|
|
// cond:
|
|
// result: (MULW x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MULW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end1addf5ea2c885aa1729b8f944859d00c
|
|
end1addf5ea2c885aa1729b8f944859d00c:
|
|
;
|
|
case OpMul32:
|
|
// match: (Mul32 x y)
|
|
// cond:
|
|
// result: (MULL x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MULL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto ende144381f85808e5144782804768e2859
|
|
ende144381f85808e5144782804768e2859:
|
|
;
|
|
case OpMul64:
|
|
// match: (Mul64 x y)
|
|
// cond:
|
|
// result: (MULQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MULQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end38da21e77ac329eb643b20e7d97d5853
|
|
end38da21e77ac329eb643b20e7d97d5853:
|
|
;
|
|
case OpMul8:
|
|
// match: (Mul8 x y)
|
|
// cond:
|
|
// result: (MULW x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MULW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end861428e804347e8489a6424f2e6ce71c
|
|
end861428e804347e8489a6424f2e6ce71c:
|
|
;
|
|
case OpMulPtr:
|
|
// match: (MulPtr x y)
|
|
// cond:
|
|
// result: (MULQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64MULQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto endbbedad106c011a93243e2062afdcc75f
|
|
endbbedad106c011a93243e2062afdcc75f:
|
|
;
|
|
case OpAMD64NEGB:
|
|
// match: (NEGB (MOVBconst [c]))
|
|
// cond:
|
|
// result: (MOVBconst [-c])
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVBconst {
|
|
goto end36d0300ba9eab8c9da86246ff653ca96
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -c
|
|
return true
|
|
}
|
|
goto end36d0300ba9eab8c9da86246ff653ca96
|
|
end36d0300ba9eab8c9da86246ff653ca96:
|
|
;
|
|
case OpAMD64NEGL:
|
|
// match: (NEGL (MOVLconst [c]))
|
|
// cond:
|
|
// result: (MOVLconst [-c])
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto end7a245ec67e56bd51911e5ba2d0aa0a16
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -c
|
|
return true
|
|
}
|
|
goto end7a245ec67e56bd51911e5ba2d0aa0a16
|
|
end7a245ec67e56bd51911e5ba2d0aa0a16:
|
|
;
|
|
case OpAMD64NEGQ:
|
|
// match: (NEGQ (MOVQconst [c]))
|
|
// cond:
|
|
// result: (MOVQconst [-c])
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end04ddd98bc6724ecb85c80c2a4e2bca5a
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -c
|
|
return true
|
|
}
|
|
goto end04ddd98bc6724ecb85c80c2a4e2bca5a
|
|
end04ddd98bc6724ecb85c80c2a4e2bca5a:
|
|
;
|
|
case OpAMD64NEGW:
|
|
// match: (NEGW (MOVWconst [c]))
|
|
// cond:
|
|
// result: (MOVWconst [-c])
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto end1db6636f0a51848d8a34f6561ecfe7ae
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -c
|
|
return true
|
|
}
|
|
goto end1db6636f0a51848d8a34f6561ecfe7ae
|
|
end1db6636f0a51848d8a34f6561ecfe7ae:
|
|
;
|
|
case OpAMD64NOTB:
|
|
// match: (NOTB (MOVBconst [c]))
|
|
// cond:
|
|
// result: (MOVBconst [^c])
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVBconst {
|
|
goto end9e383a9ceb29a9e2bf890ec6a67212a8
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = ^c
|
|
return true
|
|
}
|
|
goto end9e383a9ceb29a9e2bf890ec6a67212a8
|
|
end9e383a9ceb29a9e2bf890ec6a67212a8:
|
|
;
|
|
case OpAMD64NOTL:
|
|
// match: (NOTL (MOVLconst [c]))
|
|
// cond:
|
|
// result: (MOVLconst [^c])
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto endcc73972c088d5e652a1370a96e56502d
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = ^c
|
|
return true
|
|
}
|
|
goto endcc73972c088d5e652a1370a96e56502d
|
|
endcc73972c088d5e652a1370a96e56502d:
|
|
;
|
|
case OpAMD64NOTQ:
|
|
// match: (NOTQ (MOVQconst [c]))
|
|
// cond:
|
|
// result: (MOVQconst [^c])
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto endb39ddb6bf7339d46f74114baad4333b6
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = ^c
|
|
return true
|
|
}
|
|
goto endb39ddb6bf7339d46f74114baad4333b6
|
|
endb39ddb6bf7339d46f74114baad4333b6:
|
|
;
|
|
case OpAMD64NOTW:
|
|
// match: (NOTW (MOVWconst [c]))
|
|
// cond:
|
|
// result: (MOVWconst [^c])
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto end35848095ebcf894c6957ad3be5f82c43
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = ^c
|
|
return true
|
|
}
|
|
goto end35848095ebcf894c6957ad3be5f82c43
|
|
end35848095ebcf894c6957ad3be5f82c43:
|
|
;
|
|
case OpNeg16:
|
|
// match: (Neg16 x)
|
|
// cond:
|
|
// result: (NEGW x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NEGW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end7a8c652f4ffeb49656119af69512edb2
|
|
end7a8c652f4ffeb49656119af69512edb2:
|
|
;
|
|
case OpNeg32:
|
|
// match: (Neg32 x)
|
|
// cond:
|
|
// result: (NEGL x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NEGL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endce1f7e17fc193f6c076e47d5e401e126
|
|
endce1f7e17fc193f6c076e47d5e401e126:
|
|
;
|
|
case OpNeg64:
|
|
// match: (Neg64 x)
|
|
// cond:
|
|
// result: (NEGQ x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NEGQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enda06c5b1718f2b96aba10bf5a5c437c6c
|
|
enda06c5b1718f2b96aba10bf5a5c437c6c:
|
|
;
|
|
case OpNeg8:
|
|
// match: (Neg8 x)
|
|
// cond:
|
|
// result: (NEGB x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64NEGB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end1e5f495a2ac6cdea47b1ae5ba62aa95d
|
|
end1e5f495a2ac6cdea47b1ae5ba62aa95d:
|
|
;
|
|
case OpNeq16:
|
|
// match: (Neq16 x y)
|
|
// cond:
|
|
// result: (SETNE (CMPW <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETNE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPW, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endf177c3b3868606824e43e11da7804572
|
|
endf177c3b3868606824e43e11da7804572:
|
|
;
|
|
case OpNeq32:
|
|
// match: (Neq32 x y)
|
|
// cond:
|
|
// result: (SETNE (CMPL <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETNE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPL, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end39c4bf6d063f8a0b6f0064c96ce25173
|
|
end39c4bf6d063f8a0b6f0064c96ce25173:
|
|
;
|
|
case OpNeq64:
|
|
// match: (Neq64 x y)
|
|
// cond:
|
|
// result: (SETNE (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETNE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end8ab0bcb910c0d3213dd8726fbcc4848e
|
|
end8ab0bcb910c0d3213dd8726fbcc4848e:
|
|
;
|
|
case OpNeq8:
|
|
// match: (Neq8 x y)
|
|
// cond:
|
|
// result: (SETNE (CMPB <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETNE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end4aaff28af59a65b3684f4f1897299932
|
|
end4aaff28af59a65b3684f4f1897299932:
|
|
;
|
|
case OpNeqPtr:
|
|
// match: (NeqPtr x y)
|
|
// cond:
|
|
// result: (SETNE (CMPQ <TypeFlags> x y))
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SETNE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64CMPQ, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end6e180ffd9583cd55361ed3e465158a4c
|
|
end6e180ffd9583cd55361ed3e465158a4c:
|
|
;
|
|
case OpNot:
|
|
// match: (Not x)
|
|
// cond:
|
|
// result: (XORBconst [1] x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64XORBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 1
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end73973101aad60079c62fa64624e21db1
|
|
end73973101aad60079c62fa64624e21db1:
|
|
;
|
|
case OpAMD64ORB:
|
|
// match: (ORB x (MOVBconst [c]))
|
|
// cond:
|
|
// result: (ORBconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBconst {
|
|
goto end7b63870decde2515cb77ec4f8f76817c
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64ORBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end7b63870decde2515cb77ec4f8f76817c
|
|
end7b63870decde2515cb77ec4f8f76817c:
|
|
;
|
|
// match: (ORB (MOVBconst [c]) x)
|
|
// cond:
|
|
// result: (ORBconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVBconst {
|
|
goto end70b43d531e2097a4f6293f66256a642e
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64ORBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end70b43d531e2097a4f6293f66256a642e
|
|
end70b43d531e2097a4f6293f66256a642e:
|
|
;
|
|
// match: (ORB x x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto enddca5ce800a9eca157f243cb2fdb1408a
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enddca5ce800a9eca157f243cb2fdb1408a
|
|
enddca5ce800a9eca157f243cb2fdb1408a:
|
|
;
|
|
case OpAMD64ORBconst:
|
|
// match: (ORBconst [c] x)
|
|
// cond: int8(c)==0
|
|
// result: x
|
|
{
|
|
c := v.AuxInt
|
|
x := v.Args[0]
|
|
if !(int8(c) == 0) {
|
|
goto end565f78e3a843dc73943b59227b39a1b3
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end565f78e3a843dc73943b59227b39a1b3
|
|
end565f78e3a843dc73943b59227b39a1b3:
|
|
;
|
|
// match: (ORBconst [c] _)
|
|
// cond: int8(c)==-1
|
|
// result: (MOVBconst [-1])
|
|
{
|
|
c := v.AuxInt
|
|
if !(int8(c) == -1) {
|
|
goto end6033c7910d8cd536b31446e179e4610d
|
|
}
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto end6033c7910d8cd536b31446e179e4610d
|
|
end6033c7910d8cd536b31446e179e4610d:
|
|
;
|
|
// match: (ORBconst [c] (MOVBconst [d]))
|
|
// cond:
|
|
// result: (MOVBconst [c|d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVBconst {
|
|
goto endbe5263f022dc10a5cf53c118937d79dd
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c | d
|
|
return true
|
|
}
|
|
goto endbe5263f022dc10a5cf53c118937d79dd
|
|
endbe5263f022dc10a5cf53c118937d79dd:
|
|
;
|
|
case OpAMD64ORL:
|
|
// match: (ORL x (MOVLconst [c]))
|
|
// cond:
|
|
// result: (ORLconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLconst {
|
|
goto end1b883e30d860b6fac14ae98462c4f61a
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64ORLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end1b883e30d860b6fac14ae98462c4f61a
|
|
end1b883e30d860b6fac14ae98462c4f61a:
|
|
;
|
|
// match: (ORL (MOVLconst [c]) x)
|
|
// cond:
|
|
// result: (ORLconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto enda5bc49524a0cbd2241f792837d0a48a8
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64ORLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enda5bc49524a0cbd2241f792837d0a48a8
|
|
enda5bc49524a0cbd2241f792837d0a48a8:
|
|
;
|
|
// match: (ORL x x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto end2dd719b68f4938777ef0d820aab93659
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end2dd719b68f4938777ef0d820aab93659
|
|
end2dd719b68f4938777ef0d820aab93659:
|
|
;
|
|
case OpAMD64ORLconst:
|
|
// match: (ORLconst [c] x)
|
|
// cond: int32(c)==0
|
|
// result: x
|
|
{
|
|
c := v.AuxInt
|
|
x := v.Args[0]
|
|
if !(int32(c) == 0) {
|
|
goto end5b52623a724e8a7167c71289fb7192f1
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end5b52623a724e8a7167c71289fb7192f1
|
|
end5b52623a724e8a7167c71289fb7192f1:
|
|
;
|
|
// match: (ORLconst [c] _)
|
|
// cond: int32(c)==-1
|
|
// result: (MOVLconst [-1])
|
|
{
|
|
c := v.AuxInt
|
|
if !(int32(c) == -1) {
|
|
goto end345a8ea439ef2ef54bd84fc8a0f73e97
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto end345a8ea439ef2ef54bd84fc8a0f73e97
|
|
end345a8ea439ef2ef54bd84fc8a0f73e97:
|
|
;
|
|
// match: (ORLconst [c] (MOVLconst [d]))
|
|
// cond:
|
|
// result: (MOVLconst [c|d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto ende9ca05024248f782c88084715f81d727
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c | d
|
|
return true
|
|
}
|
|
goto ende9ca05024248f782c88084715f81d727
|
|
ende9ca05024248f782c88084715f81d727:
|
|
;
|
|
case OpAMD64ORQ:
|
|
// match: (ORQ x (MOVQconst [c]))
|
|
// cond: is32Bit(c)
|
|
// result: (ORQconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end601f2bb3ccda102e484ff60adeaf6d26
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
if !(is32Bit(c)) {
|
|
goto end601f2bb3ccda102e484ff60adeaf6d26
|
|
}
|
|
v.Op = OpAMD64ORQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end601f2bb3ccda102e484ff60adeaf6d26
|
|
end601f2bb3ccda102e484ff60adeaf6d26:
|
|
;
|
|
// match: (ORQ (MOVQconst [c]) x)
|
|
// cond: is32Bit(c)
|
|
// result: (ORQconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end010afbebcd314e288509d79a16a6d5cc
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
if !(is32Bit(c)) {
|
|
goto end010afbebcd314e288509d79a16a6d5cc
|
|
}
|
|
v.Op = OpAMD64ORQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end010afbebcd314e288509d79a16a6d5cc
|
|
end010afbebcd314e288509d79a16a6d5cc:
|
|
;
|
|
// match: (ORQ x x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto end47a27d30b82db576978c5a3a57b520fb
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end47a27d30b82db576978c5a3a57b520fb
|
|
end47a27d30b82db576978c5a3a57b520fb:
|
|
;
|
|
case OpAMD64ORQconst:
|
|
// match: (ORQconst [0] x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
if v.AuxInt != 0 {
|
|
goto end44534da6b9ce98d33fad7e20f0be1fbd
|
|
}
|
|
x := v.Args[0]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end44534da6b9ce98d33fad7e20f0be1fbd
|
|
end44534da6b9ce98d33fad7e20f0be1fbd:
|
|
;
|
|
// match: (ORQconst [-1] _)
|
|
// cond:
|
|
// result: (MOVQconst [-1])
|
|
{
|
|
if v.AuxInt != -1 {
|
|
goto endcde9b9d7c4527eaa5d50b252f50b43c1
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto endcde9b9d7c4527eaa5d50b252f50b43c1
|
|
endcde9b9d7c4527eaa5d50b252f50b43c1:
|
|
;
|
|
// match: (ORQconst [c] (MOVQconst [d]))
|
|
// cond:
|
|
// result: (MOVQconst [c|d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto enda2488509b71db9abcb06a5115c4ddc2c
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c | d
|
|
return true
|
|
}
|
|
goto enda2488509b71db9abcb06a5115c4ddc2c
|
|
enda2488509b71db9abcb06a5115c4ddc2c:
|
|
;
|
|
case OpAMD64ORW:
|
|
// match: (ORW x (MOVWconst [c]))
|
|
// cond:
|
|
// result: (ORWconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWconst {
|
|
goto end9f98df10892dbf170b49aace86ee0d7f
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64ORWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end9f98df10892dbf170b49aace86ee0d7f
|
|
end9f98df10892dbf170b49aace86ee0d7f:
|
|
;
|
|
// match: (ORW (MOVWconst [c]) x)
|
|
// cond:
|
|
// result: (ORWconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto end96405942c9ceb5fcb0ddb85a8709d015
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64ORWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end96405942c9ceb5fcb0ddb85a8709d015
|
|
end96405942c9ceb5fcb0ddb85a8709d015:
|
|
;
|
|
// match: (ORW x x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto endc6a23b64e541dc9cfc6a90fd7028e8c1
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endc6a23b64e541dc9cfc6a90fd7028e8c1
|
|
endc6a23b64e541dc9cfc6a90fd7028e8c1:
|
|
;
|
|
case OpAMD64ORWconst:
|
|
// match: (ORWconst [c] x)
|
|
// cond: int16(c)==0
|
|
// result: x
|
|
{
|
|
c := v.AuxInt
|
|
x := v.Args[0]
|
|
if !(int16(c) == 0) {
|
|
goto endbbbdec9091c8b4c58e587eac8a43402d
|
|
}
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endbbbdec9091c8b4c58e587eac8a43402d
|
|
endbbbdec9091c8b4c58e587eac8a43402d:
|
|
;
|
|
// match: (ORWconst [c] _)
|
|
// cond: int16(c)==-1
|
|
// result: (MOVWconst [-1])
|
|
{
|
|
c := v.AuxInt
|
|
if !(int16(c) == -1) {
|
|
goto ended87a5775f5e04b2d2a117a63d82dd9b
|
|
}
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto ended87a5775f5e04b2d2a117a63d82dd9b
|
|
ended87a5775f5e04b2d2a117a63d82dd9b:
|
|
;
|
|
// match: (ORWconst [c] (MOVWconst [d]))
|
|
// cond:
|
|
// result: (MOVWconst [c|d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto endba9221a8462b5c62e8d7c686f64c2778
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c | d
|
|
return true
|
|
}
|
|
goto endba9221a8462b5c62e8d7c686f64c2778
|
|
endba9221a8462b5c62e8d7c686f64c2778:
|
|
;
|
|
case OpOffPtr:
|
|
// match: (OffPtr [off] ptr)
|
|
// cond:
|
|
// result: (ADDQconst [off] ptr)
|
|
{
|
|
off := v.AuxInt
|
|
ptr := v.Args[0]
|
|
v.Op = OpAMD64ADDQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = off
|
|
v.AddArg(ptr)
|
|
return true
|
|
}
|
|
goto end0429f947ee7ac49ff45a243e461a5290
|
|
end0429f947ee7ac49ff45a243e461a5290:
|
|
;
|
|
case OpOr16:
|
|
// match: (Or16 x y)
|
|
// cond:
|
|
// result: (ORW x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ORW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end8fedf2c79d5607b7056b0ff015199cbd
|
|
end8fedf2c79d5607b7056b0ff015199cbd:
|
|
;
|
|
case OpOr32:
|
|
// match: (Or32 x y)
|
|
// cond:
|
|
// result: (ORL x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ORL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto endea45bed9ca97d2995b68b53e6012d384
|
|
endea45bed9ca97d2995b68b53e6012d384:
|
|
;
|
|
case OpOr64:
|
|
// match: (Or64 x y)
|
|
// cond:
|
|
// result: (ORQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ORQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end3a446becaf2461f4f1a41faeef313f41
|
|
end3a446becaf2461f4f1a41faeef313f41:
|
|
;
|
|
case OpOr8:
|
|
// match: (Or8 x y)
|
|
// cond:
|
|
// result: (ORB x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ORB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end6f8a8c559a167d1f0a5901d09a1fb248
|
|
end6f8a8c559a167d1f0a5901d09a1fb248:
|
|
;
|
|
case OpPanicNilCheck:
|
|
// match: (PanicNilCheck ptr mem)
|
|
// cond:
|
|
// result: (LoweredPanicNilCheck ptr mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64LoweredPanicNilCheck
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto enda02b1ad5a6f929b782190145f2c8628b
|
|
enda02b1ad5a6f929b782190145f2c8628b:
|
|
;
|
|
case OpRsh16Ux16:
|
|
// match: (Rsh16Ux16 <t> x y)
|
|
// cond:
|
|
// result: (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPWconst <TypeFlags> [16] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRW, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 16
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end73239750a306668023d2c49875ac442f
|
|
end73239750a306668023d2c49875ac442f:
|
|
;
|
|
case OpRsh16Ux32:
|
|
// match: (Rsh16Ux32 <t> x y)
|
|
// cond:
|
|
// result: (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPLconst <TypeFlags> [16] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRW, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 16
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end9951e3b2e92c892256feece722b32219
|
|
end9951e3b2e92c892256feece722b32219:
|
|
;
|
|
case OpRsh16Ux64:
|
|
// match: (Rsh16Ux64 <t> x y)
|
|
// cond:
|
|
// result: (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPQconst <TypeFlags> [16] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRW, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 16
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end610d56d808c204abfa40d653447b2c17
|
|
end610d56d808c204abfa40d653447b2c17:
|
|
;
|
|
case OpRsh16Ux8:
|
|
// match: (Rsh16Ux8 <t> x y)
|
|
// cond:
|
|
// result: (ANDW (SHRW <t> x y) (SBBLcarrymask <t> (CMPBconst <TypeFlags> [16] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRW, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 16
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end45e76a8d2b004e6802d53cf12b4757b3
|
|
end45e76a8d2b004e6802d53cf12b4757b3:
|
|
;
|
|
case OpRsh16x16:
|
|
// match: (Rsh16x16 <t> x y)
|
|
// cond:
|
|
// result: (SARW <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst <TypeFlags> [16] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORW, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 16
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endbcd8fd69ada08517f6f94f35da91e1c3
|
|
endbcd8fd69ada08517f6f94f35da91e1c3:
|
|
;
|
|
case OpRsh16x32:
|
|
// match: (Rsh16x32 <t> x y)
|
|
// cond:
|
|
// result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst <TypeFlags> [16] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORL, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 16
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endec3994083e7f82857ecec05906c29aa6
|
|
endec3994083e7f82857ecec05906c29aa6:
|
|
;
|
|
case OpRsh16x64:
|
|
// match: (Rsh16x64 <t> x y)
|
|
// cond:
|
|
// result: (SARW <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst <TypeFlags> [16] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORQ, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTQ, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 16
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end19da3883e21ffa3a45d7fc648ef38b66
|
|
end19da3883e21ffa3a45d7fc648ef38b66:
|
|
;
|
|
case OpRsh16x8:
|
|
// match: (Rsh16x8 <t> x y)
|
|
// cond:
|
|
// result: (SARW <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst <TypeFlags> [16] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORB, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 16
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end3c989f6931d059ea04e4ba93601b6c51
|
|
end3c989f6931d059ea04e4ba93601b6c51:
|
|
;
|
|
case OpRsh32Ux16:
|
|
// match: (Rsh32Ux16 <t> x y)
|
|
// cond:
|
|
// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPWconst <TypeFlags> [32] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRL, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 32
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end056ede9885a9fc2f32615a2a03b35388
|
|
end056ede9885a9fc2f32615a2a03b35388:
|
|
;
|
|
case OpRsh32Ux32:
|
|
// match: (Rsh32Ux32 <t> x y)
|
|
// cond:
|
|
// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPLconst <TypeFlags> [32] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRL, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 32
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end30439bdc3517479ea25ae7f54408ba7f
|
|
end30439bdc3517479ea25ae7f54408ba7f:
|
|
;
|
|
case OpRsh32Ux64:
|
|
// match: (Rsh32Ux64 <t> x y)
|
|
// cond:
|
|
// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPQconst <TypeFlags> [32] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRL, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 32
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end49b47fd18b54461d8eea51f6e5889cd2
|
|
end49b47fd18b54461d8eea51f6e5889cd2:
|
|
;
|
|
case OpRsh32Ux8:
|
|
// match: (Rsh32Ux8 <t> x y)
|
|
// cond:
|
|
// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPBconst <TypeFlags> [32] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRL, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 32
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end46e045970a8b1afb9035605fc0e50c69
|
|
end46e045970a8b1afb9035605fc0e50c69:
|
|
;
|
|
case OpRsh32x16:
|
|
// match: (Rsh32x16 <t> x y)
|
|
// cond:
|
|
// result: (SARL <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst <TypeFlags> [32] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORW, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 32
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end5d1b8d7e1d1e53e621d13bb0eafc9102
|
|
end5d1b8d7e1d1e53e621d13bb0eafc9102:
|
|
;
|
|
case OpRsh32x32:
|
|
// match: (Rsh32x32 <t> x y)
|
|
// cond:
|
|
// result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst <TypeFlags> [32] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORL, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 32
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end9c27383961c2161a9955012fce808cab
|
|
end9c27383961c2161a9955012fce808cab:
|
|
;
|
|
case OpRsh32x64:
|
|
// match: (Rsh32x64 <t> x y)
|
|
// cond:
|
|
// result: (SARL <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst <TypeFlags> [32] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORQ, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTQ, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 32
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end75dc7144497705c800e0c60dcd4a2828
|
|
end75dc7144497705c800e0c60dcd4a2828:
|
|
;
|
|
case OpRsh32x8:
|
|
// match: (Rsh32x8 <t> x y)
|
|
// cond:
|
|
// result: (SARL <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst <TypeFlags> [32] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORB, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 32
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto enda7b94b2fd5cbcd12bb2dcd576bdca481
|
|
enda7b94b2fd5cbcd12bb2dcd576bdca481:
|
|
;
|
|
case OpRsh64Ux16:
|
|
// match: (Rsh64Ux16 <t> x y)
|
|
// cond:
|
|
// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPWconst <TypeFlags> [64] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRQ, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 64
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto endc4bdfdc375a5c94978d936bd0db89cc5
|
|
endc4bdfdc375a5c94978d936bd0db89cc5:
|
|
;
|
|
case OpRsh64Ux32:
|
|
// match: (Rsh64Ux32 <t> x y)
|
|
// cond:
|
|
// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPLconst <TypeFlags> [64] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRQ, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 64
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end217f32bca5f6744b9a7de052f4fae13e
|
|
end217f32bca5f6744b9a7de052f4fae13e:
|
|
;
|
|
case OpRsh64Ux64:
|
|
// match: (Rsh64Ux64 <t> x y)
|
|
// cond:
|
|
// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPQconst <TypeFlags> [64] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRQ, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 64
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end530dee0bcadf1cf5d092894b6210ffcd
|
|
end530dee0bcadf1cf5d092894b6210ffcd:
|
|
;
|
|
case OpRsh64Ux8:
|
|
// match: (Rsh64Ux8 <t> x y)
|
|
// cond:
|
|
// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPBconst <TypeFlags> [64] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRQ, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 64
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto endf09baf4e0005c5eb4905f71ce4c8b306
|
|
endf09baf4e0005c5eb4905f71ce4c8b306:
|
|
;
|
|
case OpRsh64x16:
|
|
// match: (Rsh64x16 <t> x y)
|
|
// cond:
|
|
// result: (SARQ <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst <TypeFlags> [64] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORW, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 64
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endb370ee74ca256a604138321ddca9d543
|
|
endb370ee74ca256a604138321ddca9d543:
|
|
;
|
|
case OpRsh64x32:
|
|
// match: (Rsh64x32 <t> x y)
|
|
// cond:
|
|
// result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst <TypeFlags> [64] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORL, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 64
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end3cc6edf5b286a449332757ea12d2d601
|
|
end3cc6edf5b286a449332757ea12d2d601:
|
|
;
|
|
case OpRsh64x64:
|
|
// match: (Rsh64x64 <t> x y)
|
|
// cond:
|
|
// result: (SARQ <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst <TypeFlags> [64] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORQ, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTQ, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 64
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end45de7b33396d9fd2ba377bd095f1d7a6
|
|
end45de7b33396d9fd2ba377bd095f1d7a6:
|
|
;
|
|
case OpRsh64x8:
|
|
// match: (Rsh64x8 <t> x y)
|
|
// cond:
|
|
// result: (SARQ <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst <TypeFlags> [64] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORB, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 64
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto ende03fa68104fd18bb9b2bb94370e0c8b3
|
|
ende03fa68104fd18bb9b2bb94370e0c8b3:
|
|
;
|
|
case OpRsh8Ux16:
|
|
// match: (Rsh8Ux16 <t> x y)
|
|
// cond:
|
|
// result: (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPWconst <TypeFlags> [8] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRB, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 8
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto enda1adfc560334e10d5e83fbff27a8752f
|
|
enda1adfc560334e10d5e83fbff27a8752f:
|
|
;
|
|
case OpRsh8Ux32:
|
|
// match: (Rsh8Ux32 <t> x y)
|
|
// cond:
|
|
// result: (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPLconst <TypeFlags> [8] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRB, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 8
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end17f63b4b712e715a33ac780193b59c2e
|
|
end17f63b4b712e715a33ac780193b59c2e:
|
|
;
|
|
case OpRsh8Ux64:
|
|
// match: (Rsh8Ux64 <t> x y)
|
|
// cond:
|
|
// result: (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPQconst <TypeFlags> [8] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRB, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 8
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end77d5c3ef9982ebd27c135d3461b7430b
|
|
end77d5c3ef9982ebd27c135d3461b7430b:
|
|
;
|
|
case OpRsh8Ux8:
|
|
// match: (Rsh8Ux8 <t> x y)
|
|
// cond:
|
|
// result: (ANDB (SHRB <t> x y) (SBBLcarrymask <t> (CMPBconst <TypeFlags> [8] y)))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64ANDB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SHRB, TypeInvalid)
|
|
v0.Type = t
|
|
v0.AddArg(x)
|
|
v0.AddArg(y)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v1.Type = t
|
|
v2 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v2.Type = TypeFlags
|
|
v2.AuxInt = 8
|
|
v2.AddArg(y)
|
|
v1.AddArg(v2)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end206712ffbda924142afbf384aeb8f09e
|
|
end206712ffbda924142afbf384aeb8f09e:
|
|
;
|
|
case OpRsh8x16:
|
|
// match: (Rsh8x16 <t> x y)
|
|
// cond:
|
|
// result: (SARB <t> x (ORW <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst <TypeFlags> [8] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORW, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPWconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 8
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endd303f390b49d9716dc783d5c4d57ddd1
|
|
endd303f390b49d9716dc783d5c4d57ddd1:
|
|
;
|
|
case OpRsh8x32:
|
|
// match: (Rsh8x32 <t> x y)
|
|
// cond:
|
|
// result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst <TypeFlags> [8] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORL, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPLconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 8
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto ende12a524a6fc68eb245140c6919034337
|
|
ende12a524a6fc68eb245140c6919034337:
|
|
;
|
|
case OpRsh8x64:
|
|
// match: (Rsh8x64 <t> x y)
|
|
// cond:
|
|
// result: (SARB <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst <TypeFlags> [8] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORQ, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTQ, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBQcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPQconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 8
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end6ee53459daa5458d163c86ea02dd2f31
|
|
end6ee53459daa5458d163c86ea02dd2f31:
|
|
;
|
|
case OpRsh8x8:
|
|
// match: (Rsh8x8 <t> x y)
|
|
// cond:
|
|
// result: (SARB <t> x (ORB <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst <TypeFlags> [8] y)))))
|
|
{
|
|
t := v.Type
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SARB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = t
|
|
v.AddArg(x)
|
|
v0 := b.NewValue0(v.Line, OpAMD64ORB, TypeInvalid)
|
|
v0.Type = y.Type
|
|
v0.AddArg(y)
|
|
v1 := b.NewValue0(v.Line, OpAMD64NOTL, TypeInvalid)
|
|
v1.Type = y.Type
|
|
v2 := b.NewValue0(v.Line, OpAMD64SBBLcarrymask, TypeInvalid)
|
|
v2.Type = y.Type
|
|
v3 := b.NewValue0(v.Line, OpAMD64CMPBconst, TypeInvalid)
|
|
v3.Type = TypeFlags
|
|
v3.AuxInt = 8
|
|
v3.AddArg(y)
|
|
v2.AddArg(v3)
|
|
v1.AddArg(v2)
|
|
v0.AddArg(v1)
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end07f447a7e25b048c41d412c242330ec0
|
|
end07f447a7e25b048c41d412c242330ec0:
|
|
;
|
|
case OpAMD64SARB:
|
|
// match: (SARB x (MOVBconst [c]))
|
|
// cond:
|
|
// result: (SARBconst [c&31] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBconst {
|
|
goto end3bf3d17717aa6c04462e56d1c87902ce
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SARBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 31
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end3bf3d17717aa6c04462e56d1c87902ce
|
|
end3bf3d17717aa6c04462e56d1c87902ce:
|
|
;
|
|
case OpAMD64SARL:
|
|
// match: (SARL x (MOVLconst [c]))
|
|
// cond:
|
|
// result: (SARLconst [c&31] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLconst {
|
|
goto ende586a72c1b232ee0b63e37c71eeb8470
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SARLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 31
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto ende586a72c1b232ee0b63e37c71eeb8470
|
|
ende586a72c1b232ee0b63e37c71eeb8470:
|
|
;
|
|
case OpAMD64SARQ:
|
|
// match: (SARQ x (MOVQconst [c]))
|
|
// cond:
|
|
// result: (SARQconst [c&63] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end25e720ab203be2745dded5550e6d8a7c
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SARQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 63
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end25e720ab203be2745dded5550e6d8a7c
|
|
end25e720ab203be2745dded5550e6d8a7c:
|
|
;
|
|
case OpAMD64SARW:
|
|
// match: (SARW x (MOVWconst [c]))
|
|
// cond:
|
|
// result: (SARWconst [c&31] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWconst {
|
|
goto endc46e3f211f94238f9a0aec3c498af490
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SARWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 31
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endc46e3f211f94238f9a0aec3c498af490
|
|
endc46e3f211f94238f9a0aec3c498af490:
|
|
;
|
|
case OpAMD64SBBLcarrymask:
|
|
// match: (SBBLcarrymask (CMPQconst [c] (MOVQconst [d])))
|
|
// cond: inBounds(d, c)
|
|
// result: (MOVLconst [-1])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPQconst {
|
|
goto enda9e02a887246381d02b3259b9df4050c
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVQconst {
|
|
goto enda9e02a887246381d02b3259b9df4050c
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(inBounds(d, c)) {
|
|
goto enda9e02a887246381d02b3259b9df4050c
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto enda9e02a887246381d02b3259b9df4050c
|
|
enda9e02a887246381d02b3259b9df4050c:
|
|
;
|
|
// match: (SBBLcarrymask (CMPQconst [c] (MOVQconst [d])))
|
|
// cond: !inBounds(d, c)
|
|
// result: (MOVLconst [0])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPQconst {
|
|
goto end3f8220527278b72a64148fcf9dc58bfe
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVQconst {
|
|
goto end3f8220527278b72a64148fcf9dc58bfe
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(!inBounds(d, c)) {
|
|
goto end3f8220527278b72a64148fcf9dc58bfe
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end3f8220527278b72a64148fcf9dc58bfe
|
|
end3f8220527278b72a64148fcf9dc58bfe:
|
|
;
|
|
// match: (SBBLcarrymask (CMPLconst [c] (MOVLconst [d])))
|
|
// cond: inBounds(int64(int32(d)), int64(int32(c)))
|
|
// result: (MOVLconst [-1])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPLconst {
|
|
goto end880a2b9a12ed4f551bbd46473b9439bc
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVLconst {
|
|
goto end880a2b9a12ed4f551bbd46473b9439bc
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(inBounds(int64(int32(d)), int64(int32(c)))) {
|
|
goto end880a2b9a12ed4f551bbd46473b9439bc
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto end880a2b9a12ed4f551bbd46473b9439bc
|
|
end880a2b9a12ed4f551bbd46473b9439bc:
|
|
;
|
|
// match: (SBBLcarrymask (CMPLconst [c] (MOVLconst [d])))
|
|
// cond: !inBounds(int64(int32(d)), int64(int32(c)))
|
|
// result: (MOVLconst [0])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPLconst {
|
|
goto end3f08080e0f55d51afca2a131ed0c672e
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVLconst {
|
|
goto end3f08080e0f55d51afca2a131ed0c672e
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(!inBounds(int64(int32(d)), int64(int32(c)))) {
|
|
goto end3f08080e0f55d51afca2a131ed0c672e
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end3f08080e0f55d51afca2a131ed0c672e
|
|
end3f08080e0f55d51afca2a131ed0c672e:
|
|
;
|
|
// match: (SBBLcarrymask (CMPWconst [c] (MOVWconst [d])))
|
|
// cond: inBounds(int64(int16(d)), int64(int16(c)))
|
|
// result: (MOVLconst [-1])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPWconst {
|
|
goto end91ed02166e0c0d696730e1704d0a682e
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVWconst {
|
|
goto end91ed02166e0c0d696730e1704d0a682e
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(inBounds(int64(int16(d)), int64(int16(c)))) {
|
|
goto end91ed02166e0c0d696730e1704d0a682e
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto end91ed02166e0c0d696730e1704d0a682e
|
|
end91ed02166e0c0d696730e1704d0a682e:
|
|
;
|
|
// match: (SBBLcarrymask (CMPWconst [c] (MOVWconst [d])))
|
|
// cond: !inBounds(int64(int16(d)), int64(int16(c)))
|
|
// result: (MOVLconst [0])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPWconst {
|
|
goto endc7edc3a13ec73ec4e6e87e7ab421a71a
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVWconst {
|
|
goto endc7edc3a13ec73ec4e6e87e7ab421a71a
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(!inBounds(int64(int16(d)), int64(int16(c)))) {
|
|
goto endc7edc3a13ec73ec4e6e87e7ab421a71a
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto endc7edc3a13ec73ec4e6e87e7ab421a71a
|
|
endc7edc3a13ec73ec4e6e87e7ab421a71a:
|
|
;
|
|
// match: (SBBLcarrymask (CMPBconst [c] (MOVBconst [d])))
|
|
// cond: inBounds(int64(int8(d)), int64(int8(c)))
|
|
// result: (MOVLconst [-1])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPBconst {
|
|
goto end0fe2997fc76ce00b1d496f7289ab345a
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVBconst {
|
|
goto end0fe2997fc76ce00b1d496f7289ab345a
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(inBounds(int64(int8(d)), int64(int8(c)))) {
|
|
goto end0fe2997fc76ce00b1d496f7289ab345a
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto end0fe2997fc76ce00b1d496f7289ab345a
|
|
end0fe2997fc76ce00b1d496f7289ab345a:
|
|
;
|
|
// match: (SBBLcarrymask (CMPBconst [c] (MOVBconst [d])))
|
|
// cond: !inBounds(int64(int8(d)), int64(int8(c)))
|
|
// result: (MOVLconst [0])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPBconst {
|
|
goto end3a07121fcc82f1a19da4226b07a757ce
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVBconst {
|
|
goto end3a07121fcc82f1a19da4226b07a757ce
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(!inBounds(int64(int8(d)), int64(int8(c)))) {
|
|
goto end3a07121fcc82f1a19da4226b07a757ce
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end3a07121fcc82f1a19da4226b07a757ce
|
|
end3a07121fcc82f1a19da4226b07a757ce:
|
|
;
|
|
case OpAMD64SBBQcarrymask:
|
|
// match: (SBBQcarrymask (CMPQconst [c] (MOVQconst [d])))
|
|
// cond: inBounds(d, c)
|
|
// result: (MOVQconst [-1])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPQconst {
|
|
goto end378de7e659770f877c08b6b269073069
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVQconst {
|
|
goto end378de7e659770f877c08b6b269073069
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(inBounds(d, c)) {
|
|
goto end378de7e659770f877c08b6b269073069
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto end378de7e659770f877c08b6b269073069
|
|
end378de7e659770f877c08b6b269073069:
|
|
;
|
|
// match: (SBBQcarrymask (CMPQconst [c] (MOVQconst [d])))
|
|
// cond: !inBounds(d, c)
|
|
// result: (MOVQconst [0])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPQconst {
|
|
goto enda7bfd1974bf83ca79653c560a718a86c
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVQconst {
|
|
goto enda7bfd1974bf83ca79653c560a718a86c
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(!inBounds(d, c)) {
|
|
goto enda7bfd1974bf83ca79653c560a718a86c
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto enda7bfd1974bf83ca79653c560a718a86c
|
|
enda7bfd1974bf83ca79653c560a718a86c:
|
|
;
|
|
// match: (SBBQcarrymask (CMPLconst [c] (MOVLconst [d])))
|
|
// cond: inBounds(int64(int32(d)), int64(int32(c)))
|
|
// result: (MOVQconst [-1])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPLconst {
|
|
goto end8c6d39847239120fa0fe953007eb40ae
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVLconst {
|
|
goto end8c6d39847239120fa0fe953007eb40ae
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(inBounds(int64(int32(d)), int64(int32(c)))) {
|
|
goto end8c6d39847239120fa0fe953007eb40ae
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto end8c6d39847239120fa0fe953007eb40ae
|
|
end8c6d39847239120fa0fe953007eb40ae:
|
|
;
|
|
// match: (SBBQcarrymask (CMPLconst [c] (MOVLconst [d])))
|
|
// cond: !inBounds(int64(int32(d)), int64(int32(c)))
|
|
// result: (MOVQconst [0])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPLconst {
|
|
goto end20885e855545e16ca77af2b9a2b69ea9
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVLconst {
|
|
goto end20885e855545e16ca77af2b9a2b69ea9
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(!inBounds(int64(int32(d)), int64(int32(c)))) {
|
|
goto end20885e855545e16ca77af2b9a2b69ea9
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end20885e855545e16ca77af2b9a2b69ea9
|
|
end20885e855545e16ca77af2b9a2b69ea9:
|
|
;
|
|
// match: (SBBQcarrymask (CMPWconst [c] (MOVWconst [d])))
|
|
// cond: inBounds(int64(int16(d)), int64(int16(c)))
|
|
// result: (MOVQconst [-1])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPWconst {
|
|
goto end16f61db69d07e67e9f408c2790a9de7c
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVWconst {
|
|
goto end16f61db69d07e67e9f408c2790a9de7c
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(inBounds(int64(int16(d)), int64(int16(c)))) {
|
|
goto end16f61db69d07e67e9f408c2790a9de7c
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto end16f61db69d07e67e9f408c2790a9de7c
|
|
end16f61db69d07e67e9f408c2790a9de7c:
|
|
;
|
|
// match: (SBBQcarrymask (CMPWconst [c] (MOVWconst [d])))
|
|
// cond: !inBounds(int64(int16(d)), int64(int16(c)))
|
|
// result: (MOVQconst [0])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPWconst {
|
|
goto end191ca427f7d5d2286bd290920c84a51d
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVWconst {
|
|
goto end191ca427f7d5d2286bd290920c84a51d
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(!inBounds(int64(int16(d)), int64(int16(c)))) {
|
|
goto end191ca427f7d5d2286bd290920c84a51d
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end191ca427f7d5d2286bd290920c84a51d
|
|
end191ca427f7d5d2286bd290920c84a51d:
|
|
;
|
|
// match: (SBBQcarrymask (CMPBconst [c] (MOVBconst [d])))
|
|
// cond: inBounds(int64(int8(d)), int64(int8(c)))
|
|
// result: (MOVQconst [-1])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPBconst {
|
|
goto end3fd3f1e9660b9050c6a41b4fc948f793
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVBconst {
|
|
goto end3fd3f1e9660b9050c6a41b4fc948f793
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(inBounds(int64(int8(d)), int64(int8(c)))) {
|
|
goto end3fd3f1e9660b9050c6a41b4fc948f793
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = -1
|
|
return true
|
|
}
|
|
goto end3fd3f1e9660b9050c6a41b4fc948f793
|
|
end3fd3f1e9660b9050c6a41b4fc948f793:
|
|
;
|
|
// match: (SBBQcarrymask (CMPBconst [c] (MOVBconst [d])))
|
|
// cond: !inBounds(int64(int8(d)), int64(int8(c)))
|
|
// result: (MOVQconst [0])
|
|
{
|
|
if v.Args[0].Op != OpAMD64CMPBconst {
|
|
goto ende0d6edd92ae98e6dc041f65029d8b243
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
if v.Args[0].Args[0].Op != OpAMD64MOVBconst {
|
|
goto ende0d6edd92ae98e6dc041f65029d8b243
|
|
}
|
|
d := v.Args[0].Args[0].AuxInt
|
|
if !(!inBounds(int64(int8(d)), int64(int8(c)))) {
|
|
goto ende0d6edd92ae98e6dc041f65029d8b243
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto ende0d6edd92ae98e6dc041f65029d8b243
|
|
ende0d6edd92ae98e6dc041f65029d8b243:
|
|
;
|
|
case OpAMD64SETA:
|
|
// match: (SETA (InvertFlags x))
|
|
// cond:
|
|
// result: (SETB x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto enda4ac36e94fc279d762b5a6c7c6cc665d
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enda4ac36e94fc279d762b5a6c7c6cc665d
|
|
enda4ac36e94fc279d762b5a6c7c6cc665d:
|
|
;
|
|
case OpAMD64SETAE:
|
|
// match: (SETAE (InvertFlags x))
|
|
// cond:
|
|
// result: (SETBE x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto end0468f5be6caf682fdea6b91d6648991e
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETBE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end0468f5be6caf682fdea6b91d6648991e
|
|
end0468f5be6caf682fdea6b91d6648991e:
|
|
;
|
|
case OpAMD64SETB:
|
|
// match: (SETB (InvertFlags x))
|
|
// cond:
|
|
// result: (SETA x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto endc9eba7aa1e54a228570d2f5cc96f3565
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETA
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endc9eba7aa1e54a228570d2f5cc96f3565
|
|
endc9eba7aa1e54a228570d2f5cc96f3565:
|
|
;
|
|
case OpAMD64SETBE:
|
|
// match: (SETBE (InvertFlags x))
|
|
// cond:
|
|
// result: (SETAE x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto end9d9031643469798b14b8cad1f5a7a1ba
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETAE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end9d9031643469798b14b8cad1f5a7a1ba
|
|
end9d9031643469798b14b8cad1f5a7a1ba:
|
|
;
|
|
case OpAMD64SETEQ:
|
|
// match: (SETEQ (InvertFlags x))
|
|
// cond:
|
|
// result: (SETEQ x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto end5d2039c9368d8c0cfba23b5a85b459e1
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETEQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end5d2039c9368d8c0cfba23b5a85b459e1
|
|
end5d2039c9368d8c0cfba23b5a85b459e1:
|
|
;
|
|
case OpAMD64SETG:
|
|
// match: (SETG (InvertFlags x))
|
|
// cond:
|
|
// result: (SETL x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto endf7586738694c9cd0b74ae28bbadb649f
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endf7586738694c9cd0b74ae28bbadb649f
|
|
endf7586738694c9cd0b74ae28bbadb649f:
|
|
;
|
|
case OpAMD64SETGE:
|
|
// match: (SETGE (InvertFlags x))
|
|
// cond:
|
|
// result: (SETLE x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto end82c11eff6f842159f564f2dad3d2eedc
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETLE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end82c11eff6f842159f564f2dad3d2eedc
|
|
end82c11eff6f842159f564f2dad3d2eedc:
|
|
;
|
|
case OpAMD64SETL:
|
|
// match: (SETL (InvertFlags x))
|
|
// cond:
|
|
// result: (SETG x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto ende33160cd86b9d4d3b77e02fb4658d5d3
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETG
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto ende33160cd86b9d4d3b77e02fb4658d5d3
|
|
ende33160cd86b9d4d3b77e02fb4658d5d3:
|
|
;
|
|
case OpAMD64SETLE:
|
|
// match: (SETLE (InvertFlags x))
|
|
// cond:
|
|
// result: (SETGE x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto end9307d96753efbeb888d1c98a6aba7a29
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETGE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end9307d96753efbeb888d1c98a6aba7a29
|
|
end9307d96753efbeb888d1c98a6aba7a29:
|
|
;
|
|
case OpAMD64SETNE:
|
|
// match: (SETNE (InvertFlags x))
|
|
// cond:
|
|
// result: (SETNE x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
|
goto endbc71811b789475308014550f638026eb
|
|
}
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64SETNE
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endbc71811b789475308014550f638026eb
|
|
endbc71811b789475308014550f638026eb:
|
|
;
|
|
case OpAMD64SHLB:
|
|
// match: (SHLB x (MOVBconst [c]))
|
|
// cond:
|
|
// result: (SHLBconst [c&31] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBconst {
|
|
goto end2d0d0111d831d8a575b5627284a6337a
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SHLBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 31
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end2d0d0111d831d8a575b5627284a6337a
|
|
end2d0d0111d831d8a575b5627284a6337a:
|
|
;
|
|
case OpAMD64SHLL:
|
|
// match: (SHLL x (MOVLconst [c]))
|
|
// cond:
|
|
// result: (SHLLconst [c&31] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLconst {
|
|
goto end633f9ddcfbb63374c895a5f78da75d25
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SHLLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 31
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end633f9ddcfbb63374c895a5f78da75d25
|
|
end633f9ddcfbb63374c895a5f78da75d25:
|
|
;
|
|
case OpAMD64SHLQ:
|
|
// match: (SHLQ x (MOVQconst [c]))
|
|
// cond:
|
|
// result: (SHLQconst [c&63] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end4d7e3a945cacdd6b6c8c0de6f465d4ae
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SHLQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 63
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end4d7e3a945cacdd6b6c8c0de6f465d4ae
|
|
end4d7e3a945cacdd6b6c8c0de6f465d4ae:
|
|
;
|
|
case OpAMD64SHLW:
|
|
// match: (SHLW x (MOVWconst [c]))
|
|
// cond:
|
|
// result: (SHLWconst [c&31] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWconst {
|
|
goto endba96a52aa58d28b3357828051e0e695c
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SHLWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 31
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endba96a52aa58d28b3357828051e0e695c
|
|
endba96a52aa58d28b3357828051e0e695c:
|
|
;
|
|
case OpAMD64SHRB:
|
|
// match: (SHRB x (MOVBconst [c]))
|
|
// cond:
|
|
// result: (SHRBconst [c&31] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBconst {
|
|
goto enddb1cd5aaa826d43fa4f6d1b2b8795e58
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SHRBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 31
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enddb1cd5aaa826d43fa4f6d1b2b8795e58
|
|
enddb1cd5aaa826d43fa4f6d1b2b8795e58:
|
|
;
|
|
case OpAMD64SHRL:
|
|
// match: (SHRL x (MOVLconst [c]))
|
|
// cond:
|
|
// result: (SHRLconst [c&31] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLconst {
|
|
goto end344b8b9202e1925e8d0561f1c21412fc
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SHRLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 31
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end344b8b9202e1925e8d0561f1c21412fc
|
|
end344b8b9202e1925e8d0561f1c21412fc:
|
|
;
|
|
case OpAMD64SHRQ:
|
|
// match: (SHRQ x (MOVQconst [c]))
|
|
// cond:
|
|
// result: (SHRQconst [c&63] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end699d35e2d5cfa08b8a3b1c8a183ddcf3
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SHRQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 63
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end699d35e2d5cfa08b8a3b1c8a183ddcf3
|
|
end699d35e2d5cfa08b8a3b1c8a183ddcf3:
|
|
;
|
|
case OpAMD64SHRW:
|
|
// match: (SHRW x (MOVWconst [c]))
|
|
// cond:
|
|
// result: (SHRWconst [c&31] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWconst {
|
|
goto endd75ff1f9b3e9ec9c942a39b6179da1b3
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SHRWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c & 31
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endd75ff1f9b3e9ec9c942a39b6179da1b3
|
|
endd75ff1f9b3e9ec9c942a39b6179da1b3:
|
|
;
|
|
case OpAMD64SUBB:
|
|
// match: (SUBB x (MOVBconst [c]))
|
|
// cond:
|
|
// result: (SUBBconst x [c])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBconst {
|
|
goto end9ca5d2a70e2df1a5a3ed6786bce1f7b2
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SUBBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AuxInt = c
|
|
return true
|
|
}
|
|
goto end9ca5d2a70e2df1a5a3ed6786bce1f7b2
|
|
end9ca5d2a70e2df1a5a3ed6786bce1f7b2:
|
|
;
|
|
// match: (SUBB (MOVBconst [c]) x)
|
|
// cond:
|
|
// result: (NEGB (SUBBconst <v.Type> x [c]))
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVBconst {
|
|
goto endc288755d69b04d24a6aac32a73956411
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64NEGB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SUBBconst, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v0.AuxInt = c
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endc288755d69b04d24a6aac32a73956411
|
|
endc288755d69b04d24a6aac32a73956411:
|
|
;
|
|
// match: (SUBB x x)
|
|
// cond:
|
|
// result: (MOVBconst [0])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto ende8904403d937d95b0d6133d3ec92bb45
|
|
}
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto ende8904403d937d95b0d6133d3ec92bb45
|
|
ende8904403d937d95b0d6133d3ec92bb45:
|
|
;
|
|
case OpAMD64SUBBconst:
|
|
// match: (SUBBconst [c] (MOVBconst [d]))
|
|
// cond:
|
|
// result: (MOVBconst [c-d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVBconst {
|
|
goto end0e2d5c3e3c02001a20d5433daa9e8317
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c - d
|
|
return true
|
|
}
|
|
goto end0e2d5c3e3c02001a20d5433daa9e8317
|
|
end0e2d5c3e3c02001a20d5433daa9e8317:
|
|
;
|
|
// match: (SUBBconst [c] (SUBBconst [d] x))
|
|
// cond:
|
|
// result: (ADDBconst [c-d] x)
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64SUBBconst {
|
|
goto end48eccb421dfe0c678ea9c47113521d5a
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64ADDBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c - d
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end48eccb421dfe0c678ea9c47113521d5a
|
|
end48eccb421dfe0c678ea9c47113521d5a:
|
|
;
|
|
case OpAMD64SUBL:
|
|
// match: (SUBL x (MOVLconst [c]))
|
|
// cond:
|
|
// result: (SUBLconst x [c])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLconst {
|
|
goto end178c1d6c86f9c16f6497586c2f7d8625
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SUBLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AuxInt = c
|
|
return true
|
|
}
|
|
goto end178c1d6c86f9c16f6497586c2f7d8625
|
|
end178c1d6c86f9c16f6497586c2f7d8625:
|
|
;
|
|
// match: (SUBL (MOVLconst [c]) x)
|
|
// cond:
|
|
// result: (NEGL (SUBLconst <v.Type> x [c]))
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto endb0efe6e15ec20486b849534a00483ae2
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64NEGL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SUBLconst, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v0.AuxInt = c
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto endb0efe6e15ec20486b849534a00483ae2
|
|
endb0efe6e15ec20486b849534a00483ae2:
|
|
;
|
|
// match: (SUBL x x)
|
|
// cond:
|
|
// result: (MOVLconst [0])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto end332f1f641f875c69bea7289191e69133
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end332f1f641f875c69bea7289191e69133
|
|
end332f1f641f875c69bea7289191e69133:
|
|
;
|
|
case OpAMD64SUBLconst:
|
|
// match: (SUBLconst [c] (MOVLconst [d]))
|
|
// cond:
|
|
// result: (MOVLconst [c-d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto endbe7466f3c09d9645544bdfc44c37c922
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c - d
|
|
return true
|
|
}
|
|
goto endbe7466f3c09d9645544bdfc44c37c922
|
|
endbe7466f3c09d9645544bdfc44c37c922:
|
|
;
|
|
// match: (SUBLconst [c] (SUBLconst [d] x))
|
|
// cond:
|
|
// result: (ADDLconst [c-d] x)
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64SUBLconst {
|
|
goto endb5106962a865bc4654b170c2e29a72c4
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64ADDLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c - d
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endb5106962a865bc4654b170c2e29a72c4
|
|
endb5106962a865bc4654b170c2e29a72c4:
|
|
;
|
|
case OpAMD64SUBQ:
|
|
// match: (SUBQ x (MOVQconst [c]))
|
|
// cond: is32Bit(c)
|
|
// result: (SUBQconst x [c])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end9bbb7b20824a498752c605942fad89c2
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
if !(is32Bit(c)) {
|
|
goto end9bbb7b20824a498752c605942fad89c2
|
|
}
|
|
v.Op = OpAMD64SUBQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AuxInt = c
|
|
return true
|
|
}
|
|
goto end9bbb7b20824a498752c605942fad89c2
|
|
end9bbb7b20824a498752c605942fad89c2:
|
|
;
|
|
// match: (SUBQ (MOVQconst [c]) x)
|
|
// cond: is32Bit(c)
|
|
// result: (NEGQ (SUBQconst <v.Type> x [c]))
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end8beb96de3efee9206d1bd4b7d777d2cb
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
if !(is32Bit(c)) {
|
|
goto end8beb96de3efee9206d1bd4b7d777d2cb
|
|
}
|
|
v.Op = OpAMD64NEGQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SUBQconst, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v0.AuxInt = c
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end8beb96de3efee9206d1bd4b7d777d2cb
|
|
end8beb96de3efee9206d1bd4b7d777d2cb:
|
|
;
|
|
// match: (SUBQ x x)
|
|
// cond:
|
|
// result: (MOVQconst [0])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto endd87d1d839d2dc54d9c90fa4f73383480
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto endd87d1d839d2dc54d9c90fa4f73383480
|
|
endd87d1d839d2dc54d9c90fa4f73383480:
|
|
;
|
|
case OpAMD64SUBQconst:
|
|
// match: (SUBQconst [c] (MOVQconst [d]))
|
|
// cond:
|
|
// result: (MOVQconst [c-d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end96c09479fb3c043e875d89d3eb92f1d8
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c - d
|
|
return true
|
|
}
|
|
goto end96c09479fb3c043e875d89d3eb92f1d8
|
|
end96c09479fb3c043e875d89d3eb92f1d8:
|
|
;
|
|
// match: (SUBQconst [c] (SUBQconst [d] x))
|
|
// cond:
|
|
// result: (ADDQconst [c-d] x)
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64SUBQconst {
|
|
goto enddd9d61b404480adb40cfd7fedd7e5ec4
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64ADDQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c - d
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enddd9d61b404480adb40cfd7fedd7e5ec4
|
|
enddd9d61b404480adb40cfd7fedd7e5ec4:
|
|
;
|
|
case OpAMD64SUBW:
|
|
// match: (SUBW x (MOVWconst [c]))
|
|
// cond:
|
|
// result: (SUBWconst x [c])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWconst {
|
|
goto end135aa9100b2f61d58b37cede37b63731
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64SUBWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AuxInt = c
|
|
return true
|
|
}
|
|
goto end135aa9100b2f61d58b37cede37b63731
|
|
end135aa9100b2f61d58b37cede37b63731:
|
|
;
|
|
// match: (SUBW (MOVWconst [c]) x)
|
|
// cond:
|
|
// result: (NEGW (SUBWconst <v.Type> x [c]))
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto end44d23f7e65a4b1c42d0e6463f8e493b6
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64NEGW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v0 := b.NewValue0(v.Line, OpAMD64SUBWconst, TypeInvalid)
|
|
v0.Type = v.Type
|
|
v0.AddArg(x)
|
|
v0.AuxInt = c
|
|
v.AddArg(v0)
|
|
return true
|
|
}
|
|
goto end44d23f7e65a4b1c42d0e6463f8e493b6
|
|
end44d23f7e65a4b1c42d0e6463f8e493b6:
|
|
;
|
|
// match: (SUBW x x)
|
|
// cond:
|
|
// result: (MOVWconst [0])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto endb970e7c318d04a1afe1dfe08a7ca0d9c
|
|
}
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto endb970e7c318d04a1afe1dfe08a7ca0d9c
|
|
endb970e7c318d04a1afe1dfe08a7ca0d9c:
|
|
;
|
|
case OpAMD64SUBWconst:
|
|
// match: (SUBWconst [c] (MOVWconst [d]))
|
|
// cond:
|
|
// result: (MOVWconst [c-d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto end0e5079577fcf00f5925291dbd68306aa
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c - d
|
|
return true
|
|
}
|
|
goto end0e5079577fcf00f5925291dbd68306aa
|
|
end0e5079577fcf00f5925291dbd68306aa:
|
|
;
|
|
// match: (SUBWconst [c] (SUBWconst [d] x))
|
|
// cond:
|
|
// result: (ADDWconst [c-d] x)
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64SUBWconst {
|
|
goto endb628696cf5b329d03782b8093093269b
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
x := v.Args[0].Args[0]
|
|
v.Op = OpAMD64ADDWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c - d
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endb628696cf5b329d03782b8093093269b
|
|
endb628696cf5b329d03782b8093093269b:
|
|
;
|
|
case OpSignExt16to32:
|
|
// match: (SignExt16to32 x)
|
|
// cond:
|
|
// result: (MOVWQSX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVWQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end21e4271c2b48a5aa3561ccfa8fa67cd9
|
|
end21e4271c2b48a5aa3561ccfa8fa67cd9:
|
|
;
|
|
case OpSignExt16to64:
|
|
// match: (SignExt16to64 x)
|
|
// cond:
|
|
// result: (MOVWQSX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVWQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endc6d242ee3a3e195ef0f9e8dae47ada75
|
|
endc6d242ee3a3e195ef0f9e8dae47ada75:
|
|
;
|
|
case OpSignExt32to64:
|
|
// match: (SignExt32to64 x)
|
|
// cond:
|
|
// result: (MOVLQSX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVLQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endb9f1a8b2d01eee44964a71a01bca165c
|
|
endb9f1a8b2d01eee44964a71a01bca165c:
|
|
;
|
|
case OpSignExt8to16:
|
|
// match: (SignExt8to16 x)
|
|
// cond:
|
|
// result: (MOVBQSX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVBQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end372869f08e147404b80634e5f83fd506
|
|
end372869f08e147404b80634e5f83fd506:
|
|
;
|
|
case OpSignExt8to32:
|
|
// match: (SignExt8to32 x)
|
|
// cond:
|
|
// result: (MOVBQSX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVBQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end913e3575e5b4cf7f60585c108db40464
|
|
end913e3575e5b4cf7f60585c108db40464:
|
|
;
|
|
case OpSignExt8to64:
|
|
// match: (SignExt8to64 x)
|
|
// cond:
|
|
// result: (MOVBQSX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVBQSX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endcef6d6001d3f25cf5dacee11a46e5c8c
|
|
endcef6d6001d3f25cf5dacee11a46e5c8c:
|
|
;
|
|
case OpStaticCall:
|
|
// match: (StaticCall [argwid] {target} mem)
|
|
// cond:
|
|
// result: (CALLstatic [argwid] {target} mem)
|
|
{
|
|
argwid := v.AuxInt
|
|
target := v.Aux
|
|
mem := v.Args[0]
|
|
v.Op = OpAMD64CALLstatic
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = argwid
|
|
v.Aux = target
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end32c5cbec813d1c2ae94fc9b1090e4b2a
|
|
end32c5cbec813d1c2ae94fc9b1090e4b2a:
|
|
;
|
|
case OpStore:
|
|
// match: (Store ptr val mem)
|
|
// cond: (is64BitInt(val.Type) || isPtr(val.Type))
|
|
// result: (MOVQstore ptr val mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(is64BitInt(val.Type) || isPtr(val.Type)) {
|
|
goto endbaeb60123806948cd2433605820d5af1
|
|
}
|
|
v.Op = OpAMD64MOVQstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endbaeb60123806948cd2433605820d5af1
|
|
endbaeb60123806948cd2433605820d5af1:
|
|
;
|
|
// match: (Store ptr val mem)
|
|
// cond: is32BitInt(val.Type)
|
|
// result: (MOVLstore ptr val mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(is32BitInt(val.Type)) {
|
|
goto end582e895008657c728c141c6b95070de7
|
|
}
|
|
v.Op = OpAMD64MOVLstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end582e895008657c728c141c6b95070de7
|
|
end582e895008657c728c141c6b95070de7:
|
|
;
|
|
// match: (Store ptr val mem)
|
|
// cond: is16BitInt(val.Type)
|
|
// result: (MOVWstore ptr val mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(is16BitInt(val.Type)) {
|
|
goto enda3f6a985b6ebb277665f80ad30b178df
|
|
}
|
|
v.Op = OpAMD64MOVWstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto enda3f6a985b6ebb277665f80ad30b178df
|
|
enda3f6a985b6ebb277665f80ad30b178df:
|
|
;
|
|
// match: (Store ptr val mem)
|
|
// cond: is8BitInt(val.Type)
|
|
// result: (MOVBstore ptr val mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(is8BitInt(val.Type)) {
|
|
goto ende2dee0bc82f631e3c6b0031bf8d224c1
|
|
}
|
|
v.Op = OpAMD64MOVBstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto ende2dee0bc82f631e3c6b0031bf8d224c1
|
|
ende2dee0bc82f631e3c6b0031bf8d224c1:
|
|
;
|
|
// match: (Store ptr val mem)
|
|
// cond: val.Type.IsBoolean()
|
|
// result: (MOVBstore ptr val mem)
|
|
{
|
|
ptr := v.Args[0]
|
|
val := v.Args[1]
|
|
mem := v.Args[2]
|
|
if !(val.Type.IsBoolean()) {
|
|
goto end6f343b676bf49740054e459f972b24f5
|
|
}
|
|
v.Op = OpAMD64MOVBstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(ptr)
|
|
v.AddArg(val)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end6f343b676bf49740054e459f972b24f5
|
|
end6f343b676bf49740054e459f972b24f5:
|
|
;
|
|
case OpSub16:
|
|
// match: (Sub16 x y)
|
|
// cond:
|
|
// result: (SUBW x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SUBW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end54adc5de883c0460ca71c6ee464d4244
|
|
end54adc5de883c0460ca71c6ee464d4244:
|
|
;
|
|
case OpSub32:
|
|
// match: (Sub32 x y)
|
|
// cond:
|
|
// result: (SUBL x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SUBL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto enddc3a2a488bda8c5856f93343e5ffe5f8
|
|
enddc3a2a488bda8c5856f93343e5ffe5f8:
|
|
;
|
|
case OpSub64:
|
|
// match: (Sub64 x y)
|
|
// cond:
|
|
// result: (SUBQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SUBQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto endd88d5646309fd9174584888ecc8aca2c
|
|
endd88d5646309fd9174584888ecc8aca2c:
|
|
;
|
|
case OpSub8:
|
|
// match: (Sub8 x y)
|
|
// cond:
|
|
// result: (SUBB x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64SUBB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end7d33bf9bdfa505f96b930563eca7955f
|
|
end7d33bf9bdfa505f96b930563eca7955f:
|
|
;
|
|
case OpTrunc16to8:
|
|
// match: (Trunc16to8 x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end8e2f5e0a6e3a06423c077747de6c2bdd
|
|
end8e2f5e0a6e3a06423c077747de6c2bdd:
|
|
;
|
|
case OpTrunc32to16:
|
|
// match: (Trunc32to16 x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end5bed0e3a3c1c6374d86beb5a4397708c
|
|
end5bed0e3a3c1c6374d86beb5a4397708c:
|
|
;
|
|
case OpTrunc32to8:
|
|
// match: (Trunc32to8 x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endef0b8032ce91979ce6cd0004260c04ee
|
|
endef0b8032ce91979ce6cd0004260c04ee:
|
|
;
|
|
case OpTrunc64to16:
|
|
// match: (Trunc64to16 x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endd32fd6e0ce970c212835e6f71c3dcbfd
|
|
endd32fd6e0ce970c212835e6f71c3dcbfd:
|
|
;
|
|
case OpTrunc64to32:
|
|
// match: (Trunc64to32 x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end1212c4e84153210aff7fd630fb3e1883
|
|
end1212c4e84153210aff7fd630fb3e1883:
|
|
;
|
|
case OpTrunc64to8:
|
|
// match: (Trunc64to8 x)
|
|
// cond:
|
|
// result: x
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = x.Type
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end734f017d4b2810ca2288f7037365824c
|
|
end734f017d4b2810ca2288f7037365824c:
|
|
;
|
|
case OpAMD64XORB:
|
|
// match: (XORB x (MOVBconst [c]))
|
|
// cond:
|
|
// result: (XORBconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVBconst {
|
|
goto enda9ed9fdd115ffdffa8127c007c34d7b7
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64XORBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enda9ed9fdd115ffdffa8127c007c34d7b7
|
|
enda9ed9fdd115ffdffa8127c007c34d7b7:
|
|
;
|
|
// match: (XORB (MOVBconst [c]) x)
|
|
// cond:
|
|
// result: (XORBconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVBconst {
|
|
goto endb02a07d9dc7b802c59f013116e952f3f
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64XORBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endb02a07d9dc7b802c59f013116e952f3f
|
|
endb02a07d9dc7b802c59f013116e952f3f:
|
|
;
|
|
// match: (XORB x x)
|
|
// cond:
|
|
// result: (MOVBconst [0])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto end2afddc39503d04d572a3a07878f6c9c9
|
|
}
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end2afddc39503d04d572a3a07878f6c9c9
|
|
end2afddc39503d04d572a3a07878f6c9c9:
|
|
;
|
|
case OpAMD64XORBconst:
|
|
// match: (XORBconst [c] (MOVBconst [d]))
|
|
// cond:
|
|
// result: (MOVBconst [c^d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVBconst {
|
|
goto end6d8d1b612af9d253605c8bc69b822903
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVBconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c ^ d
|
|
return true
|
|
}
|
|
goto end6d8d1b612af9d253605c8bc69b822903
|
|
end6d8d1b612af9d253605c8bc69b822903:
|
|
;
|
|
case OpAMD64XORL:
|
|
// match: (XORL x (MOVLconst [c]))
|
|
// cond:
|
|
// result: (XORLconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVLconst {
|
|
goto enda9459d509d3416da67d13a22dd074a9c
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64XORLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enda9459d509d3416da67d13a22dd074a9c
|
|
enda9459d509d3416da67d13a22dd074a9c:
|
|
;
|
|
// match: (XORL (MOVLconst [c]) x)
|
|
// cond:
|
|
// result: (XORLconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto end9c1a0af00eeadd8aa325e55f1f3fb89c
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64XORLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end9c1a0af00eeadd8aa325e55f1f3fb89c
|
|
end9c1a0af00eeadd8aa325e55f1f3fb89c:
|
|
;
|
|
// match: (XORL x x)
|
|
// cond:
|
|
// result: (MOVLconst [0])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto end7bcf9cfeb69a0d7647389124eb53ce2a
|
|
}
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end7bcf9cfeb69a0d7647389124eb53ce2a
|
|
end7bcf9cfeb69a0d7647389124eb53ce2a:
|
|
;
|
|
case OpAMD64XORLconst:
|
|
// match: (XORLconst [c] (MOVLconst [d]))
|
|
// cond:
|
|
// result: (MOVLconst [c^d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVLconst {
|
|
goto end71238075b10b68a226903cc453c4715c
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVLconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c ^ d
|
|
return true
|
|
}
|
|
goto end71238075b10b68a226903cc453c4715c
|
|
end71238075b10b68a226903cc453c4715c:
|
|
;
|
|
case OpAMD64XORQ:
|
|
// match: (XORQ x (MOVQconst [c]))
|
|
// cond: is32Bit(c)
|
|
// result: (XORQconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
|
goto end452341f950062e0483f16438fb9ec500
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
if !(is32Bit(c)) {
|
|
goto end452341f950062e0483f16438fb9ec500
|
|
}
|
|
v.Op = OpAMD64XORQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end452341f950062e0483f16438fb9ec500
|
|
end452341f950062e0483f16438fb9ec500:
|
|
;
|
|
// match: (XORQ (MOVQconst [c]) x)
|
|
// cond: is32Bit(c)
|
|
// result: (XORQconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto endd221a7e3daaaaa29ee385ad36e061b57
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
if !(is32Bit(c)) {
|
|
goto endd221a7e3daaaaa29ee385ad36e061b57
|
|
}
|
|
v.Op = OpAMD64XORQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endd221a7e3daaaaa29ee385ad36e061b57
|
|
endd221a7e3daaaaa29ee385ad36e061b57:
|
|
;
|
|
// match: (XORQ x x)
|
|
// cond:
|
|
// result: (MOVQconst [0])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto end10575a5d711cf14e6d4dffbb0e8dfaeb
|
|
}
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end10575a5d711cf14e6d4dffbb0e8dfaeb
|
|
end10575a5d711cf14e6d4dffbb0e8dfaeb:
|
|
;
|
|
case OpAMD64XORQconst:
|
|
// match: (XORQconst [c] (MOVQconst [d]))
|
|
// cond:
|
|
// result: (MOVQconst [c^d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
|
goto end3f404d4f07362319fbad2e1ba0827a9f
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVQconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c ^ d
|
|
return true
|
|
}
|
|
goto end3f404d4f07362319fbad2e1ba0827a9f
|
|
end3f404d4f07362319fbad2e1ba0827a9f:
|
|
;
|
|
case OpAMD64XORW:
|
|
// match: (XORW x (MOVWconst [c]))
|
|
// cond:
|
|
// result: (XORWconst [c] x)
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1].Op != OpAMD64MOVWconst {
|
|
goto end2ca109efd66c221a5691a4da95ec6c67
|
|
}
|
|
c := v.Args[1].AuxInt
|
|
v.Op = OpAMD64XORWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end2ca109efd66c221a5691a4da95ec6c67
|
|
end2ca109efd66c221a5691a4da95ec6c67:
|
|
;
|
|
// match: (XORW (MOVWconst [c]) x)
|
|
// cond:
|
|
// result: (XORWconst [c] x)
|
|
{
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto end51ee62a06d4301e5a4aed7a6639b1d53
|
|
}
|
|
c := v.Args[0].AuxInt
|
|
x := v.Args[1]
|
|
v.Op = OpAMD64XORWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end51ee62a06d4301e5a4aed7a6639b1d53
|
|
end51ee62a06d4301e5a4aed7a6639b1d53:
|
|
;
|
|
// match: (XORW x x)
|
|
// cond:
|
|
// result: (MOVWconst [0])
|
|
{
|
|
x := v.Args[0]
|
|
if v.Args[1] != x {
|
|
goto end07f332e857be0c2707797ed480a2faf4
|
|
}
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = 0
|
|
return true
|
|
}
|
|
goto end07f332e857be0c2707797ed480a2faf4
|
|
end07f332e857be0c2707797ed480a2faf4:
|
|
;
|
|
case OpAMD64XORWconst:
|
|
// match: (XORWconst [c] (MOVWconst [d]))
|
|
// cond:
|
|
// result: (MOVWconst [c^d])
|
|
{
|
|
c := v.AuxInt
|
|
if v.Args[0].Op != OpAMD64MOVWconst {
|
|
goto ende24881ccdfa8486c4593fd9aa5df1ed6
|
|
}
|
|
d := v.Args[0].AuxInt
|
|
v.Op = OpAMD64MOVWconst
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = c ^ d
|
|
return true
|
|
}
|
|
goto ende24881ccdfa8486c4593fd9aa5df1ed6
|
|
ende24881ccdfa8486c4593fd9aa5df1ed6:
|
|
;
|
|
case OpXor16:
|
|
// match: (Xor16 x y)
|
|
// cond:
|
|
// result: (XORW x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64XORW
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end20efdd5dfd5130abf818de5546a991a0
|
|
end20efdd5dfd5130abf818de5546a991a0:
|
|
;
|
|
case OpXor32:
|
|
// match: (Xor32 x y)
|
|
// cond:
|
|
// result: (XORL x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64XORL
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end9da6bce98b437e2609488346116a75d8
|
|
end9da6bce98b437e2609488346116a75d8:
|
|
;
|
|
case OpXor64:
|
|
// match: (Xor64 x y)
|
|
// cond:
|
|
// result: (XORQ x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64XORQ
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto endc88cd189c2a6f07ecff324ed94809f8f
|
|
endc88cd189c2a6f07ecff324ed94809f8f:
|
|
;
|
|
case OpXor8:
|
|
// match: (Xor8 x y)
|
|
// cond:
|
|
// result: (XORB x y)
|
|
{
|
|
x := v.Args[0]
|
|
y := v.Args[1]
|
|
v.Op = OpAMD64XORB
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
v.AddArg(y)
|
|
return true
|
|
}
|
|
goto end50f4434ef96916d3e65ad3cc236d1723
|
|
end50f4434ef96916d3e65ad3cc236d1723:
|
|
;
|
|
case OpZero:
|
|
// match: (Zero [0] _ mem)
|
|
// cond:
|
|
// result: mem
|
|
{
|
|
if v.AuxInt != 0 {
|
|
goto endc9a38a60f0322f93682daa824611272c
|
|
}
|
|
mem := v.Args[1]
|
|
v.Op = OpCopy
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.Type = mem.Type
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endc9a38a60f0322f93682daa824611272c
|
|
endc9a38a60f0322f93682daa824611272c:
|
|
;
|
|
// match: (Zero [1] destptr mem)
|
|
// cond:
|
|
// result: (MOVBstore destptr (MOVBconst <config.Frontend().TypeInt8()> [0]) mem)
|
|
{
|
|
if v.AuxInt != 1 {
|
|
goto end56bcaef03cce4d15c03efff669bb5585
|
|
}
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVBstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(destptr)
|
|
v0 := b.NewValue0(v.Line, OpAMD64MOVBconst, TypeInvalid)
|
|
v0.Type = config.Frontend().TypeInt8()
|
|
v0.AuxInt = 0
|
|
v.AddArg(v0)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end56bcaef03cce4d15c03efff669bb5585
|
|
end56bcaef03cce4d15c03efff669bb5585:
|
|
;
|
|
// match: (Zero [2] destptr mem)
|
|
// cond:
|
|
// result: (MOVWstore destptr (MOVWconst <config.Frontend().TypeInt16()> [0]) mem)
|
|
{
|
|
if v.AuxInt != 2 {
|
|
goto endf52f08f1f7b0ae220c4cfca6586a8586
|
|
}
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVWstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(destptr)
|
|
v0 := b.NewValue0(v.Line, OpAMD64MOVWconst, TypeInvalid)
|
|
v0.Type = config.Frontend().TypeInt16()
|
|
v0.AuxInt = 0
|
|
v.AddArg(v0)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endf52f08f1f7b0ae220c4cfca6586a8586
|
|
endf52f08f1f7b0ae220c4cfca6586a8586:
|
|
;
|
|
// match: (Zero [4] destptr mem)
|
|
// cond:
|
|
// result: (MOVLstore destptr (MOVLconst <config.Frontend().TypeInt32()> [0]) mem)
|
|
{
|
|
if v.AuxInt != 4 {
|
|
goto end41c91e0c7a23e233de77812b5264fd10
|
|
}
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVLstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(destptr)
|
|
v0 := b.NewValue0(v.Line, OpAMD64MOVLconst, TypeInvalid)
|
|
v0.Type = config.Frontend().TypeInt32()
|
|
v0.AuxInt = 0
|
|
v.AddArg(v0)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end41c91e0c7a23e233de77812b5264fd10
|
|
end41c91e0c7a23e233de77812b5264fd10:
|
|
;
|
|
// match: (Zero [8] destptr mem)
|
|
// cond:
|
|
// result: (MOVQstore destptr (MOVQconst <config.Frontend().TypeInt64()> [0]) mem)
|
|
{
|
|
if v.AuxInt != 8 {
|
|
goto end157ad586af643d8dac6cc84a776000ca
|
|
}
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
v.Op = OpAMD64MOVQstore
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(destptr)
|
|
v0 := b.NewValue0(v.Line, OpAMD64MOVQconst, TypeInvalid)
|
|
v0.Type = config.Frontend().TypeInt64()
|
|
v0.AuxInt = 0
|
|
v.AddArg(v0)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto end157ad586af643d8dac6cc84a776000ca
|
|
end157ad586af643d8dac6cc84a776000ca:
|
|
;
|
|
// match: (Zero [size] destptr mem)
|
|
// cond: size < 4*8
|
|
// result: (MOVXzero [size] destptr mem)
|
|
{
|
|
size := v.AuxInt
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(size < 4*8) {
|
|
goto endf0a22f1506977610ac0a310eee152075
|
|
}
|
|
v.Op = OpAMD64MOVXzero
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = size
|
|
v.AddArg(destptr)
|
|
v.AddArg(mem)
|
|
return true
|
|
}
|
|
goto endf0a22f1506977610ac0a310eee152075
|
|
endf0a22f1506977610ac0a310eee152075:
|
|
;
|
|
// match: (Zero [size] destptr mem)
|
|
// cond: size >= 4*8
|
|
// result: (Zero [size%8] (OffPtr <config.Frontend().TypeUInt64()> [size-(size%8)] destptr) (REPSTOSQ <TypeMem> destptr (MOVQconst <config.Frontend().TypeUInt64()> [size/8]) mem))
|
|
{
|
|
size := v.AuxInt
|
|
destptr := v.Args[0]
|
|
mem := v.Args[1]
|
|
if !(size >= 4*8) {
|
|
goto end84c39fe2e8d40e0042a10741a0ef16bd
|
|
}
|
|
v.Op = OpZero
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AuxInt = size % 8
|
|
v0 := b.NewValue0(v.Line, OpOffPtr, TypeInvalid)
|
|
v0.Type = config.Frontend().TypeUInt64()
|
|
v0.AuxInt = size - (size % 8)
|
|
v0.AddArg(destptr)
|
|
v.AddArg(v0)
|
|
v1 := b.NewValue0(v.Line, OpAMD64REPSTOSQ, TypeInvalid)
|
|
v1.Type = TypeMem
|
|
v1.AddArg(destptr)
|
|
v2 := b.NewValue0(v.Line, OpAMD64MOVQconst, TypeInvalid)
|
|
v2.Type = config.Frontend().TypeUInt64()
|
|
v2.AuxInt = size / 8
|
|
v1.AddArg(v2)
|
|
v1.AddArg(mem)
|
|
v.AddArg(v1)
|
|
return true
|
|
}
|
|
goto end84c39fe2e8d40e0042a10741a0ef16bd
|
|
end84c39fe2e8d40e0042a10741a0ef16bd:
|
|
;
|
|
case OpZeroExt16to32:
|
|
// match: (ZeroExt16to32 x)
|
|
// cond:
|
|
// result: (MOVWQZX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVWQZX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endbfff79412a2cc96095069c66812844b4
|
|
endbfff79412a2cc96095069c66812844b4:
|
|
;
|
|
case OpZeroExt16to64:
|
|
// match: (ZeroExt16to64 x)
|
|
// cond:
|
|
// result: (MOVWQZX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVWQZX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end7a40262c5c856101058d2bd518ed0910
|
|
end7a40262c5c856101058d2bd518ed0910:
|
|
;
|
|
case OpZeroExt32to64:
|
|
// match: (ZeroExt32to64 x)
|
|
// cond:
|
|
// result: (MOVLQZX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVLQZX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto enddf83bdc8cc6c5673a9ef7aca7affe45a
|
|
enddf83bdc8cc6c5673a9ef7aca7affe45a:
|
|
;
|
|
case OpZeroExt8to16:
|
|
// match: (ZeroExt8to16 x)
|
|
// cond:
|
|
// result: (MOVBQZX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVBQZX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endd03d53d2a585727e4107ae1a3cc55479
|
|
endd03d53d2a585727e4107ae1a3cc55479:
|
|
;
|
|
case OpZeroExt8to32:
|
|
// match: (ZeroExt8to32 x)
|
|
// cond:
|
|
// result: (MOVBQZX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVBQZX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto endcbd33e965b3dab14fced5ae93d8949de
|
|
endcbd33e965b3dab14fced5ae93d8949de:
|
|
;
|
|
case OpZeroExt8to64:
|
|
// match: (ZeroExt8to64 x)
|
|
// cond:
|
|
// result: (MOVBQZX x)
|
|
{
|
|
x := v.Args[0]
|
|
v.Op = OpAMD64MOVBQZX
|
|
v.AuxInt = 0
|
|
v.Aux = nil
|
|
v.resetArgs()
|
|
v.AddArg(x)
|
|
return true
|
|
}
|
|
goto end63ae7cc15db9d15189b2f1342604b2cb
|
|
end63ae7cc15db9d15189b2f1342604b2cb:
|
|
}
|
|
return false
|
|
}
|
|
func rewriteBlockAMD64(b *Block) bool {
|
|
switch b.Kind {
|
|
case BlockAMD64EQ:
|
|
// match: (EQ (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (EQ cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end6b8e9afc73b1c4d528f31a60d2575fae
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64EQ
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end6b8e9afc73b1c4d528f31a60d2575fae
|
|
end6b8e9afc73b1c4d528f31a60d2575fae:
|
|
;
|
|
case BlockAMD64GE:
|
|
// match: (GE (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (LE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end0610f000a6988ee8310307ec2ea138f8
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64LE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end0610f000a6988ee8310307ec2ea138f8
|
|
end0610f000a6988ee8310307ec2ea138f8:
|
|
;
|
|
case BlockAMD64GT:
|
|
// match: (GT (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (LT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto endf60c0660b6a8aa9565c97fc87f04eb34
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64LT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endf60c0660b6a8aa9565c97fc87f04eb34
|
|
endf60c0660b6a8aa9565c97fc87f04eb34:
|
|
;
|
|
case BlockIf:
|
|
// match: (If (SETL cmp) yes no)
|
|
// cond:
|
|
// result: (LT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETL {
|
|
goto end94277282f4b83f0c035b23711a075801
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64LT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end94277282f4b83f0c035b23711a075801
|
|
end94277282f4b83f0c035b23711a075801:
|
|
;
|
|
// match: (If (SETLE cmp) yes no)
|
|
// cond:
|
|
// result: (LE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETLE {
|
|
goto enda84798dd797927b54a9a2987421b2ba2
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64LE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto enda84798dd797927b54a9a2987421b2ba2
|
|
enda84798dd797927b54a9a2987421b2ba2:
|
|
;
|
|
// match: (If (SETG cmp) yes no)
|
|
// cond:
|
|
// result: (GT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETG {
|
|
goto end3434ef985979cbf394455ab5b559567c
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64GT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end3434ef985979cbf394455ab5b559567c
|
|
end3434ef985979cbf394455ab5b559567c:
|
|
;
|
|
// match: (If (SETGE cmp) yes no)
|
|
// cond:
|
|
// result: (GE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETGE {
|
|
goto endee147d81d8620a5e23cb92bd9f13cf8d
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64GE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endee147d81d8620a5e23cb92bd9f13cf8d
|
|
endee147d81d8620a5e23cb92bd9f13cf8d:
|
|
;
|
|
// match: (If (SETEQ cmp) yes no)
|
|
// cond:
|
|
// result: (EQ cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETEQ {
|
|
goto ende7d85ccc850fc3963c50a91df096de17
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64EQ
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto ende7d85ccc850fc3963c50a91df096de17
|
|
ende7d85ccc850fc3963c50a91df096de17:
|
|
;
|
|
// match: (If (SETNE cmp) yes no)
|
|
// cond:
|
|
// result: (NE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETNE {
|
|
goto endba4b54260ecda1b5731b129c0eb493d0
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64NE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endba4b54260ecda1b5731b129c0eb493d0
|
|
endba4b54260ecda1b5731b129c0eb493d0:
|
|
;
|
|
// match: (If (SETB cmp) yes no)
|
|
// cond:
|
|
// result: (ULT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETB {
|
|
goto endf84eedfcd3f18f5c9c3f3d1045a24330
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64ULT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endf84eedfcd3f18f5c9c3f3d1045a24330
|
|
endf84eedfcd3f18f5c9c3f3d1045a24330:
|
|
;
|
|
// match: (If (SETBE cmp) yes no)
|
|
// cond:
|
|
// result: (ULE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETBE {
|
|
goto endfe0178f6f4406945ca8966817d04be60
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64ULE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endfe0178f6f4406945ca8966817d04be60
|
|
endfe0178f6f4406945ca8966817d04be60:
|
|
;
|
|
// match: (If (SETA cmp) yes no)
|
|
// cond:
|
|
// result: (UGT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETA {
|
|
goto end2b5a2d7756bdba01a732bf54d9acdb73
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64UGT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end2b5a2d7756bdba01a732bf54d9acdb73
|
|
end2b5a2d7756bdba01a732bf54d9acdb73:
|
|
;
|
|
// match: (If (SETAE cmp) yes no)
|
|
// cond:
|
|
// result: (UGE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64SETAE {
|
|
goto end9bea9963c3c5dfb97249a5feb8287f94
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64UGE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end9bea9963c3c5dfb97249a5feb8287f94
|
|
end9bea9963c3c5dfb97249a5feb8287f94:
|
|
;
|
|
// match: (If cond yes no)
|
|
// cond:
|
|
// result: (NE (TESTB <TypeFlags> cond cond) yes no)
|
|
{
|
|
v := b.Control
|
|
cond := v
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64NE
|
|
v0 := b.NewValue0(v.Line, OpAMD64TESTB, TypeInvalid)
|
|
v0.Type = TypeFlags
|
|
v0.AddArg(cond)
|
|
v0.AddArg(cond)
|
|
b.Control = v0
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end012351592edfc708bd3181d7e53f3993
|
|
end012351592edfc708bd3181d7e53f3993:
|
|
;
|
|
case BlockAMD64LE:
|
|
// match: (LE (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (GE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end0d49d7d087fe7578e8015cf13dae37e3
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64GE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end0d49d7d087fe7578e8015cf13dae37e3
|
|
end0d49d7d087fe7578e8015cf13dae37e3:
|
|
;
|
|
case BlockAMD64LT:
|
|
// match: (LT (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (GT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end6a408cde0fee0ae7b7da0443c8d902bf
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64GT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end6a408cde0fee0ae7b7da0443c8d902bf
|
|
end6a408cde0fee0ae7b7da0443c8d902bf:
|
|
;
|
|
case BlockAMD64NE:
|
|
// match: (NE (TESTB (SETL cmp)) yes no)
|
|
// cond:
|
|
// result: (LT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64TESTB {
|
|
goto end0b9ca165d6b395de676eebef94bc62f7
|
|
}
|
|
if v.Args[0].Op != OpAMD64SETL {
|
|
goto end0b9ca165d6b395de676eebef94bc62f7
|
|
}
|
|
cmp := v.Args[0].Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64LT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end0b9ca165d6b395de676eebef94bc62f7
|
|
end0b9ca165d6b395de676eebef94bc62f7:
|
|
;
|
|
// match: (NE (TESTB (SETLE cmp)) yes no)
|
|
// cond:
|
|
// result: (LE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64TESTB {
|
|
goto endaaba0ee4d0ff8c66a1c3107d2a14c4bc
|
|
}
|
|
if v.Args[0].Op != OpAMD64SETLE {
|
|
goto endaaba0ee4d0ff8c66a1c3107d2a14c4bc
|
|
}
|
|
cmp := v.Args[0].Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64LE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endaaba0ee4d0ff8c66a1c3107d2a14c4bc
|
|
endaaba0ee4d0ff8c66a1c3107d2a14c4bc:
|
|
;
|
|
// match: (NE (TESTB (SETG cmp)) yes no)
|
|
// cond:
|
|
// result: (GT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64TESTB {
|
|
goto end1b689463137526b36ba9ceed1e76e512
|
|
}
|
|
if v.Args[0].Op != OpAMD64SETG {
|
|
goto end1b689463137526b36ba9ceed1e76e512
|
|
}
|
|
cmp := v.Args[0].Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64GT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end1b689463137526b36ba9ceed1e76e512
|
|
end1b689463137526b36ba9ceed1e76e512:
|
|
;
|
|
// match: (NE (TESTB (SETGE cmp)) yes no)
|
|
// cond:
|
|
// result: (GE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64TESTB {
|
|
goto end99eefee595c658b997f41577ed853c2e
|
|
}
|
|
if v.Args[0].Op != OpAMD64SETGE {
|
|
goto end99eefee595c658b997f41577ed853c2e
|
|
}
|
|
cmp := v.Args[0].Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64GE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end99eefee595c658b997f41577ed853c2e
|
|
end99eefee595c658b997f41577ed853c2e:
|
|
;
|
|
// match: (NE (TESTB (SETEQ cmp)) yes no)
|
|
// cond:
|
|
// result: (EQ cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64TESTB {
|
|
goto end371b67d3d63e9b92d848b09c3324e8b9
|
|
}
|
|
if v.Args[0].Op != OpAMD64SETEQ {
|
|
goto end371b67d3d63e9b92d848b09c3324e8b9
|
|
}
|
|
cmp := v.Args[0].Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64EQ
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end371b67d3d63e9b92d848b09c3324e8b9
|
|
end371b67d3d63e9b92d848b09c3324e8b9:
|
|
;
|
|
// match: (NE (TESTB (SETNE cmp)) yes no)
|
|
// cond:
|
|
// result: (NE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64TESTB {
|
|
goto endd245f2aac2191d32e57cd2e321daa453
|
|
}
|
|
if v.Args[0].Op != OpAMD64SETNE {
|
|
goto endd245f2aac2191d32e57cd2e321daa453
|
|
}
|
|
cmp := v.Args[0].Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64NE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endd245f2aac2191d32e57cd2e321daa453
|
|
endd245f2aac2191d32e57cd2e321daa453:
|
|
;
|
|
// match: (NE (TESTB (SETB cmp)) yes no)
|
|
// cond:
|
|
// result: (ULT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64TESTB {
|
|
goto end90c4bec851e734d37457d611b1a5ff28
|
|
}
|
|
if v.Args[0].Op != OpAMD64SETB {
|
|
goto end90c4bec851e734d37457d611b1a5ff28
|
|
}
|
|
cmp := v.Args[0].Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64ULT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end90c4bec851e734d37457d611b1a5ff28
|
|
end90c4bec851e734d37457d611b1a5ff28:
|
|
;
|
|
// match: (NE (TESTB (SETBE cmp)) yes no)
|
|
// cond:
|
|
// result: (ULE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64TESTB {
|
|
goto end3a68a28114e9b89ee0708823386bc1ee
|
|
}
|
|
if v.Args[0].Op != OpAMD64SETBE {
|
|
goto end3a68a28114e9b89ee0708823386bc1ee
|
|
}
|
|
cmp := v.Args[0].Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64ULE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end3a68a28114e9b89ee0708823386bc1ee
|
|
end3a68a28114e9b89ee0708823386bc1ee:
|
|
;
|
|
// match: (NE (TESTB (SETA cmp)) yes no)
|
|
// cond:
|
|
// result: (UGT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64TESTB {
|
|
goto end16496f57185756e960d536b057c776c0
|
|
}
|
|
if v.Args[0].Op != OpAMD64SETA {
|
|
goto end16496f57185756e960d536b057c776c0
|
|
}
|
|
cmp := v.Args[0].Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64UGT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end16496f57185756e960d536b057c776c0
|
|
end16496f57185756e960d536b057c776c0:
|
|
;
|
|
// match: (NE (TESTB (SETAE cmp)) yes no)
|
|
// cond:
|
|
// result: (UGE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64TESTB {
|
|
goto endbd122fd599aeb9e60881a0fa735e2fde
|
|
}
|
|
if v.Args[0].Op != OpAMD64SETAE {
|
|
goto endbd122fd599aeb9e60881a0fa735e2fde
|
|
}
|
|
cmp := v.Args[0].Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64UGE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endbd122fd599aeb9e60881a0fa735e2fde
|
|
endbd122fd599aeb9e60881a0fa735e2fde:
|
|
;
|
|
// match: (NE (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (NE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end713001aba794e50b582fbff930e110af
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64NE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end713001aba794e50b582fbff930e110af
|
|
end713001aba794e50b582fbff930e110af:
|
|
;
|
|
case BlockAMD64UGE:
|
|
// match: (UGE (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (ULE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto ende3e4ddc183ca1a46598b11c2d0d13966
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64ULE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto ende3e4ddc183ca1a46598b11c2d0d13966
|
|
ende3e4ddc183ca1a46598b11c2d0d13966:
|
|
;
|
|
case BlockAMD64UGT:
|
|
// match: (UGT (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (ULT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end49818853af2e5251175d06c62768cae7
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64ULT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end49818853af2e5251175d06c62768cae7
|
|
end49818853af2e5251175d06c62768cae7:
|
|
;
|
|
case BlockAMD64ULE:
|
|
// match: (ULE (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (UGE cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto endd6698aac0d67261293b558c95ea17b4f
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64UGE
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto endd6698aac0d67261293b558c95ea17b4f
|
|
endd6698aac0d67261293b558c95ea17b4f:
|
|
;
|
|
case BlockAMD64ULT:
|
|
// match: (ULT (InvertFlags cmp) yes no)
|
|
// cond:
|
|
// result: (UGT cmp yes no)
|
|
{
|
|
v := b.Control
|
|
if v.Op != OpAMD64InvertFlags {
|
|
goto end35105dbc9646f02577167e45ae2f2fd2
|
|
}
|
|
cmp := v.Args[0]
|
|
yes := b.Succs[0]
|
|
no := b.Succs[1]
|
|
b.Kind = BlockAMD64UGT
|
|
b.Control = cmp
|
|
b.Succs[0] = yes
|
|
b.Succs[1] = no
|
|
return true
|
|
}
|
|
goto end35105dbc9646f02577167e45ae2f2fd2
|
|
end35105dbc9646f02577167e45ae2f2fd2:
|
|
}
|
|
return false
|
|
}
|