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1cc624fd62 | ||
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2e60916f6e |
113
src/cmd/asm/internal/asm/testdata/riscv64.s
vendored
113
src/cmd/asm/internal/asm/testdata/riscv64.s
vendored
@ -1161,6 +1161,119 @@ start:
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VFNCVTRODFFW V2, V3 // d7912a4a
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VFNCVTRODFFW V2, V0, V3 // d7912a48
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// 31.14.1: Vector Single-Width Integer Reduction Instructions
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VREDSUMVS V1, V2, V3 // d7a12002
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VREDSUMVS V1, V2, V0, V3 // d7a12000
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VREDMAXUVS V1, V2, V3 // d7a1201a
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VREDMAXUVS V1, V2, V0, V3 // d7a12018
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VREDMAXVS V1, V2, V3 // d7a1201e
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VREDMAXVS V1, V2, V0, V3 // d7a1201c
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VREDMINUVS V1, V2, V3 // d7a12012
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VREDMINUVS V1, V2, V0, V3 // d7a12010
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VREDMINVS V1, V2, V3 // d7a12016
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VREDMINVS V1, V2, V0, V3 // d7a12014
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VREDANDVS V1, V2, V3 // d7a12006
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VREDANDVS V1, V2, V0, V3 // d7a12004
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VREDORVS V1, V2, V3 // d7a1200a
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VREDORVS V1, V2, V0, V3 // d7a12008
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VREDXORVS V1, V2, V3 // d7a1200e
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VREDXORVS V1, V2, V0, V3 // d7a1200c
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// 31.14.2: Vector Widening Integer Reduction Instructions
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VWREDSUMUVS V1, V2, V3 // d78120c2
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VWREDSUMUVS V1, V2, V0, V3 // d78120c0
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VWREDSUMVS V1, V2, V3 // d78120c6
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VWREDSUMVS V1, V2, V0, V3 // d78120c4
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// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
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VFREDOSUMVS V1, V2, V3 // d791200e
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VFREDOSUMVS V1, V2, V0, V3 // d791200c
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VFREDUSUMVS V1, V2, V3 // d7912006
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VFREDUSUMVS V1, V2, V0, V3 // d7912004
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VFREDMAXVS V1, V2, V3 // d791201e
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VFREDMAXVS V1, V2, V0, V3 // d791201c
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VFREDMINVS V1, V2, V3 // d7912016
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VFREDMINVS V1, V2, V0, V3 // d7912014
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// 31.14.4: Vector Widening Floating-Point Reduction Instructions
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VFWREDOSUMVS V1, V2, V3 // d79120ce
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VFWREDOSUMVS V1, V2, V0, V3 // d79120cc
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VFWREDUSUMVS V1, V2, V3 // d79120c6
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VFWREDUSUMVS V1, V2, V0, V3 // d79120c4
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// 31.15: Vector Mask Instructions
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VMANDMM V1, V2, V3 // d7a12066
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VMNANDMM V1, V2, V3 // d7a12076
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VMANDNMM V1, V2, V3 // d7a12062
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VMXORMM V1, V2, V3 // d7a1206e
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VMORMM V1, V2, V3 // d7a1206a
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VMNORMM V1, V2, V3 // d7a1207a
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VMORNMM V1, V2, V3 // d7a12072
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VMXNORMM V1, V2, V3 // d7a1207e
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VMMVM V2, V3 // d7212166
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VMCLRM V3 // d7a1316e
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VMSETM V3 // d7a1317e
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VMNOTM V2, V3 // d7212176
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VCPOPM V2, X10 // 57252842
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VCPOPM V2, V0, X10 // 57252840
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VFIRSTM V2, X10 // 57a52842
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VFIRSTM V2, V0, X10 // 57a52840
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VMSBFM V2, V3 // d7a12052
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VMSBFM V2, V0, V3 // d7a12050
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VMSIFM V2, V3 // d7a12152
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VMSIFM V2, V0, V3 // d7a12150
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VMSOFM V2, V3 // d7212152
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VMSOFM V2, V0, V3 // d7212150
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VIOTAM V2, V3 // d7212852
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VIOTAM V2, V0, V3 // d7212850
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VIDV V3 // d7a10852
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VIDV V0, V3 // d7a10850
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// 31.16.1: Integer Scalar Move Instructions
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VMVXS V2, X10 // 57252042
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||||
VMVSX X10, V2 // 57610542
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||||
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||||
// 31.16.2: Floating-Point Scalar Move Instructions
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VFMVFS V2, F10 // 57152042
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VFMVSF F10, V2 // 57510542
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// 31.16.3: Vector Slide Instructions
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VSLIDEUPVX X10, V2, V3 // d741253a
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VSLIDEUPVX X10, V2, V0, V3 // d7412538
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VSLIDEUPVI $16, V2, V3 // d731283a
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VSLIDEUPVI $16, V2, V0, V3 // d7312838
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||||
VSLIDEDOWNVX X10, V2, V3 // d741253e
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||||
VSLIDEDOWNVX X10, V2, V0, V3 // d741253c
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||||
VSLIDEDOWNVI $16, V2, V3 // d731283e
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||||
VSLIDEDOWNVI $16, V2, V0, V3 // d731283c
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VSLIDE1UPVX X10, V2, V3 // d761253a
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||||
VSLIDE1UPVX X10, V2, V0, V3 // d7612538
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VFSLIDE1UPVF F10, V2, V3 // d751253a
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VFSLIDE1UPVF F10, V2, V0, V3 // d7512538
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||||
VSLIDE1DOWNVX X10, V2, V3 // d761253e
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||||
VSLIDE1DOWNVX X10, V2, V0, V3 // d761253c
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||||
VFSLIDE1DOWNVF F10, V2, V3 // d751253e
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||||
VFSLIDE1DOWNVF F10, V2, V0, V3 // d751253c
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||||
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// 31.16.4: Vector Register Gather Instructions
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||||
VRGATHERVV V1, V2, V3 // d7812032
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VRGATHERVV V1, V2, V0, V3 // d7812030
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VRGATHEREI16VV V1, V2, V3 // d781203a
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VRGATHEREI16VV V1, V2, V0, V3 // d7812038
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||||
VRGATHERVX X10, V2, V3 // d7412532
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||||
VRGATHERVX X10, V2, V0, V3 // d7412530
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||||
VRGATHERVI $16, V2, V3 // d7312832
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||||
VRGATHERVI $16, V2, V0, V3 // d7312830
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||||
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||||
// 31.16.5: Vector Compress Instruction
|
||||
VCOMPRESSVM V1, V2, V3 // d7a1205e
|
||||
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||||
// 31.16.6: Whole Vector Register Move
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||||
VMV1RV V2, V1 // d730209e
|
||||
VMV2RV V12, V10 // 57b5c09e
|
||||
VMV4RV V8, V4 // 57b2819e
|
||||
VMV8RV V8, V0 // 57b0839e
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||||
|
||||
//
|
||||
// Privileged ISA
|
||||
//
|
||||
|
||||
33
src/cmd/asm/internal/asm/testdata/riscv64error.s
vendored
33
src/cmd/asm/internal/asm/testdata/riscv64error.s
vendored
@ -347,5 +347,38 @@ TEXT errors(SB),$0
|
||||
VFNCVTFXW V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VFNCVTFFW V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VFNCVTRODFFW V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VREDSUMVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VREDMAXUVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VREDMAXVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VREDMINUVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VREDMINVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VREDANDVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VREDORVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VREDXORVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VWREDSUMUVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VWREDSUMVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VFREDOSUMVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VFREDUSUMVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VFREDMAXVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VFREDMINVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VFWREDOSUMVS V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VCPOPM V2, V4, X10 // ERROR "invalid vector mask register"
|
||||
VFIRSTM V2, V4, X10 // ERROR "invalid vector mask register"
|
||||
VMSBFM V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VMSIFM V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VMSOFM V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VIOTAM V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VSLIDEUPVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VSLIDEUPVI $16, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VSLIDEDOWNVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VSLIDEDOWNVI $16, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VSLIDE1UPVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VFSLIDE1UPVF F10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VSLIDE1DOWNVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VFSLIDE1DOWNVF F10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VRGATHERVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VRGATHEREI16VV V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VRGATHERVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VRGATHERVI $16, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
|
||||
RET
|
||||
|
||||
@ -364,5 +364,68 @@ TEXT validation(SB),$0
|
||||
VFNCVTFXW X10, V3 // ERROR "expected vector register in vs2 position"
|
||||
VFNCVTFFW X10, V3 // ERROR "expected vector register in vs2 position"
|
||||
VFNCVTRODFFW X10, V3 // ERROR "expected vector register in vs2 position"
|
||||
VREDSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VREDMAXUVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VREDMAXVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VREDMINUVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VREDMINVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VREDANDVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VREDORVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VREDXORVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VWREDSUMUVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VWREDSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VFREDOSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VFREDUSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VFREDMAXVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VFREDMINVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VFWREDOSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VFWREDUSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VMANDMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
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VMNANDMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
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VMANDNMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
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VMXORMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VMORMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VMNORMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VMORNMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VMXNORMM X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VMMVM V3, X10 // ERROR "expected vector register in vd position"
|
||||
VMNOTM V3, X10 // ERROR "expected vector register in vd position"
|
||||
VCPOPM V2, V1 // ERROR "expected integer register in rd position"
|
||||
VCPOPM X11, X10 // ERROR "expected vector register in vs2 position"
|
||||
VFIRSTM V2, V1 // ERROR "expected integer register in rd position"
|
||||
VFIRSTM X11, X10 // ERROR "expected vector register in vs2 position"
|
||||
VMSBFM X10, V3 // ERROR "expected vector register in vs2 position"
|
||||
VMSIFM X10, V3 // ERROR "expected vector register in vs2 position"
|
||||
VMSOFM X10, V3 // ERROR "expected vector register in vs2 position"
|
||||
VIOTAM X10, V3 // ERROR "expected vector register in vs2 position"
|
||||
VIDV X10 // ERROR "expected vector register in vd position"
|
||||
VMVXS X11, X10 // ERROR "expected vector register in vs2 position"
|
||||
VMVXS V2, V1 // ERROR "expected integer register in rd position"
|
||||
VMVSX X11, X10 // ERROR "expected vector register in vd position"
|
||||
VMVSX V2, V1 // ERROR "expected integer register in rs2 position"
|
||||
VFMVFS X10, F10 // ERROR "expected vector register in vs2 position"
|
||||
VFMVFS V2, V1 // ERROR "expected float register in rd position"
|
||||
VFMVSF X10, V2 // ERROR "expected float register in rs2 position"
|
||||
VFMVSF V2, V1 // ERROR "expected float register in rs2 position"
|
||||
VSLIDEUPVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
|
||||
VSLIDEUPVI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]"
|
||||
VSLIDEUPVI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]"
|
||||
VSLIDEDOWNVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
|
||||
VSLIDEDOWNVI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]"
|
||||
VSLIDEDOWNVI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]"
|
||||
VSLIDE1UPVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
|
||||
VFSLIDE1UPVF V1, V2, V3 // ERROR "expected float register in rs1 position"
|
||||
VSLIDE1DOWNVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
|
||||
VFSLIDE1DOWNVF V1, V2, V3 // ERROR "expected float register in rs1 position"
|
||||
VRGATHERVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VRGATHEREI16VV X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VRGATHERVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
|
||||
VRGATHERVI $-1, V2, V3 // ERROR "unsigned immediate -1 must be in range [0, 31]"
|
||||
VRGATHERVI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]"
|
||||
VCOMPRESSVM X10, V2, V3 // ERROR "expected vector register in vs1 position"
|
||||
VMV1RV X10, V1 // ERROR "expected vector register in vs2 position"
|
||||
VMV2RV X10, V10 // ERROR "expected vector register in vs2 position"
|
||||
VMV4RV X10, V4 // ERROR "expected vector register in vs2 position"
|
||||
VMV8RV X10, V0 // ERROR "expected vector register in vs2 position"
|
||||
|
||||
RET
|
||||
|
||||
@ -652,12 +652,16 @@ var Anames = []string{
|
||||
"SNEZ",
|
||||
"VFABSV",
|
||||
"VFNEGV",
|
||||
"VMFGEVV",
|
||||
"VMFGTVV",
|
||||
"VL1RV",
|
||||
"VL2RV",
|
||||
"VL4RV",
|
||||
"VL8RV",
|
||||
"VMCLRM",
|
||||
"VMFGEVV",
|
||||
"VMFGTVV",
|
||||
"VMMVM",
|
||||
"VMNOTM",
|
||||
"VMSETM",
|
||||
"VMSGEUVI",
|
||||
"VMSGEUVV",
|
||||
"VMSGEVI",
|
||||
|
||||
@ -1180,12 +1180,16 @@ const (
|
||||
ASNEZ
|
||||
AVFABSV
|
||||
AVFNEGV
|
||||
AVMFGEVV
|
||||
AVMFGTVV
|
||||
AVL1RV
|
||||
AVL2RV
|
||||
AVL4RV
|
||||
AVL8RV
|
||||
AVMCLRM
|
||||
AVMFGEVV
|
||||
AVMFGTVV
|
||||
AVMMVM
|
||||
AVMNOTM
|
||||
AVMSETM
|
||||
AVMSGEUVI
|
||||
AVMSGEUVV
|
||||
AVMSGEVI
|
||||
|
||||
@ -1307,6 +1307,13 @@ func validateRFI(ctxt *obj.Link, ins *instruction) {
|
||||
wantNoneReg(ctxt, ins, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRFV(ctxt *obj.Link, ins *instruction) {
|
||||
wantVectorReg(ctxt, ins, "vd", ins.rd)
|
||||
wantNoneReg(ctxt, ins, "rs1", ins.rs1)
|
||||
wantFloatReg(ctxt, ins, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRFF(ctxt *obj.Link, ins *instruction) {
|
||||
wantFloatReg(ctxt, ins, "rd", ins.rd)
|
||||
wantNoneReg(ctxt, ins, "rs1", ins.rs1)
|
||||
@ -1321,6 +1328,20 @@ func validateRIF(ctxt *obj.Link, ins *instruction) {
|
||||
wantNoneReg(ctxt, ins, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRIV(ctxt *obj.Link, ins *instruction) {
|
||||
wantVectorReg(ctxt, ins, "vd", ins.rd)
|
||||
wantNoneReg(ctxt, ins, "rs1", ins.rs1)
|
||||
wantIntReg(ctxt, ins, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRVF(ctxt *obj.Link, ins *instruction) {
|
||||
wantFloatReg(ctxt, ins, "rd", ins.rd)
|
||||
wantNoneReg(ctxt, ins, "rs1", ins.rs1)
|
||||
wantVectorReg(ctxt, ins, "vs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRVFV(ctxt *obj.Link, ins *instruction) {
|
||||
wantVectorReg(ctxt, ins, "vd", ins.rd)
|
||||
wantFloatReg(ctxt, ins, "rs1", ins.rs1)
|
||||
@ -1328,6 +1349,13 @@ func validateRVFV(ctxt *obj.Link, ins *instruction) {
|
||||
wantNoneReg(ctxt, ins, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRVI(ctxt *obj.Link, ins *instruction) {
|
||||
wantIntReg(ctxt, ins, "rd", ins.rd)
|
||||
wantNoneReg(ctxt, ins, "rs1", ins.rs1)
|
||||
wantVectorReg(ctxt, ins, "vs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRVIV(ctxt *obj.Link, ins *instruction) {
|
||||
wantVectorReg(ctxt, ins, "vd", ins.rd)
|
||||
wantIntReg(ctxt, ins, "rs1", ins.rs1)
|
||||
@ -1569,14 +1597,30 @@ func encodeRFF(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, regF(ins.rs2), 0, regF(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
||||
func encodeRFV(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, regF(ins.rs2), 0, regV(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
||||
func encodeRIF(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, regI(ins.rs2), 0, regF(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
||||
func encodeRIV(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, regI(ins.rs2), 0, regV(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
||||
func encodeRVF(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, 0, regV(ins.rs2), regF(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
||||
func encodeRVFV(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, regF(ins.rs1), regV(ins.rs2), regV(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
||||
func encodeRVI(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, 0, regV(ins.rs2), regI(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
||||
func encodeRVIV(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, regI(ins.rs1), regV(ins.rs2), regV(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
@ -1878,9 +1922,13 @@ var (
|
||||
rFFFFEncoding = encoding{encode: encodeRFFFF, validate: validateRFFFF, length: 4}
|
||||
rFFIEncoding = encoding{encode: encodeRFFI, validate: validateRFFI, length: 4}
|
||||
rFIEncoding = encoding{encode: encodeRFI, validate: validateRFI, length: 4}
|
||||
rFVEncoding = encoding{encode: encodeRFV, validate: validateRFV, length: 4}
|
||||
rIFEncoding = encoding{encode: encodeRIF, validate: validateRIF, length: 4}
|
||||
rIVEncoding = encoding{encode: encodeRIV, validate: validateRIV, length: 4}
|
||||
rFFEncoding = encoding{encode: encodeRFF, validate: validateRFF, length: 4}
|
||||
rVFEncoding = encoding{encode: encodeRVF, validate: validateRVF, length: 4}
|
||||
rVFVEncoding = encoding{encode: encodeRVFV, validate: validateRVFV, length: 4}
|
||||
rVIEncoding = encoding{encode: encodeRVI, validate: validateRVI, length: 4}
|
||||
rVIVEncoding = encoding{encode: encodeRVIV, validate: validateRVIV, length: 4}
|
||||
rVVEncoding = encoding{encode: encodeRVV, validate: validateRVV, length: 4}
|
||||
rVViEncoding = encoding{encode: encodeRVVi, validate: validateRVVi, length: 4}
|
||||
@ -2585,6 +2633,80 @@ var instructions = [ALAST & obj.AMask]instructionData{
|
||||
AVFNCVTFFW & obj.AMask: {enc: rVVEncoding},
|
||||
AVFNCVTRODFFW & obj.AMask: {enc: rVVEncoding},
|
||||
|
||||
// 31.14.1: Vector Single-Width Integer Reduction Instructions
|
||||
AVREDSUMVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVREDMAXUVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVREDMAXVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVREDMINUVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVREDMINVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVREDANDVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVREDORVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVREDXORVS & obj.AMask: {enc: rVVVEncoding},
|
||||
|
||||
// 31.14.2: Vector Widening Integer Reduction Instructions
|
||||
AVWREDSUMUVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVWREDSUMVS & obj.AMask: {enc: rVVVEncoding},
|
||||
|
||||
// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
|
||||
AVFREDOSUMVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVFREDUSUMVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVFREDMAXVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVFREDMINVS & obj.AMask: {enc: rVVVEncoding},
|
||||
|
||||
// 31.14.4: Vector Widening Floating-Point Reduction Instructions
|
||||
AVFWREDOSUMVS & obj.AMask: {enc: rVVVEncoding},
|
||||
AVFWREDUSUMVS & obj.AMask: {enc: rVVVEncoding},
|
||||
|
||||
// 31.15: Vector Mask Instructions
|
||||
AVMANDMM & obj.AMask: {enc: rVVVEncoding},
|
||||
AVMNANDMM & obj.AMask: {enc: rVVVEncoding},
|
||||
AVMANDNMM & obj.AMask: {enc: rVVVEncoding},
|
||||
AVMXORMM & obj.AMask: {enc: rVVVEncoding},
|
||||
AVMORMM & obj.AMask: {enc: rVVVEncoding},
|
||||
AVMNORMM & obj.AMask: {enc: rVVVEncoding},
|
||||
AVMORNMM & obj.AMask: {enc: rVVVEncoding},
|
||||
AVMXNORMM & obj.AMask: {enc: rVVVEncoding},
|
||||
AVCPOPM & obj.AMask: {enc: rVIEncoding},
|
||||
AVFIRSTM & obj.AMask: {enc: rVIEncoding},
|
||||
AVMSBFM & obj.AMask: {enc: rVVEncoding},
|
||||
AVMSIFM & obj.AMask: {enc: rVVEncoding},
|
||||
AVMSOFM & obj.AMask: {enc: rVVEncoding},
|
||||
AVIOTAM & obj.AMask: {enc: rVVEncoding},
|
||||
AVIDV & obj.AMask: {enc: rVVEncoding},
|
||||
|
||||
// 31.16.1: Integer Scalar Move Instructions
|
||||
AVMVXS & obj.AMask: {enc: rVIEncoding},
|
||||
AVMVSX & obj.AMask: {enc: rIVEncoding},
|
||||
|
||||
// 31.16.2: Floating-Point Scalar Move Instructions
|
||||
AVFMVFS & obj.AMask: {enc: rVFEncoding},
|
||||
AVFMVSF & obj.AMask: {enc: rFVEncoding},
|
||||
|
||||
// 31.16.3: Vector Slide Instructions
|
||||
AVSLIDEUPVX & obj.AMask: {enc: rVIVEncoding},
|
||||
AVSLIDEUPVI & obj.AMask: {enc: rVVuEncoding},
|
||||
AVSLIDEDOWNVX & obj.AMask: {enc: rVIVEncoding},
|
||||
AVSLIDEDOWNVI & obj.AMask: {enc: rVVuEncoding},
|
||||
AVSLIDE1UPVX & obj.AMask: {enc: rVIVEncoding},
|
||||
AVFSLIDE1UPVF & obj.AMask: {enc: rVFVEncoding},
|
||||
AVSLIDE1DOWNVX & obj.AMask: {enc: rVIVEncoding},
|
||||
AVFSLIDE1DOWNVF & obj.AMask: {enc: rVFVEncoding},
|
||||
|
||||
// 31.16.4: Vector Register Gather Instructions
|
||||
AVRGATHERVV & obj.AMask: {enc: rVVVEncoding},
|
||||
AVRGATHEREI16VV & obj.AMask: {enc: rVVVEncoding},
|
||||
AVRGATHERVX & obj.AMask: {enc: rVIVEncoding},
|
||||
AVRGATHERVI & obj.AMask: {enc: rVVuEncoding},
|
||||
|
||||
// 31.16.5: Vector Compress Instruction
|
||||
AVCOMPRESSVM & obj.AMask: {enc: rVVVEncoding},
|
||||
|
||||
// 31.16.6: Whole Vector Register Move
|
||||
AVMV1RV & obj.AMask: {enc: rVVEncoding},
|
||||
AVMV2RV & obj.AMask: {enc: rVVEncoding},
|
||||
AVMV4RV & obj.AMask: {enc: rVVEncoding},
|
||||
AVMV8RV & obj.AMask: {enc: rVVEncoding},
|
||||
|
||||
//
|
||||
// Privileged ISA
|
||||
//
|
||||
@ -3578,7 +3700,11 @@ func instructionsForProg(p *obj.Prog) []*instruction {
|
||||
AVFMULVV, AVFMULVF, AVFDIVVV, AVFDIVVF, AVFRDIVVF, AVFWMULVV, AVFWMULVF,
|
||||
AVFMINVV, AVFMINVF, AVFMAXVV, AVFMAXVF,
|
||||
AVFSGNJVV, AVFSGNJVF, AVFSGNJNVV, AVFSGNJNVF, AVFSGNJXVV, AVFSGNJXVF,
|
||||
AVMFEQVV, AVMFEQVF, AVMFNEVV, AVMFNEVF, AVMFLTVV, AVMFLTVF, AVMFLEVV, AVMFLEVF, AVMFGTVF, AVMFGEVF:
|
||||
AVMFEQVV, AVMFEQVF, AVMFNEVV, AVMFNEVF, AVMFLTVV, AVMFLTVF, AVMFLEVV, AVMFLEVF, AVMFGTVF, AVMFGEVF,
|
||||
AVREDSUMVS, AVREDMAXUVS, AVREDMAXVS, AVREDMINUVS, AVREDMINVS, AVREDANDVS, AVREDORVS, AVREDXORVS,
|
||||
AVWREDSUMUVS, AVWREDSUMVS, AVFREDOSUMVS, AVFREDUSUMVS, AVFREDMAXVS, AVFREDMINVS, AVFWREDOSUMVS, AVFWREDUSUMVS,
|
||||
AVSLIDEUPVX, AVSLIDEDOWNVX, AVSLIDE1UPVX, AVFSLIDE1UPVF, AVSLIDE1DOWNVX, AVFSLIDE1DOWNVF,
|
||||
AVRGATHERVV, AVRGATHEREI16VV, AVRGATHERVX:
|
||||
// Set mask bit
|
||||
switch {
|
||||
case ins.rs3 == obj.REG_NONE:
|
||||
@ -3600,7 +3726,7 @@ func instructionsForProg(p *obj.Prog) []*instruction {
|
||||
ins.rd, ins.rs1, ins.rs2, ins.rs3 = uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), obj.REG_NONE
|
||||
|
||||
case AVADDVI, AVRSUBVI, AVANDVI, AVORVI, AVXORVI, AVMSEQVI, AVMSNEVI, AVMSLEUVI, AVMSLEVI, AVMSGTUVI, AVMSGTVI,
|
||||
AVSLLVI, AVSRLVI, AVSRAVI, AVNSRLWI, AVNSRAWI:
|
||||
AVSLLVI, AVSRLVI, AVSRAVI, AVNSRLWI, AVNSRAWI, AVRGATHERVI, AVSLIDEUPVI, AVSLIDEDOWNVI:
|
||||
// Set mask bit
|
||||
switch {
|
||||
case ins.rs3 == obj.REG_NONE:
|
||||
@ -3739,6 +3865,47 @@ func instructionsForProg(p *obj.Prog) []*instruction {
|
||||
ins.as = AVFSGNJNVV
|
||||
}
|
||||
ins.rd, ins.rs1, ins.rs2 = uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)
|
||||
|
||||
case AVMANDMM, AVMNANDMM, AVMANDNMM, AVMXORMM, AVMORMM, AVMNORMM, AVMORNMM, AVMXNORMM, AVMMVM, AVMNOTM, AVCOMPRESSVM:
|
||||
ins.rd, ins.rs1, ins.rs2 = uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)
|
||||
switch ins.as {
|
||||
case AVMMVM:
|
||||
ins.as, ins.rs2 = AVMANDMM, ins.rs1
|
||||
case AVMNOTM:
|
||||
ins.as, ins.rs2 = AVMNANDMM, ins.rs1
|
||||
}
|
||||
|
||||
case AVMCLRM, AVMSETM:
|
||||
ins.rd, ins.rs1, ins.rs2 = uint32(p.From.Reg), uint32(p.From.Reg), uint32(p.From.Reg)
|
||||
switch ins.as {
|
||||
case AVMCLRM:
|
||||
ins.as = AVMXORMM
|
||||
case AVMSETM:
|
||||
ins.as = AVMXNORMM
|
||||
}
|
||||
|
||||
case AVCPOPM, AVFIRSTM, AVMSBFM, AVMSIFM, AVMSOFM, AVIOTAM:
|
||||
// Set mask bit
|
||||
switch {
|
||||
case ins.rs1 == obj.REG_NONE:
|
||||
ins.funct7 |= 1 // unmasked
|
||||
case ins.rs1 != REG_V0:
|
||||
p.Ctxt.Diag("%v: invalid vector mask register", p)
|
||||
}
|
||||
ins.rs1 = obj.REG_NONE
|
||||
|
||||
case AVIDV:
|
||||
// Set mask bit
|
||||
switch {
|
||||
case ins.rd == obj.REG_NONE:
|
||||
ins.funct7 |= 1 // unmasked
|
||||
case ins.rd != obj.REG_NONE && ins.rs2 != REG_V0:
|
||||
p.Ctxt.Diag("%v: invalid vector mask register", p)
|
||||
}
|
||||
if ins.rd == obj.REG_NONE {
|
||||
ins.rd = uint32(p.From.Reg)
|
||||
}
|
||||
ins.rs1, ins.rs2 = obj.REG_NONE, REG_V0
|
||||
}
|
||||
|
||||
for _, ins := range inss {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user