go/parser: use non-adjusted position while parsing CommentGroups

Line directives should not affect the way Comments get grouped
into CommentGroups.

Change-Id: I9aa4b558cb1333b32be692e8720291d0e6961cae
GitHub-Last-Rev: de867b27bff28983716ba9126329d75f456a2b5a
GitHub-Pull-Request: golang/go#69133
Reviewed-on: https://go-review.googlesource.com/c/go/+/609515
Reviewed-by: Alan Donovan <adonovan@google.com>
Reviewed-by: Carlos Amedee <carlos@golang.org>
Auto-Submit: Alan Donovan <adonovan@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>

VERSION

@@ -1,2 +0,0 @@
-go1.24.2
-time 2025-03-26T19:09:39Z

api/next/46771.txt

@@ -0,0 +1 @@
+pkg mime/multipart, func FileContentDisposition(string, string) string #46771

api/next/49580.txt

@@ -0,0 +1,8 @@
+pkg io/fs, func Lstat(FS, string) (FileInfo, error) #49580
+pkg io/fs, func ReadLink(FS, string) (string, error) #49580
+pkg io/fs, type ReadLinkFS interface { Lstat, Open, ReadLink } #49580
+pkg io/fs, type ReadLinkFS interface, Lstat(string) (FileInfo, error) #49580
+pkg io/fs, type ReadLinkFS interface, Open(string) (File, error) #49580
+pkg io/fs, type ReadLinkFS interface, ReadLink(string) (string, error) #49580
+pkg testing/fstest, method (MapFS) Lstat(string) (fs.FileInfo, error) #49580
+pkg testing/fstest, method (MapFS) ReadLink(string) (string, error) #49580

api/next/63796.txt

@@ -0,0 +1 @@
+pkg sync, method (*WaitGroup) Go(func()) #63769

api/next/67002.txt

@@ -0,0 +1,8 @@
+pkg os, method (*Root) Chmod(string, fs.FileMode) error #67002
+pkg os, method (*Root) Chown(string, int, int) error #67002
+pkg os, method (*Root) Chtimes(string, time.Time, time.Time) error #67002
+pkg os, method (*Root) Lchown(string, int, int) error #67002
+pkg os, method (*Root) Link(string, string) error #67002
+pkg os, method (*Root) Readlink(string) (string, error) #67002
+pkg os, method (*Root) Rename(string, string) error #67002
+pkg os, method (*Root) Symlink(string, string) error #67002

api/next/67516.txt

@@ -0,0 +1 @@
+pkg crypto/tls, type ConnectionState struct, CurveID CurveID #67516

api/next/70250.txt

@@ -0,0 +1,17 @@
+pkg go/types, const FieldVar = 6 #70250
+pkg go/types, const FieldVar VarKind #70250
+pkg go/types, const LocalVar = 2 #70250
+pkg go/types, const LocalVar VarKind #70250
+pkg go/types, const PackageVar = 1 #70250
+pkg go/types, const PackageVar VarKind #70250
+pkg go/types, const ParamVar = 4 #70250
+pkg go/types, const ParamVar VarKind #70250
+pkg go/types, const RecvVar = 3 #70250
+pkg go/types, const RecvVar VarKind #70250
+pkg go/types, const ResultVar = 5 #70250
+pkg go/types, const ResultVar VarKind #70250
+pkg go/types, func LookupSelection(Type, bool, *Package, string) (Selection, bool) #70737
+pkg go/types, method (*Var) Kind() VarKind #70250
+pkg go/types, method (*Var) SetKind(VarKind) #70250
+pkg go/types, method (VarKind) String() string #70250
+pkg go/types, type VarKind uint8 #70250

api/next/70780.txt

@@ -0,0 +1,3 @@
+pkg unicode, var CategoryAliases map[string]string #70780
+pkg unicode, var Cn *RangeTable #70780
+pkg unicode, var LC *RangeTable #70780

api/next/71122.txt

@@ -0,0 +1 @@
+pkg go/parser, func ParseDir //deprecated #71122

api/next/72843.txt

@@ -0,0 +1,4 @@
+pkg debug/elf, const PT_RISCV_ATTRIBUTES = 1879048195 #72843
+pkg debug/elf, const PT_RISCV_ATTRIBUTES ProgType #72843
+pkg debug/elf, const SHT_RISCV_ATTRIBUTES = 1879048195 #72843
+pkg debug/elf, const SHT_RISCV_ATTRIBUTES SectionType #72843

codereview.cfg

@@ -1,2 +1 @@
-branch: release-branch.go1.24
-parent-branch: master
+branch: master

doc/go_mem.html

@@ -453,7 +453,7 @@ crash, or do something else.)
 </p>
 
 <p class="rule">
-The <i>k</i>th receive on a channel with capacity <i>C</i> is synchronized before the completion of the <i>k</i>+<i>C</i>th send from that channel completes.
+The <i>k</i>th receive from a channel with capacity <i>C</i> is synchronized before the completion of the <i>k</i>+<i>C</i>th send on that channel.
 </p>
 
 <p>

doc/go_spec.html

@@ -1,6 +1,6 @@
 <!--{
 	"Title": "The Go Programming Language Specification",
-	"Subtitle": "Language version go1.24 (Dec 30, 2024)",
+	"Subtitle": "Language version go1.25 (Feb 25, 2025)",
 	"Path": "/ref/spec"
 }-->
 
@@ -8,8 +8,6 @@
 
 <p>
 This is the reference manual for the Go programming language.
-The pre-Go1.18 version, without generics, can be found
-<a href="/doc/go1.17_spec.html">here</a>.
 For more information and other documents, see <a href="/">go.dev</a>.
 </p>
 
@@ -1858,110 +1856,10 @@ The underlying type of <code>[]B1</code>, <code>B3</code>, and <code>B4</code> i
 The underlying type of <code>P</code> is <code>interface{}</code>.
 </p>
 
-<h3 id="Core_types">Core types</h3>
-
-<p>
-Each non-interface type <code>T</code> has a <i>core type</i>, which is the same as the
-<a href="#Underlying_types">underlying type</a> of <code>T</code>.
-</p>
-
-<p>
-An interface <code>T</code> has a core type if one of the following
-conditions is satisfied:
-</p>
-
-<ol>
-<li>
-There is a single type <code>U</code> which is the <a href="#Underlying_types">underlying type</a>
-of all types in the <a href="#Interface_types">type set</a> of <code>T</code>; or
-</li>
-<li>
-the type set of <code>T</code> contains only <a href="#Channel_types">channel types</a>
-with identical element type <code>E</code>, and all directional channels have the same
-direction.
-</li>
-</ol>
-
-<p>
-No other interfaces have a core type.
-</p>
-
-<p>
-The core type of an interface is, depending on the condition that is satisfied, either:
-</p>
-
-<ol>
-<li>
-the type <code>U</code>; or
-</li>
-<li>
-the type <code>chan E</code> if <code>T</code> contains only bidirectional
-channels, or the type <code>chan&lt;- E</code> or <code>&lt;-chan E</code>
-depending on the direction of the directional channels present.
-</li>
-</ol>
-
-<p>
-By definition, a core type is never a <a href="#Type_definitions">defined type</a>,
-<a href="#Type_parameter_declarations">type parameter</a>, or
-<a href="#Interface_types">interface type</a>.
-</p>
-
-<p>
-Examples of interfaces with core types:
-</p>
-
-<pre>
-type Celsius float32
-type Kelvin  float32
-
-interface{ int }                          // int
-interface{ Celsius|Kelvin }               // float32
-interface{ ~chan int }                    // chan int
-interface{ ~chan int|~chan&lt;- int }        // chan&lt;- int
-interface{ ~[]*data; String() string }    // []*data
-</pre>
-
-<p>
-Examples of interfaces without core types:
-</p>
-
-<pre>
-interface{}                               // no single underlying type
-interface{ Celsius|float64 }              // no single underlying type
-interface{ chan int | chan&lt;- string }     // channels have different element types
-interface{ &lt;-chan int | chan&lt;- int }      // directional channels have different directions
-</pre>
-
-<p>
-Some operations (<a href="#Slice_expressions">slice expressions</a>,
-<a href="#Appending_and_copying_slices"><code>append</code> and <code>copy</code></a>)
-rely on a slightly more loose form of core types which accept byte slices and strings.
-Specifically, if there are exactly two types, <code>[]byte</code> and <code>string</code>,
-which are the underlying types of all types in the type set of interface <code>T</code>,
-the core type of <code>T</code> is called <code>bytestring</code>.
-</p>
-
-<p>
-Examples of interfaces with <code>bytestring</code> core types:
-</p>
-
-<pre>
-interface{ int }                          // int (same as ordinary core type)
-interface{ []byte | string }              // bytestring
-interface{ ~[]byte | myString }           // bytestring
-</pre>
-
-<p>
-Note that <code>bytestring</code> is not a real type; it cannot be used to declare
-variables or compose other types. It exists solely to describe the behavior of some
-operations that read from a sequence of bytes, which may be a byte slice or a string.
-</p>
-
 <h3 id="Type_identity">Type identity</h3>
 
 <p>
-Two types are either <i>identical</i> or <i>different</i>.
+Two types are either <i>identical</i> ("the same") or <i>different</i>.
 </p>
 
 <p>
@@ -3255,7 +3153,8 @@ math.Sin // denotes the Sin function in package math
 <h3 id="Composite_literals">Composite literals</h3>
 
 <p>
-Composite literals construct new composite values each time they are evaluated.
+Composite literals construct new values for structs, arrays, slices, and maps
+each time they are evaluated.
 They consist of the type of the literal followed by a brace-bound list of elements.
 Each element may optionally be preceded by a corresponding key.
 </p>
@@ -3273,10 +3172,14 @@ Element      = Expression | LiteralValue .
 </pre>
 
 <p>
-The LiteralType's <a href="#Core_types">core type</a> <code>T</code>
+Unless the LiteralType is a type parameter,
+its <a href="#Underlying_types">underlying type
 must be a struct, array, slice, or map type
 (the syntax enforces this constraint except when the type is given
 as a TypeName).
+If the LiteralType is a type parameter, all types in its type set
+must have the same underlying type which must be
+a valid composite literal type.
 The types of the elements and keys must be <a href="#Assignability">assignable</a>
 to the respective field, element, and key types of type <code>T</code>;
 there is no additional conversion.
@@ -3461,7 +3364,6 @@ noteFrequency := map[string]float32{
 }
 </pre>
 
-
 <h3 id="Function_literals">Function literals</h3>
 
 <p>
@@ -3934,11 +3836,12 @@ The following rules apply:
 </p>
 
 <p>
-If <code>a</code> is neither a map nor a type parameter:
+If <code>a</code> is neither a map nor a <a href="#Type_parameter_declarations">type parameter</a>:
 </p>
 <ul>
-	<li>the index <code>x</code> must be an untyped constant or its
-	    <a href="#Core_types">core type</a> must be an <a href="#Numeric_types">integer</a></li>
+	<li>the index <code>x</code> must be an untyped constant, or its type must be
+	    an <a href="#Numeric_types">integer</a> or a type parameter whose type set
+	    contains only integer types</li>
 	<li>a constant index must be non-negative and
 	    <a href="#Representability">representable</a> by a value of type <code>int</code></li>
 	<li>a constant index that is untyped is given type <code>int</code></li>
@@ -4052,14 +3955,26 @@ Assigning to an element of a <code>nil</code> map causes a
 
 <p>
 Slice expressions construct a substring or slice from a string, array, pointer
-to array, or slice. There are two variants: a simple form that specifies a low
+to array, or slice operand.
+There are two variants: a simple form that specifies a low
 and high bound, and a full form that also specifies a bound on the capacity.
 </p>
 
+<p>
+If the operand type is a <a href="#Type_parameter_declarations">type parameter</a>,
+unless its type set contains string types,
+all types in the type set must have the same underlying type, and the slice expression
+must be valid for an operand of that type.
+If the type set contains string types it may also contain byte slices with underlying
+type <code>[]byte</code>.
+In this case, the slice expression must be valid for an operand of <code>string</code>
+type.
+</p>
+
 <h4>Simple slice expressions</h4>
 
 <p>
-The primary expression
+For a string, array, pointer to array, or slice <code>a</code>, the primary expression
 </p>
 
 <pre>
@@ -4067,9 +3982,7 @@ a[low : high]
 </pre>
 
 <p>
-constructs a substring or slice. The <a href="#Core_types">core type</a> of
-<code>a</code> must be a string, array, pointer to array, slice, or a
-<a href="#Core_types"><code>bytestring</code></a>.
+constructs a substring or slice.
 The <i>indices</i> <code>low</code> and
 <code>high</code> select which elements of operand <code>a</code> appear
 in the result. The result has indices starting at 0 and length equal to
@@ -4149,7 +4062,7 @@ s3 := s[:0]    // s3 == nil
 <h4>Full slice expressions</h4>
 
 <p>
-The primary expression
+For an array, pointer to array, or slice <code>a</code> (but not a string), the primary expression
 </p>
 
 <pre>
@@ -4160,8 +4073,6 @@ a[low : high : max]
 constructs a slice of the same type, and with the same length and elements as the simple slice
 expression <code>a[low : high]</code>. Additionally, it controls the resulting slice's capacity
 by setting it to <code>max - low</code>. Only the first index may be omitted; it defaults to 0.
-The <a href="#Core_types">core type</a> of <code>a</code> must be an array, pointer to array,
-or slice (but not a string).
 After slicing the array <code>a</code>
 </p>
 
@@ -4267,8 +4178,8 @@ No <a href="#Run_time_panics">run-time panic</a> occurs in this case.
 <h3 id="Calls">Calls</h3>
 
 <p>
-Given an expression <code>f</code> with a <a href="#Core_types">core type</a>
-<code>F</code> of <a href="#Function_types">function type</a>,
+Given an expression <code>f</code> of <a href="#Function_types">function type</a>
+<code>F</code>,
 </p>
 
 <pre>
@@ -4298,6 +4209,12 @@ If <code>f</code> denotes a generic function, it must be
 or used as a function value.
 </p>
 
+<p>
+If the type of <code>f</code> is a <a href="#Type_parameter_declarations">type parameter</a>,
+all types in its type set must have the same underlying type, which must be a function type,
+and the function call must be valid for that type.
+</p>
+
 <p>
 In a function call, the function value and arguments are evaluated in
 <a href="#Order_of_evaluation">the usual order</a>.
@@ -4811,17 +4728,28 @@ more complicated:
 
 <ul>
 <li>
-	If <code>C</code> has a <a href="#Core_types">core type</a>
-	<code>core(C)</code>
+	If all types in <code>C</code>'s type set have the same
+	underlying type <code>U</code>,
 	and <code>P</code> has a known type argument <code>A</code>,
-	<code>core(C)</code> and <code>A</code> must unify loosely.
+	<code>U</code> and <code>A</code> must unify loosely.
+</li>
+<li>
+	Similarly, if all types in <code>C</code>'s type set are
+	channel types with the same element type and non-conflicting
+	channel directions,
+	and <code>P</code> has a known type argument <code>A</code>,
+	the most restrictive channel type in <code>C</code>'s type
+	set and <code>A</code> must unify loosely.
+</li>
+<li>
 	If <code>P</code> does not have a known type argument
 	and <code>C</code> contains exactly one type term <code>T</code>
 	that is not an underlying (tilde) type, unification adds the
 	mapping <code>P ➞ T</code> to the map.
 </li>
 <li>
-	If <code>C</code> does not have a core type
+	If <code>C</code> does not have a type <code>U</code>
+	as described above
 	and <code>P</code> has a known type argument <code>A</code>,
 	<code>A</code> must have all methods of <code>C</code>, if any,
 	and corresponding method types must unify exactly.
@@ -5372,10 +5300,10 @@ var x *int = nil
 <h3 id="Receive_operator">Receive operator</h3>
 
 <p>
-For an operand <code>ch</code> whose <a href="#Core_types">core type</a> is a
-<a href="#Channel_types">channel</a>,
+For an operand <code>ch</code> of <a href="#Channel_types">channel type</a>,
 the value of the receive operation <code>&lt;-ch</code> is the value received
-from the channel <code>ch</code>. The channel direction must permit receive operations,
+from the channel <code>ch</code>.
+The channel direction must permit receive operations,
 and the type of the receive operation is the element type of the channel.
 The expression blocks until a value is available.
 Receiving from a <code>nil</code> channel blocks forever.
@@ -5391,6 +5319,12 @@ f(&lt;-ch)
 &lt;-strobe  // wait until clock pulse and discard received value
 </pre>
 
+<p>
+If the operand type is a <a href="#Type_parameter_declarations">type parameter</a>,
+all types in its type set must be channel types that permit receive operations, and
+they must all have the same element type, which is the type of the receive operation.
+</p>
+
 <p>
 A receive expression used in an <a href="#Assignment_statements">assignment statement</a> or initialization of the special form
 </p>
@@ -6126,8 +6060,7 @@ len("foo")  // illegal if len is the built-in function
 
 <p>
 A send statement sends a value on a channel.
-The channel expression's <a href="#Core_types">core type</a>
-must be a <a href="#Channel_types">channel</a>,
+The channel expression must be of <a href="#Channel_types">channel type</a>,
 the channel direction must permit send operations,
 and the type of the value to be sent must be <a href="#Assignability">assignable</a>
 to the channel's element type.
@@ -6151,6 +6084,13 @@ A send on a <code>nil</code> channel blocks forever.
 ch &lt;- 3  // send value 3 to channel ch
 </pre>
 
+<p>
+If the type of the channel expression is a
+<a href="#Type_parameter_declarations">type parameter</a>,
+all types in its type set must be channel types that permit send operations,
+they must all have the same element type,
+and the type of the value to be sent must be assignable to that element type.
+</p>
 
 <h3 id="IncDec_statements">IncDec statements</h3>
 
@@ -6743,8 +6683,7 @@ RangeClause = [ ExpressionList "=" | IdentifierList ":=" ] "range" Expression .
 
 <p>
 The expression on the right in the "range" clause is called the <i>range expression</i>,
-its <a href="#Core_types">core type</a> must be
-an array, pointer to an array, slice, string, map, channel permitting
+which may be an array, pointer to an array, slice, string, map, channel permitting
 <a href="#Receive_operator">receive operations</a>, an integer, or
 a function with specific signature (see below).
 As with an assignment, if present the operands on the left must be
@@ -6958,6 +6897,12 @@ for k, v := range t.Walk {
 }
 </pre>
 
+<p>
+If the type of the range expression is a <a href="#Type_parameter_declarations">type parameter</a>,
+all types in its type set must have the same underlying type and the range expression must be valid
+for that type, or, if the type set contains channel types, it must only contain channel types with
+identical element types, and all channel types must permit receive operations.
+</p>
 
 <h3 id="Go_statements">Go statements</h3>
 
@@ -7431,23 +7376,28 @@ by the arguments overlaps.
 
 <p>
 The <a href="#Function_types">variadic</a> function <code>append</code>
-appends zero or more values <code>x</code> to a slice <code>s</code>
-and returns the resulting slice of the same type as <code>s</code>.
-The <a href="#Core_types">core type</a> of <code>s</code> must be a slice
-of type <code>[]E</code>.
+appends zero or more values <code>x</code> to a slice <code>s</code> of
+type <code>S</code> and returns the resulting slice, also of type
+<code>S</code>.
 The values <code>x</code> are passed to a parameter of type <code>...E</code>
+where <code>E</code> is the element type of <code>S</code>
 and the respective <a href="#Passing_arguments_to_..._parameters">parameter
 passing rules</a> apply.
-As a special case, if the core type of <code>s</code> is <code>[]byte</code>,
-<code>append</code> also accepts a second argument with core type
-<a href="#Core_types"><code>bytestring</code></a> followed by <code>...</code>.
-This form appends the bytes of the byte slice or string.
+As a special case, <code>append</code> also accepts a first argument assignable
+to type <code>[]byte</code> with a second argument of string type followed by
+<code>...</code>.
+This form appends the bytes of the string.
 </p>
 
 <pre class="grammar">
-append(s S, x ...E) S  // core type of S is []E
+append(s S, x ...E) S  // E is the element type of S
 </pre>
 
+<p>
+If <code>S</code> is a <a href="#Type_parameter_declarations">type parameter</a>,
+all types in its type set must have the same underlying slice type <code>[]E</code>.
+</p>
+
 <p>
 If the capacity of <code>s</code> is not large enough to fit the additional
 values, <code>append</code> <a href="#Allocation">allocates</a> a new, sufficiently large underlying
@@ -7473,14 +7423,14 @@ b = append(b, "bar"...)            // append string contents      b is []byte{'b
 The function <code>copy</code> copies slice elements from
 a source <code>src</code> to a destination <code>dst</code> and returns the
 number of elements copied.
-The <a href="#Core_types">core types</a> of both arguments must be slices
-with <a href="#Type_identity">identical</a> element type.
+Both arguments must have <a href="#Type_identity">identical</a> element type
+<code>E</code> and must be assignable to a slice of type <code>[]E</code>.
 The number of elements copied is the minimum of
 <code>len(src)</code> and <code>len(dst)</code>.
-As a special case, if the destination's core type is <code>[]byte</code>,
-<code>copy</code> also accepts a source argument with core type
-<a href="#Core_types"><code>bytestring</code></a>.
-This form copies the bytes from the byte slice or string into the byte slice.
+As a special case, <code>copy</code> also accepts a destination argument
+assignable to type <code>[]byte</code> with a source argument of a
+<code>string</code> type.
+This form copies the bytes from the string into the byte slice.
 </p>
 
 <pre class="grammar">
@@ -7488,6 +7438,11 @@ copy(dst, src []T) int
 copy(dst []byte, src string) int
 </pre>
 
+<p>
+If the type of one or both arguments is a <a href="#Type_parameter_declarations">type parameter</a>,
+all types in their respective type sets must have the same underlying slice type <code>[]E</code>.
+</p>
+
 <p>
 Examples:
 </p>
@@ -7538,8 +7493,7 @@ If the map or slice is <code>nil</code>, <code>clear</code> is a no-op.
 <h3 id="Close">Close</h3>
 
 <p>
-For an argument <code>ch</code> with a <a href="#Core_types">core type</a>
-that is a <a href="#Channel_types">channel</a>, the built-in function <code>close</code>
+For a channel <code>ch</code>, the built-in function <code>close(ch)</code>
 records that no more values will be sent on the channel.
 It is an error if <code>ch</code> is a receive-only channel.
 Sending to or closing a closed channel causes a <a href="#Run_time_panics">run-time panic</a>.
@@ -7551,6 +7505,12 @@ The multi-valued <a href="#Receive_operator">receive operation</a>
 returns a received value along with an indication of whether the channel is closed.
 </p>
 
+<p>
+If the type of the argument to <code>close</code> is a
+<a href="#Type_parameter_declarations">type parameter</a>,
+all types in its type set must be channels with the same element type.
+It is an error if any of those channels is a receive-only channel.
+</p>
 
 <h3 id="Complex_numbers">Manipulating complex numbers</h3>
 
@@ -7720,27 +7680,36 @@ var z complex128
 
 <p>
 The built-in function <code>make</code> takes a type <code>T</code>,
+which must be a slice, map or channel type, or a type parameter,
 optionally followed by a type-specific list of expressions.
-The <a href="#Core_types">core type</a> of <code>T</code> must
-be a slice, map or channel.
 It returns a value of type <code>T</code> (not <code>*T</code>).
 The memory is initialized as described in the section on
 <a href="#The_zero_value">initial values</a>.
 </p>
 
 <pre class="grammar">
-Call             Core type    Result
+Call             Type T            Result
 
-make(T, n)       slice        slice of type T with length n and capacity n
-make(T, n, m)    slice        slice of type T with length n and capacity m
+make(T, n)       slice             slice of type T with length n and capacity n
+make(T, n, m)    slice             slice of type T with length n and capacity m
 
-make(T)          map          map of type T
-make(T, n)       map          map of type T with initial space for approximately n elements
+make(T)          map               map of type T
+make(T, n)       map               map of type T with initial space for approximately n elements
 
-make(T)          channel      unbuffered channel of type T
-make(T, n)       channel      buffered channel of type T, buffer size n
+make(T)          channel           unbuffered channel of type T
+make(T, n)       channel           buffered channel of type T, buffer size n
+
+make(T, n)       type parameter    see below
+make(T, n, m)    type parameter    see below
 </pre>
 
+<p>
+If the first argument is a <a href="#Type_parameter_declarations">type parameter</a>,
+all types in its type set must have the same underlying type, which must be a slice
+or map type, or, if there are channel types, there must only be channel types, they
+must all have the same element type, and the channel directions must not conflict.
+</p>
+
 <p>
 Each of the size arguments <code>n</code> and <code>m</code> must be of <a href="#Numeric_types">integer type</a>,
 have a <a href="#Interface_types">type set</a> containing only integer types,
@@ -8483,17 +8452,14 @@ func String(ptr *byte, len IntegerType) string
 func StringData(str string) *byte
 </pre>
 
-<!--
-These conversions also apply to type parameters with suitable core types.
-Determine if we can simply use core type instead of underlying type here,
-of if the general conversion rules take care of this.
--->
-
 <p>
 A <code>Pointer</code> is a <a href="#Pointer_types">pointer type</a> but a <code>Pointer</code>
 value may not be <a href="#Address_operators">dereferenced</a>.
-Any pointer or value of <a href="#Core_types">core type</a> <code>uintptr</code> can be
-<a href="#Conversions">converted</a> to a type of core type <code>Pointer</code> and vice versa.
+Any pointer or value of <a href="#Underlying_types">underlying type</a> <code>uintptr</code> can be
+<a href="#Conversions">converted</a> to a type of underlying type <code>Pointer</code> and vice versa.
+If the respective types are <a href="#Type_parameter_declarations">type parameters</a>, all types in
+their respective type sets must have the same underlying type, which must be <code>uintptr</code> and
+<code>Pointer</code>, respectively.
 The effect of converting between <code>Pointer</code> and <code>uintptr</code> is implementation-defined.
 </p>
 
@@ -8847,9 +8813,9 @@ following conditions is true:
 </li>
 <li>
 	Exactly one type is an <a href="#Type_inference">unbound</a>
-	type parameter with a <a href="#Core_types">core type</a>,
-	and that core type unifies with the other type per the
-	unification rules for <code>≡<sub>A</sub></code>
+	type parameter, and all the types in its type set unify with
+	the other type
+	per the unification rules for <code>≡<sub>A</sub></code>
 	(loose unification at the top level and exact unification
 	for element types).
 </li>

doc/godebug.md

@@ -109,7 +109,9 @@ Only the work module's `go.mod` is consulted for `godebug` directives.
 Any directives in required dependency modules are ignored.
 It is an error to list a `godebug` with an unrecognized setting.
 (Toolchains older than Go 1.23 reject all `godebug` lines, since they do not
-understand `godebug` at all.)
+understand `godebug` at all.) When a workspace is in use, `godebug`
+directives in `go.mod` files are ignored, and `go.work` will be consulted
+for `godebug` directives instead.
 
 The defaults from the `go` and `godebug` lines apply to all main
 packages that are built. For more fine-grained control,
@@ -151,6 +153,22 @@ for example,
 see the [runtime documentation](/pkg/runtime#hdr-Environment_Variables)
 and the [go command documentation](/cmd/go#hdr-Build_and_test_caching).
 
+### Go 1.25
+
+Go 1.25 added a new `decoratemappings` setting that controls whether the Go
+runtime annotates OS anonymous memory mappings with context about their
+purpose. These annotations appear in /proc/self/maps and /proc/self/smaps as
+"[anon: Go: ...]". This setting is only used on Linux. For Go 1.25, it defaults
+to `decoratemappings=1`, enabling annotations. Using `decoratemappings=0`
+reverts to the pre-Go 1.25 behavior. This setting is fixed at program startup
+time, and can't be modified by changing the `GODEBUG` environment variable
+after the program starts.
+
+Go 1.25 added a new `embedfollowsymlinks` setting that controls whether the
+Go command will follow symlinks to regular files embedding files.
+The default value `embedfollowsymlinks=0` does not allow following
+symlinks. `embedfollowsymlinks=1` will allow following symlinks.
+
 ### Go 1.24
 
 Go 1.24 added a new `fips140` setting that controls whether the Go
@@ -217,6 +235,8 @@ field by default.
 Go 1.24 enabled the post-quantum key exchange mechanism
 X25519MLKEM768 by default. The default can be reverted using the
 [`tlsmlkem` setting](/pkg/crypto/tls/#Config.CurvePreferences).
+This can be useful when dealing with buggy TLS servers that do not handle large records correctly,
+causing a timeout during the handshake (see [TLS post-quantum TL;DR fail](https://tldr.fail/)).
 Go 1.24 also removed X25519Kyber768Draft00 and the Go 1.23 `tlskyber` setting.
 
 Go 1.24 made [`ParsePKCS1PrivateKey`](/pkg/crypto/x509/#ParsePKCS1PrivateKey)
@@ -253,6 +273,8 @@ Previous versions default to `winreadlinkvolume=0`.
 Go 1.23 enabled the experimental post-quantum key exchange mechanism
 X25519Kyber768Draft00 by default. The default can be reverted using the
 [`tlskyber` setting](/pkg/crypto/tls/#Config.CurvePreferences).
+This can be useful when dealing with buggy TLS servers that do not handle large records correctly,
+causing a timeout during the handshake (see [TLS post-quantum TL;DR fail](https://tldr.fail/)).
 
 Go 1.23 changed the behavior of
 [crypto/x509.ParseCertificate](/pkg/crypto/x509/#ParseCertificate) to reject
@@ -348,7 +370,7 @@ certificate policy OIDs with components larger than 31 bits. By default this
 field is only used during parsing, when it is populated with policy OIDs, but
 not used during marshaling. It can be used to marshal these larger OIDs, instead
 of the existing PolicyIdentifiers field, by using the
-[`x509usepolicies` setting.](/pkg/crypto/x509/#CreateCertificate).
+[`x509usepolicies` setting](/pkg/crypto/x509/#CreateCertificate).
 
 
 ### Go 1.21

doc/initial/6-stdlib/99-minor/0-heading.md

@@ -1,3 +1,10 @@
 ### Minor changes to the library {#minor_library_changes}
 
+#### go/types
 
+The `Var.Kind` method returns an enumeration of type `VarKind` that
+classifies the variable (package-level, local, receiver, parameter,
+result, or struct field). See issue #70250.
+
+Callers of `NewVar` or `NewParam` are encouraged to call `Var.SetKind`
+to ensure that this attribute is set correctly in all cases.

doc/next/1-intro.md

@@ -0,0 +1,8 @@
+<style>
+  main ul li { margin: 0.5em 0; }
+</style>
+
+## DRAFT RELEASE NOTES — Introduction to Go 1.N {#introduction}
+
+**Go 1.25 is not yet released. These are work-in-progress release notes.
+Go 1.25 is expected to be released in August 2025.**

doc/next/2-language.md

@@ -0,0 +1,3 @@
+## Changes to the language {#language}
+
+

doc/next/3-tools.md

@@ -0,0 +1,42 @@
+## Tools {#tools}
+
+### Go command {#go-command}
+
+The `go build` `-asan` option now defaults to doing leak detection at
+program exit.
+This will report an error if memory allocated by C is not freed and is
+not referenced by any other memory allocated by either C or Go.
+These new error reports may be disabled by setting
+`ASAN_OPTIONS=detect_leaks=0` in the environment when running the
+program.
+
+<!-- go.dev/issue/71294 -->
+
+The new `work` package pattern matches all packages in the work (formerly called main)
+modules: either the single work module in module mode or the set of workspace modules
+in workspace mode.
+
+<!-- go.dev/issue/65847 -->
+
+When the go command updates the `go` line in a `go.mod` or `go.work` file,
+it [no longer](/ref/mod#go-mod-file-toolchain) adds a toolchain line
+specifying the command's current version.
+
+### Cgo {#cgo}
+
+### Vet {#vet}
+
+The `go vet` command includes new analyzers:
+
+<!-- go.dev/issue/18022 -->
+
+- [waitgroup](https://pkg.go.dev/golang.org/x/tools/go/analysis/passes/waitgroup),
+  which reports misplaced calls to [sync.WaitGroup.Add]; and
+
+<!-- go.dev/issue/28308 -->
+
+- [hostport](https://pkg.go.dev/golang.org/x/tools/go/analysis/passes/hostport),
+  which reports uses of `fmt.Sprintf("%s:%d", host, port)` to
+  construct addresses for [net.Dial], as these will not work with
+  IPv6; instead it suggests using [net.JoinHostPort].
+

doc/next/4-runtime.md

@@ -0,0 +1,26 @@
+## Runtime {#runtime}
+
+<!-- go.dev/issue/71517 -->
+
+The message printed when a program exits due to an unhandled panic
+that was recovered and re-raised no longer repeats the text of
+the panic value.
+
+Previously, a program which panicked with `panic("PANIC")`,
+recovered the panic, and then re-panicked with the original
+value would print:
+
+    panic: PANIC [recovered]
+      panic: PANIC
+
+This program will now print:
+
+    panic: PANIC [recovered, reraised]
+
+<!-- go.dev/issue/71546 -->
+
+On Linux systems with kernel support for anonymous VMA names
+(`CONFIG_ANON_VMA_NAME`), the Go runtime will annotate anonymous memory
+mappings with context about their purpose. e.g., `[anon: Go: heap]` for heap
+memory. This can be disabled with the [GODEBUG setting](/doc/godebug)
+`decoratemappings=0`.

doc/next/5-toolchain.md

@@ -0,0 +1,44 @@
+## Compiler {#compiler}
+
+<!-- https://go.dev/issue/26379 -->
+
+The compiler and linker in Go 1.25 now generate debug information
+using [DWARF version 5](https://dwarfstd.org/dwarf5std.html); the
+newer DWARF version reduces the space required for debugging
+information in Go binaries.
+DWARF 5 generation is gated by the "dwarf5" GOEXPERIMENT; this
+functionality can be disabled (for now) using GOEXPERIMENT=nodwarf5.
+
+<!-- https://go.dev/issue/72860, CL 657715 -->
+
+The compiler [has been fixed](/cl/657715)
+to ensure that nil pointer checks are performed promptly. Programs like the following,
+which used to execute successfully, will now panic with a nil-pointer exception:
+
+```
+package main
+
+import "os"
+
+func main() {
+	f, err := os.Open("nonExistentFile")
+	name := f.Name()
+	if err != nil {
+		return
+	}
+	println(name)
+}
+```
+
+This program is incorrect in that it uses the result of `os.Open` before checking
+the error. The main result of `os.Open` can be a nil pointer if the error result is non-nil.
+But because of [a compiler bug](/issue/72860), this program ran successfully under
+Go versions 1.21 through 1.24 (in violation of the Go spec). It will no longer run
+successfully in Go 1.25. If this change is affecting your code, the solution is to put
+the non-nil error check earlier in your code, preferably immediately after
+the error-generating statement.
+
+## Assembler {#assembler}
+
+## Linker {#linker}
+

doc/next/6-stdlib/0-heading.md

@@ -0,0 +1,2 @@
+## Standard library {#library}
+

doc/next/6-stdlib/99-minor/0-heading.md

@@ -0,0 +1,3 @@
+### Minor changes to the library {#minor_library_changes}
+
+

doc/next/6-stdlib/99-minor/README

@@ -0,0 +1 @@
+API changes and other small changes to the standard library go here.

doc/next/6-stdlib/99-minor/archive/tar/49580.md

@@ -0,0 +1,2 @@
+The [*Writer.AddFS] implementation now supports symbolic links
+for filesystems that implement [io/fs.ReadLinkFS].

doc/next/6-stdlib/99-minor/crypto/elliptic/hidden.md

@@ -0,0 +1,2 @@
+The hidden and undocumented `Inverse` and `CombinedMult` methods on some [Curve]
+implementations have been removed.

doc/next/6-stdlib/99-minor/crypto/tls/67516.md

@@ -0,0 +1,2 @@
+The new [ConnectionState.CurveID] field exposes the key exchange mechanism used
+to establish the connection.

doc/next/6-stdlib/99-minor/crypto/tls/fips.md

@@ -0,0 +1,2 @@
+When [FIPS 140-3 mode](/doc/security/fips140) is enabled, Extended Master Secret
+is now required in TLS 1.2, and Ed25519 and X25519MLKEM768 are now allowed.

doc/next/6-stdlib/99-minor/debug/elf/72843.md

@@ -0,0 +1,4 @@
+The [debug/elf] package adds two new constants:
+- [PT_RISCV_ATTRIBUTES]
+- [SHT_RISCV_ATTRIBUTES]
+for RISC-V ELF parsing.

doc/next/6-stdlib/99-minor/go/parser/71122.md

@@ -0,0 +1 @@
+The [ParseDir] function is deprecated.

doc/next/6-stdlib/99-minor/go/types/70250.md

@@ -0,0 +1,3 @@
+[Var] now has a [Var.Kind] method that classifies the variable as one
+of: package-level, receiver, parameter, result, or local variable, or
+a struct field.

doc/next/6-stdlib/99-minor/go/types/70737.md

@@ -0,0 +1,3 @@
+The new [LookupSelection] function looks up the field or method of a
+given name and receiver type, like the existing [LookupFieldOrMethod]
+function, but returns the result in the form of a [Selection].

doc/next/6-stdlib/99-minor/io/fs/49580.md

@@ -0,0 +1 @@
+A new [ReadLinkFS] interface provides the ability to read symbolic links in a filesystem.

doc/next/6-stdlib/99-minor/mime/multipart/46771.md

@@ -0,0 +1,2 @@
+The new helper function [FieldContentDisposition] builds multipart
+Content-Disposition header fields.

doc/next/6-stdlib/99-minor/net/10350.md

@@ -0,0 +1,3 @@
+On Windows, the [TCPConn.File], [UDPConn.File], [UnixConn.File],
+[IPConn.File], [TCPListener.File], and [UnixListener.File]
+methods are now supported.

doc/next/6-stdlib/99-minor/net/56025.md

@@ -0,0 +1,5 @@
+[LookupMX] and [*Resolver.LookupMX] now return DNS names that look
+like valid IP address, as well as valid domain names.
+Previously if a name server returned an IP address as a DNS name,
+LookupMX would discard it, as required by the RFCs.
+However, name servers in practice do sometimes return IP addresses.

doc/next/6-stdlib/99-minor/net/63529.md

@@ -0,0 +1 @@
+On Windows, the [ListenMulticastUDP] now supports IPv6 addresses.

doc/next/6-stdlib/99-minor/net/9503.md

@@ -0,0 +1,2 @@
+On Windows, the [FileConn], [FilePacketConn], [FileListener]
+functions are now supported.

doc/next/6-stdlib/99-minor/os/15388.md

@@ -0,0 +1,14 @@
+On Windows, [NewFile] now supports handles opened for asynchronous I/O (that is,
+[syscall.FILE_FLAG_OVERLAPPED] is specified in the [syscall.CreateFile] call).
+These handles are associated with the Go runtime's I/O completion port,
+which provides the following benefits for the resulting [File]:
+
+- I/O methods ([File.Read], [File.Write], [File.ReadAt], and [File.WriteAt]) do not block an OS thread.
+- Deadline methods ([File.SetDeadline], [File.SetReadDeadline], and [File.SetWriteDeadline]) are supported.
+
+This enhancement is especially beneficial for applications that communicate via named pipes on Windows.
+
+Note that a handle can only be associated with one completion port at a time.
+If the handle provided to [NewFile] is already associated with a completion port,
+the returned [File] is downgraded to synchronous I/O mode.
+In this case, I/O methods will block an OS thread, and the deadline methods have no effect.

doc/next/6-stdlib/99-minor/os/49580.md

@@ -0,0 +1,2 @@
+The filesystem returned by [DirFS] implements the new [io/fs.ReadLinkFS] interface.
+[CopyFS] supports symlinks when copying filesystems that implement [io/fs.ReadLinkFS].

doc/next/6-stdlib/99-minor/os/67002.md

@@ -0,0 +1,10 @@
+The [os.Root] type supports the following additional methods:
+
+  * [os.Root.Chmod]
+  * [os.Root.Chown]
+  * [os.Root.Chtimes]
+  * [os.Root.Lchown]
+  * [os.Root.Link]
+  * [os.Root.Readlink]
+  * [os.Root.Rename]
+  * [os.Root.Symlink]

doc/next/6-stdlib/99-minor/regexp/syntax/70781.md

@@ -0,0 +1,4 @@
+The `\p{name}` and `\P{name}` character class syntaxes now accept the names
+Any, ASCII, Assigned, Cn, and LC, as well as Unicode category aliases like `\p{Letter}` for `\pL`.
+Following [Unicode TR18](https://unicode.org/reports/tr18/), they also now use
+case-insensitive name lookups, ignoring spaces, underscores, and hyphens.

doc/next/6-stdlib/99-minor/sync/63769.md

@@ -0,0 +1,2 @@
+[WaitGroup] has added a new method [WaitGroup.Go],
+that makes the common pattern of creating and counting goroutines more convenient.

doc/next/6-stdlib/99-minor/testing/fstest/49580.md

@@ -0,0 +1,3 @@
+[MapFS] implements the new [io/fs.ReadLinkFS] interface.
+[TestFS] will verify the functionality of the [io/fs.ReadLinkFS] interface if implemented.
+[TestFS] will no longer follow symlinks to avoid unbounded recursion.

doc/next/6-stdlib/99-minor/unicode/70780.md

@@ -0,0 +1,4 @@
+The new [CategoryAliases] map provides access to category alias names, such as “Letter” for “L”.
+The new categories [Cn] and [LC] define unassigned codepoints and cased letters, respectively.
+These have always been defined by Unicode but were inadvertently omitted in earlier versions of Go.
+The [C] category now includes [Cn], meaning it has added all unassigned code points.

doc/next/7-ports.md

@@ -0,0 +1,11 @@
+## Ports {#ports}
+
+### Darwin
+
+<!-- go.dev/issue/69839 -->
+As [announced](/doc/go1.24#darwin) in the Go 1.24 release notes, Go 1.25 requires macOS 12 Monterey or later; support for previous versions has been discontinued.
+
+### Windows
+
+<!-- go.dev/issue/71671 -->
+Go 1.25 is the last release that contains the [broken](/doc/go1.24#windows) 32-bit windows/arm port (`GOOS=windows` `GOARCH=arm`). It will be removed in Go 1.26.

lib/time/update.bash

@@ -40,7 +40,12 @@ curl -sS -L -O https://www.iana.org/time-zones/repository/releases/tzdata$DATA.t
 tar xzf tzcode$CODE.tar.gz
 tar xzf tzdata$DATA.tar.gz
 
-if ! make CFLAGS=-DSTD_INSPIRED AWK=awk TZDIR=zoneinfo posix_only >make.out 2>&1; then
+# The PACKRATLIST and PACKRATDATA options are copied from Ubuntu:
+# https://git.launchpad.net/ubuntu/+source/tzdata/tree/debian/rules?h=debian/sid
+#
+# You can see the description of these make variables in the tzdata Makefile:
+# https://github.com/eggert/tz/blob/main/Makefile
+if ! make CFLAGS=-DSTD_INSPIRED AWK=awk TZDIR=zoneinfo PACKRATDATA=backzone PACKRATLIST=zone.tab posix_only >make.out 2>&1; then
 	cat make.out
 	exit 2
 fi

misc/linkcheck/linkcheck.go

@@ -1,191 +0,0 @@
-// Copyright 2013 The Go Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style
-// license that can be found in the LICENSE file.
-
-// The linkcheck command finds missing links in the godoc website.
-// It crawls a URL recursively and notes URLs and URL fragments
-// that it's seen and prints a report of missing links at the end.
-package main
-
-import (
-	"errors"
-	"flag"
-	"fmt"
-	"io"
-	"log"
-	"net/http"
-	"os"
-	"regexp"
-	"strings"
-	"sync"
-)
-
-var (
-	root    = flag.String("root", "http://localhost:6060", "Root to crawl")
-	verbose = flag.Bool("verbose", false, "verbose")
-)
-
-var wg sync.WaitGroup        // outstanding fetches
-var urlq = make(chan string) // URLs to crawl
-
-// urlFrag is a URL and its optional #fragment (without the #)
-type urlFrag struct {
-	url, frag string
-}
-
-var (
-	mu          sync.Mutex
-	crawled     = make(map[string]bool)      // URL without fragment -> true
-	neededFrags = make(map[urlFrag][]string) // URL#frag -> who needs it
-)
-
-var aRx = regexp.MustCompile(`<a href=['"]?(/[^\s'">]+)`)
-
-// Owned by crawlLoop goroutine:
-var (
-	linkSources = make(map[string][]string) // url no fragment -> sources
-	fragExists  = make(map[urlFrag]bool)
-	problems    []string
-)
-
-func localLinks(body string) (links []string) {
-	seen := map[string]bool{}
-	mv := aRx.FindAllStringSubmatch(body, -1)
-	for _, m := range mv {
-		ref := m[1]
-		if strings.HasPrefix(ref, "/src/") {
-			continue
-		}
-		if !seen[ref] {
-			seen[ref] = true
-			links = append(links, m[1])
-		}
-	}
-	return
-}
-
-var idRx = regexp.MustCompile(`\bid=['"]?([^\s'">]+)`)
-
-func pageIDs(body string) (ids []string) {
-	mv := idRx.FindAllStringSubmatch(body, -1)
-	for _, m := range mv {
-		ids = append(ids, m[1])
-	}
-	return
-}
-
-// url may contain a #fragment, and the fragment is then noted as needing to exist.
-func crawl(url string, sourceURL string) {
-	if strings.Contains(url, "/devel/release") {
-		return
-	}
-	mu.Lock()
-	defer mu.Unlock()
-	if u, frag, ok := strings.Cut(url, "#"); ok {
-		url = u
-		if frag != "" {
-			uf := urlFrag{url, frag}
-			neededFrags[uf] = append(neededFrags[uf], sourceURL)
-		}
-	}
-	if crawled[url] {
-		return
-	}
-	crawled[url] = true
-
-	wg.Add(1)
-	go func() {
-		urlq <- url
-	}()
-}
-
-func addProblem(url, errmsg string) {
-	msg := fmt.Sprintf("Error on %s: %s (from %s)", url, errmsg, linkSources[url])
-	if *verbose {
-		log.Print(msg)
-	}
-	problems = append(problems, msg)
-}
-
-func crawlLoop() {
-	for url := range urlq {
-		if err := doCrawl(url); err != nil {
-			addProblem(url, err.Error())
-		}
-	}
-}
-
-func doCrawl(url string) error {
-	defer wg.Done()
-
-	req, err := http.NewRequest("GET", url, nil)
-	if err != nil {
-		return err
-	}
-	res, err := http.DefaultTransport.RoundTrip(req)
-	if err != nil {
-		return err
-	}
-	// Handle redirects.
-	if res.StatusCode/100 == 3 {
-		newURL, err := res.Location()
-		if err != nil {
-			return fmt.Errorf("resolving redirect: %v", err)
-		}
-		if !strings.HasPrefix(newURL.String(), *root) {
-			// Skip off-site redirects.
-			return nil
-		}
-		crawl(newURL.String(), url)
-		return nil
-	}
-	if res.StatusCode != 200 {
-		return errors.New(res.Status)
-	}
-	slurp, err := io.ReadAll(res.Body)
-	res.Body.Close()
-	if err != nil {
-		log.Fatalf("Error reading %s body: %v", url, err)
-	}
-	if *verbose {
-		log.Printf("Len of %s: %d", url, len(slurp))
-	}
-	body := string(slurp)
-	for _, ref := range localLinks(body) {
-		if *verbose {
-			log.Printf("  links to %s", ref)
-		}
-		dest := *root + ref
-		linkSources[dest] = append(linkSources[dest], url)
-		crawl(dest, url)
-	}
-	for _, id := range pageIDs(body) {
-		if *verbose {
-			log.Printf(" url %s has #%s", url, id)
-		}
-		fragExists[urlFrag{url, id}] = true
-	}
-	return nil
-}
-
-func main() {
-	flag.Parse()
-
-	go crawlLoop()
-	crawl(*root, "")
-
-	wg.Wait()
-	close(urlq)
-	for uf, needers := range neededFrags {
-		if !fragExists[uf] {
-			problems = append(problems, fmt.Sprintf("Missing fragment for %+v from %v", uf, needers))
-		}
-	}
-
-	for _, s := range problems {
-		fmt.Println(s)
-	}
-	if len(problems) > 0 {
-		os.Exit(1)
-	}
-}

src/all.bat

@@ -6,17 +6,11 @@
 
 setlocal
 
-if exist make.bat goto ok
-echo all.bat must be run from go\src
-:: cannot exit: would kill parent command interpreter
-goto end
-:ok
+if not exist make.bat (
+    echo all.bat must be run from go\src
+    exit /b 1
+)
 
-call .\make.bat --no-banner --no-local
-if %GOBUILDFAIL%==1 goto end
-call .\run.bat --no-rebuild --no-local
-if %GOBUILDFAIL%==1 goto end
-"%GOTOOLDIR%/dist" banner
-
-:end
-if x%GOBUILDEXIT%==x1 exit %GOBUILDFAIL%
+call .\make.bat --no-banner || exit /b 1
+call .\run.bat --no-rebuild || exit /b 1
+..\bin\go tool dist banner

src/archive/tar/writer.go

@@ -415,11 +415,17 @@ func (tw *Writer) AddFS(fsys fs.FS) error {
 		if err != nil {
 			return err
 		}
-		// TODO(#49580): Handle symlinks when fs.ReadLinkFS is available.
-		if !d.IsDir() && !info.Mode().IsRegular() {
+		linkTarget := ""
+		if typ := d.Type(); typ == fs.ModeSymlink {
+			var err error
+			linkTarget, err = fs.ReadLink(fsys, name)
+			if err != nil {
+				return err
+			}
+		} else if !typ.IsRegular() && typ != fs.ModeDir {
 			return errors.New("tar: cannot add non-regular file")
 		}
-		h, err := FileInfoHeader(info, "")
+		h, err := FileInfoHeader(info, linkTarget)
 		if err != nil {
 			return err
 		}
@@ -430,7 +436,7 @@ func (tw *Writer) AddFS(fsys fs.FS) error {
 		if err := tw.WriteHeader(h); err != nil {
 			return err
 		}
-		if d.IsDir() {
+		if !d.Type().IsRegular() {
 			return nil
 		}
 		f, err := fsys.Open(name)

src/archive/tar/writer_test.go

@@ -1342,6 +1342,7 @@ func TestWriterAddFS(t *testing.T) {
 		"emptyfolder":          {Mode: 0o755 | os.ModeDir},
 		"file.go":              {Data: []byte("hello")},
 		"subfolder/another.go": {Data: []byte("world")},
+		"symlink.go":           {Mode: 0o777 | os.ModeSymlink, Data: []byte("file.go")},
 		// Notably missing here is the "subfolder" directory. This makes sure even
 		// if we don't have a subfolder directory listed.
 	}
@@ -1370,7 +1371,7 @@ func TestWriterAddFS(t *testing.T) {
 	for _, name := range names {
 		entriesLeft--
 
-		entryInfo, err := fsys.Stat(name)
+		entryInfo, err := fsys.Lstat(name)
 		if err != nil {
 			t.Fatalf("getting entry info error: %v", err)
 		}
@@ -1396,18 +1397,23 @@ func TestWriterAddFS(t *testing.T) {
 				name, entryInfo.Mode(), hdr.FileInfo().Mode())
 		}
 
-		if entryInfo.IsDir() {
-			continue
-		}
-
-		data, err := io.ReadAll(tr)
-		if err != nil {
-			t.Fatal(err)
-		}
-		origdata := fsys[name].Data
-		if string(data) != string(origdata) {
-			t.Fatalf("test fs has file content %v; archive header has %v",
-				data, origdata)
+		switch entryInfo.Mode().Type() {
+		case fs.ModeDir:
+			// No additional checks necessary.
+		case fs.ModeSymlink:
+			origtarget := string(fsys[name].Data)
+			if hdr.Linkname != origtarget {
+				t.Fatalf("test fs has link content %s; archive header %v", origtarget, hdr.Linkname)
+			}
+		default:
+			data, err := io.ReadAll(tr)
+			if err != nil {
+				t.Fatal(err)
+			}
+			origdata := fsys[name].Data
+			if string(data) != string(origdata) {
+				t.Fatalf("test fs has file content %v; archive header has %v", origdata, data)
+			}
 		}
 	}
 	if entriesLeft > 0 {

src/archive/zip/reader.go

@@ -8,6 +8,7 @@ import (
 	"bufio"
 	"encoding/binary"
 	"errors"
+	"fmt"
 	"hash"
 	"hash/crc32"
 	"internal/godebug"
@@ -804,6 +805,9 @@ func toValidName(name string) string {
 
 func (r *Reader) initFileList() {
 	r.fileListOnce.Do(func() {
+		// Preallocate the minimum size of the index.
+		// We may also synthesize additional directory entries.
+		r.fileList = make([]fileListEntry, 0, len(r.File))
 		// files and knownDirs map from a file/directory name
 		// to an index into the r.fileList entry that we are
 		// building. They are used to mark duplicate entries.
@@ -985,6 +989,12 @@ func (d *openDir) ReadDir(count int) ([]fs.DirEntry, error) {
 		s, err := d.files[d.offset+i].stat()
 		if err != nil {
 			return nil, err
+		} else if s.Name() == "." || !fs.ValidPath(s.Name()) {
+			return nil, &fs.PathError{
+				Op:   "readdir",
+				Path: d.e.name,
+				Err:  fmt.Errorf("invalid file name: %v", d.files[d.offset+i].name),
+			}
 		}
 		list[i] = s
 	}

src/archive/zip/reader_test.go

@@ -8,6 +8,7 @@ import (
 	"bytes"
 	"encoding/binary"
 	"encoding/hex"
+	"errors"
 	"internal/obscuretestdata"
 	"io"
 	"io/fs"
@@ -1281,6 +1282,49 @@ func TestFSWalk(t *testing.T) {
 	}
 }
 
+func TestFSWalkBadFile(t *testing.T) {
+	t.Parallel()
+
+	var buf bytes.Buffer
+	zw := NewWriter(&buf)
+	hdr := &FileHeader{Name: "."}
+	hdr.SetMode(fs.ModeDir | 0o755)
+	w, err := zw.CreateHeader(hdr)
+	if err != nil {
+		t.Fatalf("create zip header: %v", err)
+	}
+	_, err = w.Write([]byte("some data"))
+	if err != nil {
+		t.Fatalf("write zip contents: %v", err)
+
+	}
+	err = zw.Close()
+	if err != nil {
+		t.Fatalf("close zip writer: %v", err)
+
+	}
+
+	zr, err := NewReader(bytes.NewReader(buf.Bytes()), int64(buf.Len()))
+	if err != nil {
+		t.Fatalf("create zip reader: %v", err)
+
+	}
+	var count int
+	var errRepeat = errors.New("repeated call to path")
+	err = fs.WalkDir(zr, ".", func(p string, d fs.DirEntry, err error) error {
+		count++
+		if count > 2 { // once for directory read, once for the error
+			return errRepeat
+		}
+		return err
+	})
+	if err == nil {
+		t.Fatalf("expected error from invalid file name")
+	} else if errors.Is(err, errRepeat) {
+		t.Fatal(err)
+	}
+}
+
 func TestFSModTime(t *testing.T) {
 	t.Parallel()
 	z, err := OpenReader("testdata/subdir.zip")

src/bufio/bufio.go

@@ -519,9 +519,11 @@ func (b *Reader) WriteTo(w io.Writer) (n int64, err error) {
 	b.lastByte = -1
 	b.lastRuneSize = -1
 
-	n, err = b.writeBuf(w)
-	if err != nil {
-		return
+	if b.r < b.w {
+		n, err = b.writeBuf(w)
+		if err != nil {
+			return
+		}
 	}
 
 	if r, ok := b.rd.(io.WriterTo); ok {

src/bufio/bufio_test.go

@@ -1149,7 +1149,7 @@ func (w errorWriterToTest) Write(p []byte) (int, error) {
 var errorWriterToTests = []errorWriterToTest{
 	{1, 0, nil, io.ErrClosedPipe, io.ErrClosedPipe},
 	{0, 1, io.ErrClosedPipe, nil, io.ErrClosedPipe},
-	{0, 0, io.ErrUnexpectedEOF, io.ErrClosedPipe, io.ErrClosedPipe},
+	{0, 0, io.ErrUnexpectedEOF, io.ErrClosedPipe, io.ErrUnexpectedEOF},
 	{0, 1, io.EOF, nil, nil},
 }
 

src/bufio/net_test.go

@@ -0,0 +1,96 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//go:build unix
+
+package bufio_test
+
+import (
+	"bufio"
+	"io"
+	"net"
+	"path/filepath"
+	"strings"
+	"sync"
+	"testing"
+)
+
+// TestCopyUnixpacket tests that we can use bufio when copying
+// across a unixpacket socket. This used to fail due to an unnecessary
+// empty Write call that was interpreted as an EOF.
+func TestCopyUnixpacket(t *testing.T) {
+	tmpDir := t.TempDir()
+	socket := filepath.Join(tmpDir, "unixsock")
+
+	// Start a unixpacket server.
+	addr := &net.UnixAddr{
+		Name: socket,
+		Net:  "unixpacket",
+	}
+	server, err := net.ListenUnix("unixpacket", addr)
+	if err != nil {
+		t.Skipf("skipping test because opening a unixpacket socket failed: %v", err)
+	}
+
+	// Start a goroutine for the server to accept one connection
+	// and read all the data sent on the connection,
+	// reporting the number of bytes read on ch.
+	ch := make(chan int, 1)
+	var wg sync.WaitGroup
+	wg.Add(1)
+	go func() {
+		defer wg.Done()
+
+		tot := 0
+		defer func() {
+			ch <- tot
+		}()
+
+		serverConn, err := server.Accept()
+		if err != nil {
+			t.Error(err)
+			return
+		}
+
+		buf := make([]byte, 1024)
+		for {
+			n, err := serverConn.Read(buf)
+			tot += n
+			if err == io.EOF {
+				return
+			}
+			if err != nil {
+				t.Error(err)
+				return
+			}
+		}
+	}()
+
+	clientConn, err := net.DialUnix("unixpacket", nil, addr)
+	if err != nil {
+		// Leaves the server goroutine hanging. Oh well.
+		t.Fatal(err)
+	}
+
+	defer wg.Wait()
+	defer clientConn.Close()
+
+	const data = "data"
+	r := bufio.NewReader(strings.NewReader(data))
+	n, err := io.Copy(clientConn, r)
+	if err != nil {
+		t.Fatal(err)
+	}
+
+	if n != int64(len(data)) {
+		t.Errorf("io.Copy returned %d, want %d", n, len(data))
+	}
+
+	clientConn.Close()
+	tot := <-ch
+
+	if tot != len(data) {
+		t.Errorf("server read %d, want %d", tot, len(data))
+	}
+}

src/bytes/bytes.go

@@ -451,7 +451,9 @@ var asciiSpace = [256]uint8{'\t': 1, '\n': 1, '\v': 1, '\f': 1, '\r': 1, ' ': 1}
 // Fields interprets s as a sequence of UTF-8-encoded code points.
 // It splits the slice s around each instance of one or more consecutive white space
 // characters, as defined by [unicode.IsSpace], returning a slice of subslices of s or an
-// empty slice if s contains only white space.
+// empty slice if s contains only white space. Every element of the returned slice is
+// non-empty. Unlike [Split], leading and trailing runs of white space characters
+// are discarded.
 func Fields(s []byte) [][]byte {
 	// First count the fields.
 	// This is an exact count if s is ASCII, otherwise it is an approximation.
@@ -505,7 +507,9 @@ func Fields(s []byte) [][]byte {
 // FieldsFunc interprets s as a sequence of UTF-8-encoded code points.
 // It splits the slice s at each run of code points c satisfying f(c) and
 // returns a slice of subslices of s. If all code points in s satisfy f(c), or
-// len(s) == 0, an empty slice is returned.
+// len(s) == 0, an empty slice is returned. Every element of the returned slice is
+// non-empty. Unlike [SplitFunc], leading and trailing runs of code points
+// satisfying f(c) are discarded.
 //
 // FieldsFunc makes no guarantees about the order in which it calls f(c)
 // and assumes that f always returns the same value for a given c.
@@ -1188,19 +1192,22 @@ func Replace(s, old, new []byte, n int) []byte {
 	t := make([]byte, len(s)+n*(len(new)-len(old)))
 	w := 0
 	start := 0
-	for i := 0; i < n; i++ {
-		j := start
-		if len(old) == 0 {
-			if i > 0 {
-				_, wid := utf8.DecodeRune(s[start:])
-				j += wid
-			}
-		} else {
-			j += Index(s[start:], old)
+	if len(old) > 0 {
+		for range n {
+			j := start + Index(s[start:], old)
+			w += copy(t[w:], s[start:j])
+			w += copy(t[w:], new)
+			start = j + len(old)
 		}
-		w += copy(t[w:], s[start:j])
+	} else { // len(old) == 0
 		w += copy(t[w:], new)
-		start = j + len(old)
+		for range n - 1 {
+			_, wid := utf8.DecodeRune(s[start:])
+			j := start + wid
+			w += copy(t[w:], s[start:j])
+			w += copy(t[w:], new)
+			start = j
+		}
 	}
 	w += copy(t[w:], s[start:])
 	return t[0:w]

src/bytes/bytes_test.go

@@ -7,6 +7,7 @@ package bytes_test
 import (
 	. "bytes"
 	"fmt"
+	"internal/asan"
 	"internal/testenv"
 	"iter"
 	"math"
@@ -1786,9 +1787,20 @@ var ReplaceTests = []ReplaceTest{
 
 func TestReplace(t *testing.T) {
 	for _, tt := range ReplaceTests {
-		in := append([]byte(tt.in), "<spare>"...)
+		var (
+			in  = []byte(tt.in)
+			old = []byte(tt.old)
+			new = []byte(tt.new)
+		)
+		if !asan.Enabled {
+			allocs := testing.AllocsPerRun(10, func() { Replace(in, old, new, tt.n) })
+			if allocs > 1 {
+				t.Errorf("Replace(%q, %q, %q, %d) allocates %.2f objects", tt.in, tt.old, tt.new, tt.n, allocs)
+			}
+		}
+		in = append(in, "<spare>"...)
 		in = in[:len(tt.in)]
-		out := Replace(in, []byte(tt.old), []byte(tt.new), tt.n)
+		out := Replace(in, old, new, tt.n)
 		if s := string(out); s != tt.out {
 			t.Errorf("Replace(%q, %q, %q, %d) = %q, want %q", tt.in, tt.old, tt.new, tt.n, s, tt.out)
 		}
@@ -1796,7 +1808,7 @@ func TestReplace(t *testing.T) {
 			t.Errorf("Replace(%q, %q, %q, %d) didn't copy", tt.in, tt.old, tt.new, tt.n)
 		}
 		if tt.n == -1 {
-			out := ReplaceAll(in, []byte(tt.old), []byte(tt.new))
+			out := ReplaceAll(in, old, new)
 			if s := string(out); s != tt.out {
 				t.Errorf("ReplaceAll(%q, %q, %q) = %q, want %q", tt.in, tt.old, tt.new, s, tt.out)
 			}
@@ -1804,6 +1816,69 @@ func TestReplace(t *testing.T) {
 	}
 }
 
+func FuzzReplace(f *testing.F) {
+	for _, tt := range ReplaceTests {
+		f.Add([]byte(tt.in), []byte(tt.old), []byte(tt.new), tt.n)
+	}
+	f.Fuzz(func(t *testing.T, in, old, new []byte, n int) {
+		differentImpl := func(in, old, new []byte, n int) []byte {
+			var out Buffer
+			if n < 0 {
+				n = math.MaxInt
+			}
+			for i := 0; i < len(in); {
+				if n == 0 {
+					out.Write(in[i:])
+					break
+				}
+				if HasPrefix(in[i:], old) {
+					out.Write(new)
+					i += len(old)
+					n--
+					if len(old) != 0 {
+						continue
+					}
+					if i == len(in) {
+						break
+					}
+				}
+				if len(old) == 0 {
+					_, length := utf8.DecodeRune(in[i:])
+					out.Write(in[i : i+length])
+					i += length
+				} else {
+					out.WriteByte(in[i])
+					i++
+				}
+			}
+			if len(old) == 0 && n != 0 {
+				out.Write(new)
+			}
+			return out.Bytes()
+		}
+		if simple, replace := differentImpl(in, old, new, n), Replace(in, old, new, n); !slices.Equal(simple, replace) {
+			t.Errorf("The two implementations do not match %q != %q for Replace(%q, %q, %q, %d)", simple, replace, in, old, new, n)
+		}
+	})
+}
+
+func BenchmarkReplace(b *testing.B) {
+	for _, tt := range ReplaceTests {
+		desc := fmt.Sprintf("%q %q %q %d", tt.in, tt.old, tt.new, tt.n)
+		var (
+			in  = []byte(tt.in)
+			old = []byte(tt.old)
+			new = []byte(tt.new)
+		)
+		b.Run(desc, func(b *testing.B) {
+			b.ReportAllocs()
+			for b.Loop() {
+				Replace(in, old, new, tt.n)
+			}
+		})
+	}
+}
+
 type TitleTest struct {
 	in, out string
 }

src/bytes/example_test.go

@@ -628,3 +628,93 @@ func ExampleToUpperSpecial() {
 	// Original : ahoj vývojári golang
 	// ToUpper : AHOJ VÝVOJÁRİ GOLANG
 }
+
+func ExampleLines() {
+	text := []byte("Hello\nWorld\nGo Programming\n")
+	for line := range bytes.Lines(text) {
+		fmt.Printf("%q\n", line)
+	}
+
+	// Output:
+	// "Hello\n"
+	// "World\n"
+	// "Go Programming\n"
+}
+
+func ExampleSplitSeq() {
+	s := []byte("a,b,c,d")
+	for part := range bytes.SplitSeq(s, []byte(",")) {
+		fmt.Printf("%q\n", part)
+	}
+
+	// Output:
+	// "a"
+	// "b"
+	// "c"
+	// "d"
+}
+
+func ExampleSplitAfterSeq() {
+	s := []byte("a,b,c,d")
+	for part := range bytes.SplitAfterSeq(s, []byte(",")) {
+		fmt.Printf("%q\n", part)
+	}
+
+	// Output:
+	// "a,"
+	// "b,"
+	// "c,"
+	// "d"
+}
+
+func ExampleFieldsSeq() {
+	text := []byte("The quick brown fox")
+	fmt.Println("Split byte slice into fields:")
+	for word := range bytes.FieldsSeq(text) {
+		fmt.Printf("%q\n", word)
+	}
+
+	textWithSpaces := []byte("  lots   of   spaces  ")
+	fmt.Println("\nSplit byte slice with multiple spaces:")
+	for word := range bytes.FieldsSeq(textWithSpaces) {
+		fmt.Printf("%q\n", word)
+	}
+
+	// Output:
+	// Split byte slice into fields:
+	// "The"
+	// "quick"
+	// "brown"
+	// "fox"
+	//
+	// Split byte slice with multiple spaces:
+	// "lots"
+	// "of"
+	// "spaces"
+}
+
+func ExampleFieldsFuncSeq() {
+	text := []byte("The quick brown fox")
+	fmt.Println("Split on whitespace(similar to FieldsSeq):")
+	for word := range bytes.FieldsFuncSeq(text, unicode.IsSpace) {
+		fmt.Printf("%q\n", word)
+	}
+
+	mixedText := []byte("abc123def456ghi")
+	fmt.Println("\nSplit on digits:")
+	for word := range bytes.FieldsFuncSeq(mixedText, unicode.IsDigit) {
+		fmt.Printf("%q\n", word)
+	}
+
+	// Output:
+	// Split on whitespace(similar to FieldsSeq):
+	// "The"
+	// "quick"
+	// "brown"
+	// "fox"
+	//
+	// Split on digits:
+	// "abc"
+	// "def"
+	// "ghi"
+}

src/bytes/iter.go

@@ -28,7 +28,6 @@ func Lines(s []byte) iter.Seq[[]byte] {
 				return
 			}
 		}
-		return
 	}
 }
 

src/clean.bat

@@ -6,27 +6,16 @@
 
 setlocal
 
-set GOBUILDFAIL=0
-
-go tool dist env -w -p >env.bat
-if errorlevel 1 goto fail
+go tool dist env -w -p >env.bat || exit /b 1
 call .\env.bat
 del env.bat
 echo.
 
-if exist %GOTOOLDIR%\dist.exe goto distok
-echo cannot find %GOTOOLDIR%\dist; nothing to clean
-goto fail
-:distok
+if not exist %GOTOOLDIR%\dist.exe (
+    echo cannot find %GOTOOLDIR%\dist.exe; nothing to clean
+    exit /b 1
+)
 
 "%GOBIN%\go" clean -i std
 "%GOBIN%\go" tool dist clean
 "%GOBIN%\go" clean -i cmd
-
-goto end
-
-:fail
-set GOBUILDFAIL=1
-
-:end
-if x%GOBUILDEXIT%==x1 exit %GOBUILDFAIL%

src/cmd/api/api_test.go

@@ -99,6 +99,11 @@ func TestGolden(t *testing.T) {
 }
 
 func TestCompareAPI(t *testing.T) {
+	if *flagCheck {
+		// not worth repeating in -check
+		t.Skip("skipping with -check set")
+	}
+
 	tests := []struct {
 		name                          string
 		features, required, exception []string
@@ -180,6 +185,11 @@ func TestCompareAPI(t *testing.T) {
 }
 
 func TestSkipInternal(t *testing.T) {
+	if *flagCheck {
+		// not worth repeating in -check
+		t.Skip("skipping with -check set")
+	}
+
 	tests := []struct {
 		pkg  string
 		want bool
@@ -294,14 +304,20 @@ func TestIssue41358(t *testing.T) {
 }
 
 func TestIssue64958(t *testing.T) {
+	if testing.Short() {
+		t.Skip("skipping with -short")
+	}
+	if *flagCheck {
+		// slow, not worth repeating in -check
+		t.Skip("skipping with -check set")
+	}
+	testenv.MustHaveGoBuild(t)
+
 	defer func() {
 		if x := recover(); x != nil {
 			t.Errorf("expected no panic; recovered %v", x)
 		}
 	}()
-
-	testenv.MustHaveGoBuild(t)
-
 	for _, context := range contexts {
 		w := NewWalker(context, "testdata/src/issue64958")
 		pkg, err := w.importFrom("p", "", 0)

src/cmd/api/main_test.go

@@ -1058,7 +1058,7 @@ func (w *Walker) emitIfaceType(name string, typ *types.Interface) {
 		if w.isDeprecated(m) {
 			w.emitf("%s //deprecated", m.Name())
 		}
-		w.emitf("%s%s", m.Name(), w.signatureString(m.Type().(*types.Signature)))
+		w.emitf("%s%s", m.Name(), w.signatureString(m.Signature()))
 	}
 
 	if !complete {
@@ -1088,7 +1088,7 @@ func (w *Walker) emitIfaceType(name string, typ *types.Interface) {
 }
 
 func (w *Walker) emitFunc(f *types.Func) {
-	sig := f.Type().(*types.Signature)
+	sig := f.Signature()
 	if sig.Recv() != nil {
 		panic("method considered a regular function: " + f.String())
 	}

src/cmd/asm/internal/arch/arm64.go

@@ -59,10 +59,10 @@ func jumpArm64(word string) bool {
 
 var arm64SpecialOperand map[string]arm64.SpecialOperand
 
-// GetARM64SpecialOperand returns the internal representation of a special operand.
-func GetARM64SpecialOperand(name string) arm64.SpecialOperand {
+// ARM64SpecialOperand returns the internal representation of a special operand.
+func ARM64SpecialOperand(name string) arm64.SpecialOperand {
 	if arm64SpecialOperand == nil {
-		// Generate the mapping automatically when the first time the function is called.
+		// Generate mapping when function is first called.
 		arm64SpecialOperand = map[string]arm64.SpecialOperand{}
 		for opd := arm64.SPOP_BEGIN; opd < arm64.SPOP_END; opd++ {
 			arm64SpecialOperand[opd.String()] = opd

src/cmd/asm/internal/arch/riscv64.go

@@ -13,9 +13,8 @@ import (
 	"cmd/internal/obj/riscv"
 )
 
-// IsRISCV64AMO reports whether the op (as defined by a riscv.A*
-// constant) is one of the AMO instructions that requires special
-// handling.
+// IsRISCV64AMO reports whether op is an AMO instruction that requires
+// special handling.
 func IsRISCV64AMO(op obj.As) bool {
 	switch op {
 	case riscv.ASCW, riscv.ASCD, riscv.AAMOSWAPW, riscv.AAMOSWAPD, riscv.AAMOADDW, riscv.AAMOADDD,
@@ -26,3 +25,33 @@ func IsRISCV64AMO(op obj.As) bool {
 	}
 	return false
 }
+
+// IsRISCV64VTypeI reports whether op is a vtype immediate instruction that
+// requires special handling.
+func IsRISCV64VTypeI(op obj.As) bool {
+	return op == riscv.AVSETVLI || op == riscv.AVSETIVLI
+}
+
+var riscv64SpecialOperand map[string]riscv.SpecialOperand
+
+// RISCV64SpecialOperand returns the internal representation of a special operand.
+func RISCV64SpecialOperand(name string) riscv.SpecialOperand {
+	if riscv64SpecialOperand == nil {
+		// Generate mapping when function is first called.
+		riscv64SpecialOperand = map[string]riscv.SpecialOperand{}
+		for opd := riscv.SPOP_BEGIN; opd < riscv.SPOP_END; opd++ {
+			riscv64SpecialOperand[opd.String()] = opd
+		}
+	}
+	if opd, ok := riscv64SpecialOperand[name]; ok {
+		return opd
+	}
+	return riscv.SPOP_END
+}
+
+// RISCV64ValidateVectorType reports whether the given configuration is a
+// valid vector type.
+func RISCV64ValidateVectorType(vsew, vlmul, vtail, vmask int64) error {
+	_, err := riscv.EncodeVectorType(vsew, vlmul, vtail, vmask)
+	return err
+}

src/cmd/asm/internal/asm/asm.go

@@ -915,6 +915,19 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
 			prog.To = a[5]
 			break
 		}
+		if p.arch.Family == sys.RISCV64 && arch.IsRISCV64VTypeI(op) {
+			prog.From = a[0]
+			vsew := p.getSpecial(prog, op, &a[1])
+			vlmul := p.getSpecial(prog, op, &a[2])
+			vtail := p.getSpecial(prog, op, &a[3])
+			vmask := p.getSpecial(prog, op, &a[4])
+			if err := arch.RISCV64ValidateVectorType(vsew, vlmul, vtail, vmask); err != nil {
+				p.errorf("invalid vtype: %v", err)
+			}
+			prog.AddRestSourceArgs([]obj.Addr{a[1], a[2], a[3], a[4]})
+			prog.To = a[5]
+			break
+		}
 		fallthrough
 	default:
 		p.errorf("can't handle %s instruction with %d operands", op, len(a))
@@ -965,3 +978,11 @@ func (p *Parser) getRegister(prog *obj.Prog, op obj.As, addr *obj.Addr) int16 {
 	}
 	return addr.Reg
 }
+
+// getSpecial checks that addr represents a special operand and returns its value.
+func (p *Parser) getSpecial(prog *obj.Prog, op obj.As, addr *obj.Addr) int64 {
+	if addr.Type != obj.TYPE_SPECIAL || addr.Name != 0 || addr.Reg != 0 || addr.Index != 0 {
+		p.errorf("%s: expected special operand; found %s", op, obj.Dconv(prog, addr))
+	}
+	return addr.Offset
+}

src/cmd/asm/internal/asm/endtoend_test.go

@@ -465,9 +465,15 @@ func TestLOONG64Encoder(t *testing.T) {
 	testEndToEnd(t, "loong64", "loong64enc1")
 	testEndToEnd(t, "loong64", "loong64enc2")
 	testEndToEnd(t, "loong64", "loong64enc3")
+	testEndToEnd(t, "loong64", "loong64enc4")
+	testEndToEnd(t, "loong64", "loong64enc5")
 	testEndToEnd(t, "loong64", "loong64")
 }
 
+func TestLOONG64Errors(t *testing.T) {
+	testErrors(t, "loong64", "loong64error")
+}
+
 func TestPPC64EndToEnd(t *testing.T) {
 	defer func(old int) { buildcfg.GOPPC64 = old }(buildcfg.GOPPC64)
 	for _, goppc64 := range []int{8, 9, 10} {
@@ -487,6 +493,10 @@ func TestRISCVErrors(t *testing.T) {
 	testErrors(t, "riscv64", "riscv64error")
 }
 
+func TestRISCVValidation(t *testing.T) {
+	testErrors(t, "riscv64", "riscv64validation")
+}
+
 func TestS390XEndToEnd(t *testing.T) {
 	testEndToEnd(t, "s390x", "s390x")
 }

src/cmd/asm/internal/asm/parse.go

@@ -21,6 +21,7 @@ import (
 	"cmd/asm/internal/lex"
 	"cmd/internal/obj"
 	"cmd/internal/obj/arm64"
+	"cmd/internal/obj/riscv"
 	"cmd/internal/obj/x86"
 	"cmd/internal/objabi"
 	"cmd/internal/src"
@@ -398,16 +399,21 @@ func (p *Parser) operand(a *obj.Addr) {
 	tok := p.next()
 	name := tok.String()
 	if tok.ScanToken == scanner.Ident && !p.atStartOfRegister(name) {
+		// See if this is an architecture specific special operand.
 		switch p.arch.Family {
 		case sys.ARM64:
-			// arm64 special operands.
-			if opd := arch.GetARM64SpecialOperand(name); opd != arm64.SPOP_END {
+			if opd := arch.ARM64SpecialOperand(name); opd != arm64.SPOP_END {
 				a.Type = obj.TYPE_SPECIAL
 				a.Offset = int64(opd)
-				break
 			}
-			fallthrough
-		default:
+		case sys.RISCV64:
+			if opd := arch.RISCV64SpecialOperand(name); opd != riscv.SPOP_END {
+				a.Type = obj.TYPE_SPECIAL
+				a.Offset = int64(opd)
+			}
+		}
+
+		if a.Type != obj.TYPE_SPECIAL {
 			// We have a symbol. Parse $sym±offset(symkind)
 			p.symbolReference(a, p.qualifySymbol(name), prefix)
 		}

src/cmd/asm/internal/asm/testdata/amd64enc_extra.s

@@ -1059,5 +1059,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
 	RDPID DX                                // f30fc7fa
 	RDPID R11                               // f3410fc7fb
 
+	ENDBR64					// f30f1efa
+
 	// End of tests.
 	RET

src/cmd/asm/internal/asm/testdata/arm64.s

@@ -1888,4 +1888,10 @@ next:
 	DC	CIGDVAC, R25                       // b97e0bd5
 	DC	CVAP, R26                          // 3a7c0bd5
 	DC	CVADP, R27                         // 3b7d0bd5
+
+// Branch Target Identification
+	BTI	C                                  // 5f2403d5
+	BTI	J                                  // 9f2403d5
+	BTI	JC                                 // df2403d5
+
 	END

src/cmd/asm/internal/asm/testdata/arm64error.s

@@ -420,4 +420,6 @@ TEXT errors(SB),$0
 	AESE	V1.B16, V2.B8                                    // ERROR "invalid arrangement"
 	SHA256SU1	V1.S4, V2.B16, V3.S4                     // ERROR "invalid arrangement"
 	SHA1H	V1.B16, V2.B16                                   // ERROR "invalid operands"
+	BTI                                       		 // ERROR "missing operand"
+	BTI	PLDL1KEEP					 // ERROR "illegal argument"
 	RET

src/cmd/asm/internal/asm/testdata/loong64enc1.s

@@ -6,12 +6,16 @@
 
 TEXT asmtest(SB),DUPOK|NOSPLIT,$0
 lable1:
-	BFPT	1(PC)			// 00050048
-	BFPT	lable1	// BFPT 2	//1ffdff4b
+	BFPT	1(PC)				// 00050048
+	BFPT	lable1		// BFPT 2	// 1ffdff4b
+	BFPT	FCC0, lable1	// BFPT FCC0, 2	// 1ff9ff4b
+	BFPT	FCC7, lable1	// BFPT FCC7, 2	// fff5ff4b
 
 lable2:
-	BFPF	1(PC)			// 00040048
-	BFPF	lable2	// BFPF 4 	// 1ffcff4b
+	BFPF	1(PC)				// 00040048
+	BFPF	lable2		// BFPF 6 	// 1ffcff4b
+	BFPF	FCC0, lable2	// BFPF FCC0, 6	// 1ff8ff4b
+	BFPF	FCC7, lable2	// BFPF FCC7, 6	// fff4ff4b
 
 	// relocation in play so the assembled offset should be 0
 	JMP	foo(SB)			// 00000050
@@ -107,8 +111,8 @@ lable2:
 	MOVV	$4(R4), R5		// 8510c002
 	MOVW	$-1, R4			// 04fcff02
 	MOVV	$-1, R4			// 04fcff02
-	MOVW	$1, R4			// 0404c002
-	MOVV	$1, R4			// 0404c002
+	MOVW	$1, R4			// 04048003
+	MOVV	$1, R4			// 04048003
 	ADD	$-1, R4, R5		// 85fcbf02
 	ADD	$-1, R4			// 84fcbf02
 	ADDV	$-1, R4, R5		// 85fcff02
@@ -346,6 +350,15 @@ lable2:
 	FTINTVF		F0, F1		// 01241b01
 	FTINTVD		F0, F1		// 01281b01
 
+	FMAXAF		F4, F5, F6	// a6900c01
+	FMAXAF		F4, F5		// a5900c01
+	FMAXAD		F4, F5, F6	// a6100d01
+	FMAXAD		F4, F5		// a5100d01
+	FMINAF		F4, F5, F6	// a6900e01
+	FMINAF		F4, F5		// a5900e01
+	FMINAD		F4, F5, F6	// a6100f01
+	FMINAD		F4, F5		// a5100f01
+
 	FTINTRMWF	F0, F2		// 02041a01
 	FTINTRMWD	F0, F2		// 02081a01
 	FTINTRMVF	F0, F2		// 02241a01
@@ -506,6 +519,16 @@ lable2:
 	XVSEQH		X3, X2, X4      // 448c0074
 	XVSEQW		X3, X2, X4      // 440c0174
 	XVSEQV		X3, X2, X4      // 448c0174
+	VSEQB		$0, V2, V3      // 43008072
+	VSEQH		$1,  V2, V3     // 43848072
+	VSEQW		$8, V2, V3      // 43208172
+	VSEQV		$15, V2, V3     // 43bc8172
+	VSEQV		$-15, V2, V3    // 43c48172
+	XVSEQB		$0, X2, X4      // 44008076
+	XVSEQH		$3, X2, X4      // 448c8076
+	XVSEQW		$12, X2, X4     // 44308176
+	XVSEQV		$15, X2, X4     // 44bc8176
+	XVSEQV		$-15, X2, X4    // 44c48176
 
 	// VPCNT{B,H,W,V}, XVPCNT{B,H,W,V} instruction
 	VPCNTB		V1, V2          // 22209c72
@@ -516,3 +539,428 @@ lable2:
 	XVPCNTH		X3, X2          // 62249c76
 	XVPCNTW		X3, X2          // 62289c76
 	XVPCNTV		X3, X2          // 622c9c76
+
+	// VANDV,VORV,VXORV,VNORV,VANDNV,VORNV
+	VANDV		V1, V2, V3      // 43042671
+	VORV		V1, V2, V3      // 43842671
+	VXORV		V1, V2, V3      // 43042771
+	VNORV		V1, V2, V3      // 43842771
+	VANDNV		V1, V2, V3      // 43042871
+	VORNV		V1, V2, V3      // 43842871
+
+	// VANDB,VORB,VXORB,VNORB
+	VANDB		$0, V2, V3      // 4300d073
+	VORB		$64, V2, V3     // 4300d573
+	VXORB		$128, V2, V3    // 4300da73
+	VNORB		$255, V2, V3    // 43fcdf73
+
+	// XVANDV,XVORV,XVXORV,XVNORV,XVANDNV,XVORNV
+	XVANDV		X1, X2, X3      // 43042675
+	XVORV		X1, X2, X3      // 43842675
+	XVXORV		X1, X2, X3      // 43042775
+	XVNORV		X1, X2, X3      // 43842775
+	XVANDNV		X1, X2, X3      // 43042875
+	XVORNV		X1, X2, X3      // 43842875
+
+	// XVANDB,XVORB,XVXORB,XVNORB
+	XVANDB		$0, X2, X3      // 4300d077
+	XVORB		$1, X2, X3      // 4304d477
+	XVXORB		$127, X2, X3    // 43fcd977
+	XVNORB		$255, X2, X3    // 43fcdf77
+
+	// MOVV C_DCON12_0, r
+	MOVV    $0x7a90000000000000, R4         // MOVV $8831558869273542656, R4        // 04a41e03
+	MOVV    $0xea90000000000000, R4         // MOVV $-1544734672188080128, R4       // 04a43a03
+
+	// MOVV C_UCON, r
+	MOVV    $0x54321000, R4                 // MOVV $1412567040, R4                 // 2464a814
+	MOVV    $0xffffffff8432f000, R4         // MOVV $-2077036544, R4                // e4650815
+
+	// MOVV C_ADDCON, r
+	MOVV    $0xfffffffffffff821, R4         // MOVV $-2015, R4                      // 0484e002
+
+	// MOVV C_ANDCON, r
+	MOVV $0x821, R4                         // MOVV $2081, R4                       // 0484a003
+
+	// ADDV C_SCON, [r1], r2
+	ADDV	$0x321, R4			// ADDV	$801, R4			// 8484cc02
+	ADDV	$0x321, R5, R4			// ADDV	$801, R5, R4			// a484cc02
+	ADDV	$0xfffffffffffffc21, R4		// ADDV	$-991, R4			// 8484f002
+	ADDV	$0xfffffffffffffc21, R5, R4	// ADDV	$-991, R5, R4			// a484f002
+
+	// AND C_SCON, [r1], r2
+	AND	$0x321, R4			// AND	$801, R4			// 84844c03
+	AND	$0x321, R5, R4			// AND	$801, R5, R4			// a4844c03
+
+	// [X]{VSLL/VSRL/VSRA/VROTR}{B,H,W,V} instructions
+	VSLLB		V1, V2, V3	// 4304e870
+	VSLLH		V1, V2, V3	// 4384e870
+	VSLLW		V1, V2, V3	// 4304e970
+	VSLLV		V1, V2, V3	// 4384e970
+	VSRLB		V1, V2, V3	// 4304ea70
+	VSRLH		V1, V2, V3	// 4384ea70
+	VSRLW		V1, V2, V3	// 4304eb70
+	VSRLV		V1, V2, V3	// 4384eb70
+	VSRAB		V1, V2, V3	// 4304ec70
+	VSRAH		V1, V2, V3	// 4384ec70
+	VSRAW		V1, V2, V3	// 4304ed70
+	VSRAV		V1, V2, V3	// 4384ed70
+	VROTRB		V1, V2, V3	// 4304ee70
+	VROTRH		V1, V2, V3	// 4384ee70
+	VROTRW		V1, V2, V3	// 4304ef70
+	VROTRV		V1, V2, V3	// 4384ef70
+	XVSLLB		X3, X2, X1	// 410ce874
+	XVSLLH		X3, X2, X1	// 418ce874
+	XVSLLW		X3, X2, X1	// 410ce974
+	XVSLLV		X3, X2, X1	// 418ce974
+	XVSRLB		X3, X2, X1	// 410cea74
+	XVSRLH		X3, X2, X1	// 418cea74
+	XVSRLW		X3, X2, X1	// 410ceb74
+	XVSRLV		X3, X2, X1	// 418ceb74
+	XVSRAB		X3, X2, X1	// 410cec74
+	XVSRAH		X3, X2, X1	// 418cec74
+	XVSRAW		X3, X2, X1	// 410ced74
+	XVSRAV		X3, X2, X1	// 418ced74
+	XVROTRB		X3, X2, X1	// 410cee74
+	XVROTRH		X3, X2, X1	// 418cee74
+	XVROTRW		X3, X2, X1	// 410cef74
+	XVROTRV		X3, X2, X1	// 418cef74
+	VSLLB		$0, V1, V2	// 22202c73
+	VSLLB		$7, V1, V2	// 223c2c73
+	VSLLB		$5, V1		// 21342c73
+	VSLLH		$0, V1, V2	// 22402c73
+	VSLLH		$15, V1, V2	// 227c2c73
+	VSLLH		$10, V1		// 21682c73
+	VSLLW		$0, V1, V2	// 22802c73
+	VSLLW		$31, V1, V2	// 22fc2c73
+	VSLLW		$11, V1		// 21ac2c73
+	VSLLV		$0, V1, V2	// 22002d73
+	VSLLV		$63, V1, V2	// 22fc2d73
+	VSLLV		$30, V1		// 21782d73
+	VSRLB		$0, V1, V2	// 22203073
+	VSRLB		$7, V1, V2	// 223c3073
+	VSRLB		$4, V1		// 21303073
+	VSRLH		$0, V1, V2	// 22403073
+	VSRLH		$15, V1, V2	// 227c3073
+	VSRLH		$9, V1		// 21643073
+	VSRLW		$0, V1, V2	// 22803073
+	VSRLW		$31, V1, V2	// 22fc3073
+	VSRLW		$16, V1		// 21c03073
+	VSRLV		$0, V1, V2	// 22003173
+	VSRLV		$63, V1, V2	// 22fc3173
+	VSRLV		$40, V1		// 21a03173
+	VSRAB		$0, V1, V2	// 22203473
+	VSRAB		$7, V1, V2	// 223c3473
+	VSRAB		$6, V1		// 21383473
+	VSRAH		$0, V1, V2	// 22403473
+	VSRAH		$15, V1, V2	// 227c3473
+	VSRAH		$8, V1		// 21603473
+	VSRAW		$0, V1, V2	// 22803473
+	VSRAW		$31, V1, V2	// 22fc3473
+	VSRAW		$12, V1		// 21b03473
+	VSRAV		$0, V1, V2	// 22003573
+	VSRAV		$63, V1, V2	// 22fc3573
+	VSRAV		$50, V1		// 21c83573
+	VROTRB		$0, V1, V2	// 2220a072
+	VROTRB		$7, V1, V2	// 223ca072
+	VROTRB		$3, V1		// 212ca072
+	VROTRH		$0, V1, V2	// 2240a072
+	VROTRH		$15, V1, V2	// 227ca072
+	VROTRH		$5, V1		// 2154a072
+	VROTRW		$0, V1, V2	// 2280a072
+	VROTRW		$31, V1, V2	// 22fca072
+	VROTRW		$18, V1		// 21c8a072
+	VROTRV		$0, V1, V2	// 2200a172
+	VROTRV		$63, V1, V2	// 22fca172
+	VROTRV		$52, V1		// 21d0a172
+	XVSLLB		$0, X2, X1	// 41202c77
+	XVSLLB		$7, X2, X1	// 413c2c77
+	XVSLLB		$4, X2		// 42302c77
+	XVSLLH		$0, X2, X1	// 41402c77
+	XVSLLH		$15, X2, X1	// 417c2c77
+	XVSLLH		$8, X2		// 42602c77
+	XVSLLW		$0, X2, X1	// 41802c77
+	XVSLLW		$31, X2, X1	// 41fc2c77
+	XVSLLW		$13, X2		// 42b42c77
+	XVSLLV		$0, X2, X1	// 41002d77
+	XVSLLV		$63, X2, X1	// 41fc2d77
+	XVSLLV		$36, X2		// 42902d77
+	XVSRLB		$0, X2, X1	// 41203077
+	XVSRLB		$7, X2, X1	// 413c3077
+	XVSRLB		$5, X2		// 42343077
+	XVSRLH		$0, X2, X1	// 41403077
+	XVSRLH		$15, X2, X1	// 417c3077
+	XVSRLH		$9, X2		// 42643077
+	XVSRLW		$0, X2, X1	// 41803077
+	XVSRLW		$31, X2, X1	// 41fc3077
+	XVSRLW		$14, X2		// 42b83077
+	XVSRLV		$0, X2, X1	// 41003177
+	XVSRLV		$63, X2, X1	// 41fc3177
+	XVSRLV		$45, X2		// 42b43177
+	XVSRAB		$0, X2, X1	// 41203477
+	XVSRAB		$7, X2, X1	// 413c3477
+	XVSRAB		$6, X2		// 42383477
+	XVSRAH		$0, X2, X1	// 41403477
+	XVSRAH		$15, X2, X1	// 417c3477
+	XVSRAH		$10, X2		// 42683477
+	XVSRAW		$0, X2, X1	// 41803477
+	XVSRAW		$31, X2, X1	// 41fc3477
+	XVSRAW		$16, X2		// 42c03477
+	XVSRAV		$0, X2, X1	// 41003577
+	XVSRAV		$63, X2, X1	// 41fc3577
+	XVSRAV		$48, X2		// 42c03577
+	XVROTRB		$0, X2, X1	// 4120a076
+	XVROTRB		$7, X2, X1	// 413ca076
+	XVROTRB		$3, X2		// 422ca076
+	XVROTRH		$0, X2, X1	// 4140a076
+	XVROTRH		$15, X2, X1	// 417ca076
+	XVROTRH		$13, X2		// 4274a076
+	XVROTRW		$0, X2, X1	// 4180a076
+	XVROTRW		$31, X2, X1	// 41fca076
+	XVROTRW		$24, X2		// 42e0a076
+	XVROTRV		$0, X2, X1	// 4100a176
+	XVROTRV		$63, X2, X1	// 41fca176
+	XVROTRV		$52, X2		// 42d0a176
+
+	// [X]VADD{B,H,W,V,Q}, [X]VSUB{B,H,W,V,Q} instructions
+	VADDB		V1, V2, V3	// 43040a70
+	VADDH		V1, V2, V3	// 43840a70
+	VADDW		V1, V2, V3	// 43040b70
+	VADDV		V1, V2, V3	// 43840b70
+	VADDQ		V1, V2, V3	// 43042d71
+	VSUBB		V1, V2, V3	// 43040c70
+	VSUBH		V1, V2, V3	// 43840c70
+	VSUBW		V1, V2, V3	// 43040d70
+	VSUBV		V1, V2, V3	// 43840d70
+	VSUBQ		V1, V2, V3	// 43842d71
+	XVADDB		X3, X2, X1	// 410c0a74
+	XVADDH		X3, X2, X1	// 418c0a74
+	XVADDW		X3, X2, X1	// 410c0b74
+	XVADDV		X3, X2, X1	// 418c0b74
+	XVADDQ		X3, X2, X1	// 410c2d75
+	XVSUBB		X3, X2, X1	// 410c0c74
+	XVSUBH		X3, X2, X1	// 418c0c74
+	XVSUBW		X3, X2, X1	// 410c0d74
+	XVSUBV		X3, X2, X1	// 418c0d74
+	XVSUBQ		X3, X2, X1	// 418c2d75
+
+	// [X]VADD{B,H,W,V}U, [X]VSUB{B,H,W,V}U instructions
+	VADDBU		$1, V2, V1	// 41048a72
+	VADDHU		$2, V2, V1	// 41888a72
+	VADDWU		$3, V2, V1	// 410c8b72
+	VADDVU		$4, V2, V1	// 41908b72
+	VSUBBU		$5, V2, V1	// 41148c72
+	VSUBHU		$6, V2, V1	// 41988c72
+	VSUBWU		$7, V2, V1	// 411c8d72
+	VSUBVU		$8, V2, V1	// 41a08d72
+	XVADDBU		$9, X1, X2	// 22248a76
+	XVADDHU		$10, X1, X2	// 22a88a76
+	XVADDWU		$11, X1, X2	// 222c8b76
+	XVADDVU		$12, X1, X2	// 22b08b76
+	XVSUBBU		$13, X1, X2	// 22348c76
+	XVSUBHU		$14, X1, X2	// 22b88c76
+	XVSUBWU		$15, X1, X2	// 223c8d76
+	XVSUBVU		$16, X1, X2	// 22c08d76
+
+	// [X]VILV{L/H}{B,H,W,V} instructions
+	VILVLB		V1, V2, V3	// 43041a71
+	VILVLH		V1, V2, V3	// 43841a71
+	VILVLW		V1, V2, V3	// 43041b71
+	VILVLV		V1, V2, V3	// 43841b71
+	VILVHB		V1, V2, V3	// 43041c71
+	VILVHH		V1, V2, V3	// 43841c71
+	VILVHW		V1, V2, V3	// 43041d71
+	VILVHV		V1, V2, V3	// 43841d71
+	XVILVLB		X3, X2, X1	// 410c1a75
+	XVILVLH		X3, X2, X1	// 418c1a75
+	XVILVLW		X3, X2, X1	// 410c1b75
+	XVILVLV		X3, X2, X1	// 418c1b75
+	XVILVHB		X3, X2, X1	// 410c1c75
+	XVILVHH		X3, X2, X1	// 418c1c75
+	XVILVHW		X3, X2, X1	// 410c1d75
+	XVILVHV		X3, X2, X1	// 418c1d75
+
+	// [X]VMUL{B/H/W/V} and [X]VMUH{B/H/W/V}[U] instructions
+	VMULB		V1, V2, V3	// 43048470
+	VMULH		V1, V2, V3	// 43848470
+	VMULW		V1, V2, V3	// 43048570
+	VMULV		V1, V2, V3	// 43848570
+	VMUHB		V1, V2, V3	// 43048670
+	VMUHH		V1, V2, V3	// 43848670
+	VMUHW		V1, V2, V3	// 43048770
+	VMUHV		V1, V2, V3	// 43848770
+	VMUHBU		V1, V2, V3	// 43048870
+	VMUHHU		V1, V2, V3	// 43848870
+	VMUHWU		V1, V2, V3	// 43048970
+	VMUHVU		V1, V2, V3	// 43848970
+	XVMULB		X3, X2, X1	// 410c8474
+	XVMULH		X3, X2, X1	// 418c8474
+	XVMULW		X3, X2, X1	// 410c8574
+	XVMULV		X3, X2, X1	// 418c8574
+	XVMUHB		X3, X2, X1	// 410c8674
+	XVMUHH		X3, X2, X1	// 418c8674
+	XVMUHW		X3, X2, X1	// 410c8774
+	XVMUHV		X3, X2, X1	// 418c8774
+	XVMUHBU		X3, X2, X1	// 410c8874
+	XVMUHHU		X3, X2, X1	// 418c8874
+	XVMUHWU		X3, X2, X1	// 410c8974
+	XVMUHVU		X3, X2, X1	// 418c8974
+
+	// [X]VDIV{B/H/W/V}[U] and [X]VMOD{B/H/W/V}[U] instructions
+	VDIVB		V1, V2, V3	// 4304e070
+	VDIVH		V1, V2, V3	// 4384e070
+	VDIVW		V1, V2, V3	// 4304e170
+	VDIVV		V1, V2, V3	// 4384e170
+	VDIVBU		V1, V2, V3	// 4304e470
+	VDIVHU		V1, V2, V3	// 4384e470
+	VDIVWU		V1, V2, V3	// 4304e570
+	VDIVVU		V1, V2, V3	// 4384e570
+	VMODB		V1, V2, V3	// 4304e270
+	VMODH		V1, V2, V3	// 4384e270
+	VMODW		V1, V2, V3	// 4304e370
+	VMODV		V1, V2, V3	// 4384e370
+	VMODBU		V1, V2, V3	// 4304e670
+	VMODHU		V1, V2, V3	// 4384e670
+	VMODWU		V1, V2, V3	// 4304e770
+	VMODVU		V1, V2, V3	// 4384e770
+	XVDIVB		X3, X2, X1	// 410ce074
+	XVDIVH		X3, X2, X1	// 418ce074
+	XVDIVW		X3, X2, X1	// 410ce174
+	XVDIVV		X3, X2, X1	// 418ce174
+	XVDIVBU		X3, X2, X1	// 410ce474
+	XVDIVHU		X3, X2, X1	// 418ce474
+	XVDIVWU		X3, X2, X1	// 410ce574
+	XVDIVVU		X3, X2, X1	// 418ce574
+	XVMODB		X3, X2, X1	// 410ce274
+	XVMODH		X3, X2, X1	// 418ce274
+	XVMODW		X3, X2, X1	// 410ce374
+	XVMODV		X3, X2, X1	// 418ce374
+	XVMODBU		X3, X2, X1	// 410ce674
+	XVMODHU		X3, X2, X1	// 418ce674
+	XVMODWU		X3, X2, X1	// 410ce774
+	XVMODVU		X3, X2, X1	// 418ce774
+
+	// [X]VF{SQRT/RECIP/RSQRT}{F/D} instructions
+	VFSQRTF		V1, V2		// 22e49c72
+	VFSQRTD		V1, V2		// 22e89c72
+	VFRECIPF	V1, V2		// 22f49c72
+	VFRECIPD	V1, V2		// 22f89c72
+	VFRSQRTF	V1, V2		// 22049d72
+	VFRSQRTD	V1, V2		// 22089d72
+	XVFSQRTF	X2, X1		// 41e49c76
+	XVFSQRTD	X2, X1		// 41e89c76
+	XVFRECIPF	X2, X1		// 41f49c76
+	XVFRECIPD	X2, X1		// 41f89c76
+	XVFRSQRTF	X2, X1		// 41049d76
+	XVFRSQRTD	X2, X1		// 41089d76
+
+	// [X]VNEG{B/H/W/V} instructions
+	VNEGB		V1, V2		// 22309c72
+	VNEGH		V1, V2		// 22349c72
+	VNEGW		V1, V2		// 22389c72
+	VNEGV		V1, V2		// 223c9c72
+	XVNEGB		X2, X1		// 41309c76
+	XVNEGH		X2, X1		// 41349c76
+	XVNEGW		X2, X1		// 41389c76
+	XVNEGV		X2, X1		// 413c9c76
+
+	// [X]{VMULW}{EV/OD}.{H.B/W.H/D.W/Q.D}[U] instructions
+	VMULWEVHB	V1, V2, V3	// 43049070
+	VMULWEVWH	V1, V2, V3	// 43849070
+	VMULWEVVW	V1, V2, V3	// 43049170
+	VMULWEVQV	V1, V2, V3	// 43849170
+	VMULWODHB	V1, V2, V3	// 43049270
+	VMULWODWH	V1, V2, V3	// 43849270
+	VMULWODVW	V1, V2, V3	// 43049370
+	VMULWODQV	V1, V2, V3	// 43849370
+	VMULWEVHBU	V1, V2, V3	// 43049870
+	VMULWEVWHU	V1, V2, V3	// 43849870
+	VMULWEVVWU	V1, V2, V3	// 43049970
+	VMULWEVQVU	V1, V2, V3	// 43849970
+	VMULWODHBU	V1, V2, V3	// 43049a70
+	VMULWODWHU	V1, V2, V3	// 43849a70
+	VMULWODVWU	V1, V2, V3	// 43049b70
+	VMULWODQVU	V1, V2, V3	// 43849b70
+	XVMULWEVHB	X1, X2, X3	// 43049074
+	XVMULWEVWH	X1, X2, X3	// 43849074
+	XVMULWEVVW	X1, X2, X3	// 43049174
+	XVMULWEVQV	X1, X2, X3	// 43849174
+	XVMULWODHB	X1, X2, X3	// 43049274
+	XVMULWODWH	X1, X2, X3	// 43849274
+	XVMULWODVW	X1, X2, X3	// 43049374
+	XVMULWODQV	X1, X2, X3	// 43849374
+	XVMULWEVHBU	X1, X2, X3	// 43049874
+	XVMULWEVWHU	X1, X2, X3	// 43849874
+	XVMULWEVVWU	X1, X2, X3	// 43049974
+	XVMULWEVQVU	X1, X2, X3	// 43849974
+	XVMULWODHBU	X1, X2, X3	// 43049a74
+	XVMULWODWHU	X1, X2, X3	// 43849a74
+	XVMULWODVWU	X1, X2, X3	// 43049b74
+	XVMULWODQVU	X1, X2, X3	// 43849b74
+
+	// [X]{VMULW}{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D} instructions
+	VMULWEVHBUB	V1, V2, V3	// 4304a070
+	VMULWEVWHUH	V1, V2, V3	// 4384a070
+	VMULWEVVWUW	V1, V2, V3	// 4304a170
+	VMULWEVQVUV	V1, V2, V3	// 4384a170
+	VMULWODHBUB	V1, V2, V3	// 4304a270
+	VMULWODWHUH	V1, V2, V3	// 4384a270
+	VMULWODVWUW	V1, V2, V3	// 4304a370
+	VMULWODQVUV	V1, V2, V3	// 4384a370
+	XVMULWEVHBUB	X1, X2, X3	// 4304a074
+	XVMULWEVWHUH	X1, X2, X3	// 4384a074
+	XVMULWEVVWUW	X1, X2, X3	// 4304a174
+	XVMULWEVQVUV	X1, X2, X3	// 4384a174
+	XVMULWODHBUB	X1, X2, X3	// 4304a274
+	XVMULWODWHUH	X1, X2, X3	// 4384a274
+	XVMULWODVWUW	X1, X2, X3	// 4304a374
+	XVMULWODQVUV	X1, X2, X3	// 4384a374
+
+	// [X]VSHUF4I.{B/H/W/D} instructions
+	VSHUF4IB	$0, V2, V1	// 41009073
+	VSHUF4IB	$16, V2, V1	// 41409073
+	VSHUF4IB	$255, V2, V1	// 41fc9373
+	VSHUF4IH	$0, V2, V1	// 41009473
+	VSHUF4IH	$128, V2, V1	// 41009673
+	VSHUF4IH	$255, V2, V1	// 41fc9773
+	VSHUF4IW	$0, V2, V1	// 41009873
+	VSHUF4IW	$96, V2, V1	// 41809973
+	VSHUF4IW	$255, V2, V1	// 41fc9b73
+	VSHUF4IV	$0, V2, V1	// 41009c73
+	VSHUF4IV	$8, V2, V1	// 41209c73
+	VSHUF4IV	$15, V2, V1	// 413c9c73
+	XVSHUF4IB	$0, X1, X2	// 22009077
+	XVSHUF4IB	$16, X1, X2	// 22409077
+	XVSHUF4IB	$255, X1, X2	// 22fc9377
+	XVSHUF4IH	$0, X1, X2	// 22009477
+	XVSHUF4IH	$128, X1, X2	// 22009677
+	XVSHUF4IH	$255, X1, X2	// 22fc9777
+	XVSHUF4IW	$0, X1, X2	// 22009877
+	XVSHUF4IW	$96, X1, X2	// 22809977
+	XVSHUF4IW	$255, X1, X2	// 22fc9b77
+	XVSHUF4IV	$0, X1, X2	// 22009c77
+	XVSHUF4IV	$8, X1, X2	// 22209c77
+	XVSHUF4IV	$15, X1, X2	// 223c9c77
+
+	// [X]VSETEQZ.V, [X]VSETNEZ.V
+	VSETEQV		V1, FCC0	// 20989c72
+	VSETNEV		V1, FCC0	// 209c9c72
+	XVSETEQV	X1, FCC0	// 20989c76
+	XVSETNEV	X1, FCC0	// 209c9c76
+	// [X]VSETANYEQZ.{B/H/W/D} instructions
+	VSETANYEQB	V1, FCC0	// 20a09c72
+	VSETANYEQH	V1, FCC0	// 20a49c72
+	VSETANYEQW	V1, FCC0	// 20a89c72
+	VSETANYEQV	V1, FCC0	// 20ac9c72
+	VSETALLNEB	V1, FCC0	// 20b09c72
+	VSETALLNEH	V1, FCC0	// 20b49c72
+	VSETALLNEW	V1, FCC0	// 20b89c72
+	VSETALLNEV	V1, FCC0	// 20bc9c72
+	XVSETANYEQB	X1, FCC0	// 20a09c76
+	XVSETANYEQH	X1, FCC0	// 20a49c76
+	XVSETANYEQW	X1, FCC0	// 20a89c76
+	XVSETANYEQV	X1, FCC0	// 20ac9c76
+	XVSETALLNEB	X1, FCC0	// 20b09c76
+	XVSETALLNEH	X1, FCC0	// 20b49c76
+	XVSETALLNEW	X1, FCC0	// 20b89c76
+	XVSETALLNEV	X1, FCC0	// 20bc9c76

src/cmd/asm/internal/asm/testdata/loong64enc2.s

@@ -12,7 +12,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
 	AND	$-1, R4, R5		// 1efcbf0285f81400
 	AND	$-1, R4			// 1efcbf0284f81400
 	MOVW	$-1, F4			// 1efcbf02c4a71401
-	MOVW	$1, F4			// 1e048002c4a71401
+	MOVW	$1, F4			// 1e048003c4a71401
 	TEQ	$4, R4, R5		// 8508005c04002a00
 	TEQ	$4, R4			// 0408005c04002a00
 	TNE	$4, R4, R5		// 8508005804002a00
@@ -77,3 +77,49 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
 	MOVH	name(SB), R4		// 1e00001ac4034028
 	MOVHU	R4, name(SB)		// 1e00001ac4034029
 	MOVHU	name(SB), R4		// 1e00001ac403402a
+
+	// MOVV C_DCON12_20S, r
+	MOVV    $0x273fffff80000000, R4         // MOVV	$2828260563841187840, R4        // 0400001584cc0903
+	MOVV    $0xf73fffff80000000, R4         // MOVV	$-630503949979353088, R4        // 0400001584cc3d03
+
+	// MOVV C_DCON20S_20, r
+	MOVV    $0xfff800000f000000, R4         // MOVV	$-2251799562027008, R4          // 04001e1404000017
+
+	// MOVV C_DCON12_12S, r
+	MOVV    $0x273ffffffffff800, R4         // MOVV	$2828260565988669440, R4        // 0400e00284cc0903
+	MOVV    $0xf73ffffffffff800, R4         // MOVV	$-630503947831871488, R4        // 0400e00284cc3d03
+
+	// MOVV C_DCON20S_12S, r
+	MOVV    $0xfff80000fffff800, R4         // MOVV	$-2251795518720000, R4          // 0400a00204000017
+	MOVV    $0xfff8000000000000, R4         // MOVV	$-2251799813685248, R4          // 0400800204000017
+
+	// MOVV C_DCON12_12U, r
+	MOVV    $0x2730000000000800, R4         // MOVV	$2823756966361303040, R4        // 0400a00384cc0903
+	MOVV    $0xf730000000000800, R4         // MOVV	$-635007547459237888, R4        // 0400a00384cc3d03
+
+	// MOVV C_DCON20S_12U, r
+	MOVV    $0xfff8000000000800, R4         // MOVV	$-2251799813683200, R4          // 0400a00304000017
+
+	// ADDV/AND C_DCON12_0, [r1], r2
+	ADDV	$0x3210000000000000, R4		// ADDV	$3607383301523767296, R4	// 1e840c0384f81000
+	ADDV	$0x3210000000000000, R5, R4	// ADDV	$3607383301523767296, R5, R4	// 1e840c03a4f81000
+	ADDV	$0xc210000000000000, R4		// ADDV	$-4463067230724161536, R4	// 1e84300384f81000
+	ADDV	$0xc210000000000000, R5, R4	// ADDV	$-4463067230724161536, R5, R4	// 1e843003a4f81000
+	AND	$0x3210000000000000, R4		// AND	$3607383301523767296, R4	// 1e840c0384f81400
+	AND	$0x3210000000000000, R5, R4	// AND	$3607383301523767296, R5, R4	// 1e840c03a4f81400
+	AND	$0xc210000000000000, R4		// AND	$-4463067230724161536, R4	// 1e84300384f81400
+	AND	$0xc210000000000000, R5, R4	// AND	$-4463067230724161536, R5, R4	// 1e843003a4f81400
+
+	// ADDV/AND C_UCON, [r1], r2
+	ADDV	$0x43210000, R4			// ADDV	$1126236160, R4			// 1e42861484f81000
+	ADDV	$0x43210000, R5, R4		// ADDV	$1126236160, R5, R4		// 1e428614a4f81000
+	ADDV	$0xffffffffc3210000, R4		// ADDV	$-1021247488, R4		// 1e42861584f81000
+	ADDV	$0xffffffffc3210000, R5, R4	// ADDV	$-1021247488, R5, R4		// 1e428615a4f81000
+	AND	$0x43210000, R4			// AND	$1126236160, R4			// 1e42861484f81400
+	AND	$0x43210000, R5, R4		// AND	$1126236160, R5, R4		// 1e428614a4f81400
+	AND	$0xffffffffc3210000, R4		// AND	$-1021247488, R4		// 1e42861584f81400
+	AND	$0xffffffffc3210000, R5, R4	// AND	$-1021247488, R5, R4		// 1e428615a4f81400
+
+	// AND C_ADDCON, [r1], r2
+	AND	$0xfffffffffffffc21, R4		// AND	$-991, R4			// 1e84b00284f81400
+	AND	$0xfffffffffffffc21, R5, R4	// AND	$-991, R5, R4			// 1e84b002a4f81400

src/cmd/asm/internal/asm/testdata/loong64enc3.s

@@ -121,3 +121,68 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
 	XOR	$74565, R4, R5			// 5e020014de178d0385f81500
 	XOR	$4097, R4			// 3e000014de07800384f81500
 	XOR	$4097, R4, R5			// 3e000014de07800385f81500
+
+	// MOVV C_DCON32_12S, r
+	MOVV    $0x27312345fffff800, R4         // MOVV	$2824077224892692480, R4        // 0400a002a468241684cc0903
+	MOVV    $0xf7312345fffff800, R4         // MOVV	$-634687288927848448, R4        // 0400a002a468241684cc3d03
+
+	// MOVV C_DCON32_0, r
+	MOVV    $0x2731234500000000, R4         // MOVV	$2824077220597727232, R4        // 04008002a468241684cc0903
+	MOVV    $0xf731234500000000, R4         // MOVV	$-634687293222813696, R4        // 04008002a468241684cc3d03
+
+	// MOVV C_DCON32_20, r
+	MOVV    $0x2731234512345000, R4         // MOVV	$2824077220903145472, R4        // a4682414a468241684cc0903
+	MOVV    $0xf731234512345000, R4         // MOVV	$-634687292917395456, R4        // a4682414a468241684cc3d03
+
+	// MOVV C_DCON12_32S, r
+	MOVV    $0x273fffff80000800, R4         // MOVV	$2828260563841189888, R4        // 040000158400a00384cc0903
+	MOVV    $0xf73fffff80000800, R4         // MOVV	$-630503949979351040, R4        // 040000158400a00384cc3d03
+
+	// MOVV C_DCON20S_32, r
+	MOVV    $0xfff8000080000800, R4         // MOVV	$-2251797666199552, R4          // 040000158400a00304000017
+
+	// MOVV C_DCON32_12U, r
+	MOVV    $0x2731234500000800, R4         // MOVV	$2824077220597729280, R4        // 0400a003a468241684cc0903
+	MOVV    $0xf731234500000800, R4         // MOVV	$-634687293222811648, R4        // 0400a003a468241684cc3d03
+
+	// ADDV/AND C_DCON12_20S, [r1], r2
+	ADDV    $0x273fffff80000000, R4         // ADDV	$2828260563841187840, R4        // 1e000015decf090384f81000
+	ADDV    $0x273fffff80000000, R4, R5     // ADDV	$2828260563841187840, R4, R5    // 1e000015decf090385f81000
+	AND     $0x273fffff80000000, R4         // AND	$2828260563841187840, R4        // 1e000015decf090384f81400
+	AND     $0x273fffff80000000, R4, R5     // AND	$2828260563841187840, R4, R5    // 1e000015decf090385f81400
+
+	// ADDV/AND C_DCON20S_20, [r1], r2
+	ADDV    $0xfff800000f000000, R4         // ADDV	$-2251799562027008, R4          // 1e001e141e00001784f81000
+	ADDV    $0xfff800000f000000, R4, R5     // ADDV	$-2251799562027008, R4, R5      // 1e001e141e00001785f81000
+	AND     $0xfff800000f000000, R4         // AND	$-2251799562027008, R4          // 1e001e141e00001784f81400
+	AND     $0xfff800000f000000, R4, R5     // AND	$-2251799562027008, R4, R5      // 1e001e141e00001785f81400
+
+	// ADDV/AND C_DCON12_12S, [r1], r2
+	ADDV    $0x273ffffffffff800, R4         // ADDV	$2828260565988669440, R4        // 1e00e002decf090384f81000
+	ADDV    $0x273ffffffffff800, R4, R5     // ADDV	$2828260565988669440, R4, R5    // 1e00e002decf090385f81000
+	AND     $0x273ffffffffff800, R4         // AND	$2828260565988669440, R4        // 1e00e002decf090384f81400
+	AND     $0x273ffffffffff800, R4, R5     // AND	$2828260565988669440, R4, R5    // 1e00e002decf090385f81400
+
+	// ADDV/AND C_DCON20S_12S, [r1], r2
+	ADDV    $0xfff80000fffff800, R4         // ADDV	$-2251795518720000, R4          // 1e00a0021e00001784f81000
+	ADDV    $0xfff80000fffff800, R4, R5     // ADDV	$-2251795518720000, R4, R5      // 1e00a0021e00001785f81000
+	AND     $0xfff80000fffff800, R4         // AND	$-2251795518720000, R4          // 1e00a0021e00001784f81400
+	AND     $0xfff80000fffff800, R4, R5     // AND	$-2251795518720000, R4, R5      // 1e00a0021e00001785f81400
+
+	// ADDV/AND C_DCON20S_0, [r1], r2
+	ADDV    $0xfff8000000000000, R4         // ADDV	$-2251799813685248, R4          // 1e0080021e00001784f81000
+	ADDV    $0xfff8000000000000, R4, R5     // ADDV	$-2251799813685248, R4, R5      // 1e0080021e00001785f81000
+	AND     $0xfff8000000000000, R4         // AND	$-2251799813685248, R4          // 1e0080021e00001784f81400
+	AND     $0xfff8000000000000, R4, R5     // AND	$-2251799813685248, R4, R5      // 1e0080021e00001785f81400
+
+	// ADDV/AND C_DCON12_12U, [r1], r2
+	ADDV    $0x2730000000000800, R4         // ADDV	$2823756966361303040, R4        // 1e00a003decf090384f81000
+	ADDV    $0x2730000000000800, R4, R5     // ADDV	$2823756966361303040, R4, R5    // 1e00a003decf090385f81000
+	AND     $0x2730000000000800, R4         // AND	$2823756966361303040, R4        // 1e00a003decf090384f81400
+	AND     $0x2730000000000800, R4, R5     // AND	$2823756966361303040, R4, R5    // 1e00a003decf090385f81400
+
+	// ADDV/AND C_DCON20S_12U, [r1], r2
+	ADDV    $0xfff8000000000800, R4         // ADDV	$-2251799813683200, R4          // 1e00a0031e00001784f81000
+	ADDV    $0xfff8000000000800, R4, R5     // ADDV	$-2251799813683200, R4, R5      // 1e00a0031e00001785f81000
+	AND     $0xfff8000000000800, R4         // AND	$-2251799813683200, R4          // 1e00a0031e00001784f81400
+	AND     $0xfff8000000000800, R4, R5     // AND	$-2251799813683200, R4, R5      // 1e00a0031e00001785f81400

src/cmd/asm/internal/asm/testdata/loong64enc4.s

@@ -0,0 +1,42 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+#include "../../../../../runtime/textflag.h"
+
+TEXT asmtest(SB),DUPOK|NOSPLIT,$0
+	// ADDV/AND C_DCON32_12S, [r1], r2
+	ADDV    $0x27312345fffff800, R4         // ADDV	$2824077224892692480, R4        // 1e00a002be682416decf090384f81000
+	ADDV    $0x27312345fffff800, R4, R5     // ADDV	$2824077224892692480, R4, R5    // 1e00a002be682416decf090385f81000
+	AND     $0x27312345fffff800, R4         // AND	$2824077224892692480, R4        // 1e00a002be682416decf090384f81400
+	AND     $0x27312345fffff800, R4, R5     // AND	$2824077224892692480, R4, R5    // 1e00a002be682416decf090385f81400
+
+	// ADDV/AND C_DCON32_0, [r1], r2
+	ADDV    $0x2731234500000000, R4         // ADDV	$2824077220597727232, R4        // 1e008002be682416decf090384f81000
+	ADDV    $0x2731234500000000, R4, R5     // ADDV	$2824077220597727232, R4, R5    // 1e008002be682416decf090385f81000
+	AND     $0x2731234500000000, R4         // AND	$2824077220597727232, R4        // 1e008002be682416decf090384f81400
+	AND     $0x2731234500000000, R4, R5     // AND	$2824077220597727232, R4, R5    // 1e008002be682416decf090385f81400
+
+	// ADDV/AND C_DCON32_20, [r1], r2
+	ADDV    $0x2731234512345000, R4         // ADDV	$2824077220903145472, R4        // be682414be682416decf090384f81000
+	ADDV    $0x2731234512345000, R4, R5     // ADDV	$2824077220903145472, R4, R5    // be682414be682416decf090385f81000
+	AND     $0x2731234512345000, R4         // AND	$2824077220903145472, R4        // be682414be682416decf090384f81400
+	AND     $0x2731234512345000, R4, R5     // AND	$2824077220903145472, R4, R5    // be682414be682416decf090385f81400
+
+	// ADDV/AND C_DCON12_32S, [r1], r2
+	ADDV    $0x273fffff80000800, R4         // ADDV	$2828260563841189888, R4        // 1e000015de03a003decf090384f81000
+	ADDV    $0x273fffff80000800, R4, R5     // ADDV	$2828260563841189888, R4, R5    // 1e000015de03a003decf090385f81000
+	AND     $0x273fffff80000800, R4         // AND	$2828260563841189888, R4        // 1e000015de03a003decf090384f81400
+	AND     $0x273fffff80000800, R4, R5     // AND	$2828260563841189888, R4, R5    // 1e000015de03a003decf090385f81400
+
+	// ADDV/AND C_DCON20S_32, [r1], r2
+	ADDV    $0xfff8000080000800, R4         // ADDV	$-2251797666199552, R4          // 1e000015de03a0031e00001784f81000
+	ADDV    $0xfff8000080000800, R4, R5     // ADDV	$-2251797666199552, R4, R5      // 1e000015de03a0031e00001785f81000
+	AND     $0xfff8000080000800, R4         // AND	$-2251797666199552, R4          // 1e000015de03a0031e00001784f81400
+	AND     $0xfff8000080000800, R4, R5     // AND	$-2251797666199552, R4, R5      // 1e000015de03a0031e00001785f81400
+
+	// ADDV/AND C_DCON32_12U, [r1], r2
+	ADDV    $0x2731234500000800, R4         // ADDV	$2824077220597729280, R4        // 1e00a003be682416decf090384f81000
+	ADDV    $0x2731234500000800, R4, R5     // ADDV	$2824077220597729280, R4, R5    // 1e00a003be682416decf090385f81000
+	AND     $0x2731234500000800, R4         // AND	$2824077220597729280, R4        // 1e00a003be682416decf090384f81400
+	AND     $0x2731234500000800, R4, R5     // AND	$2824077220597729280, R4, R5    // 1e00a003be682416decf090385f81400

src/cmd/asm/internal/asm/testdata/loong64enc5.s

@@ -0,0 +1,17 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+#include "../../../../../runtime/textflag.h"
+
+TEXT asmtest(SB),DUPOK|NOSPLIT,$0
+	// ADDV/AND C_DCON, [r1], r2
+	ADDV	$0xfedcba9876543210, R4		// ADDV	$-81985529216486896, R4		// 7ea8ec14de4388031e539717deb73f0384f81000
+	ADDV	$0xfedcba9876543210, R5, R4	// ADDV	$-81985529216486896, R5, R4	// 7ea8ec14de4388031e539717deb73f03a4f81000
+	ADDV	$0x4edcba9876543210, R4		// ADDV	$5682621993817747984, R4	// 7ea8ec14de4388031e539717deb7130384f81000
+	ADDV	$0x4edcba9876543210, R5, R4	// ADDV	$5682621993817747984, R5, R4	// 7ea8ec14de4388031e539717deb71303a4f81000
+	AND	$0x4edcba9876543210, R4		// AND	$5682621993817747984, R4	// 7ea8ec14de4388031e539717deb7130384f81400
+	AND	$0x4edcba9876543210, R5, R4	// AND	$5682621993817747984, R5, R4	// 7ea8ec14de4388031e539717deb71303a4f81400
+	AND	$0xfedcba9876543210, R4		// AND	$-81985529216486896, R4		// 7ea8ec14de4388031e539717deb73f0384f81400
+	AND	$0xfedcba9876543210, R5, R4	// AND	$-81985529216486896, R5, R4	// 7ea8ec14de4388031e539717deb73f03a4f81400
+

src/cmd/asm/internal/asm/testdata/loong64error.s

@@ -0,0 +1,7 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+TEXT errors(SB),$0
+	VSHUF4IV	$16, V1, V2	// ERROR "operand out of range 0 to 15"
+	XVSHUF4IV	$16, X1, X2	// ERROR "operand out of range 0 to 15"

src/cmd/asm/internal/asm/testdata/riscv64.s

@@ -363,6 +363,10 @@ start:
 	SLLIUW		$63, X17, X18			// 1b99f80b
 	SLLIUW		$1, X18, X19			// 9b191908
 
+	//
+	// "B" Extension for Bit Manipulation, Version 1.0.0
+	//
+
 	// 28.4.2: Basic Bit Manipulation (Zbb)
 	ANDN	X19, X20, X21				// b37a3a41 or 93caf9ffb37a5a01
 	ANDN	X19, X20				// 337a3a41 or 93cff9ff337afa01
@@ -372,14 +376,14 @@ start:
 	CPOPW	X23, X24				// 1b9c2b60
 	CTZ	X24, X25				// 931c1c60
 	CTZW	X25, X26				// 1b9d1c60
-	MAX	X26, X28, X29				// b36eae0b
-	MAX	X26, X28				// 336eae0b
-	MAXU	X28, X29, X30				// 33ffce0b
-	MAXU	X28, X29				// b3fece0b
-	MIN	X29, X30, X5				// b342df0b
-	MIN	X29, X30				// 334fdf0b
-	MINU	X30, X5, X6				// 33d3e20b
-	MINU	X30, X5					// b3d2e20b
+	MAX	X26, X28, X29				// b36eae0b or b32fae01b30ff041b34eae01b3fedf01b34ede01
+	MAX	X26, X28				// 336eae0b or b32fcd01b30ff041334ecd0133fecf01334ecd01
+	MAXU	X28, X29, X30				// 33ffce0b or b3bfce01b30ff04133cfce0133ffef0133cfee01
+	MAXU	X28, X29				// b3fece0b or b33fde01b30ff041b34ede01b3fedf01b34ede01
+	MIN	X29, X30, X5				// b342df0b or b3afee01b30ff041b342df01b3f25f00b3425f00
+	MIN	X29, X30				// 334fdf0b or b32fdf01b30ff04133cfee0133ffef0133cfee01
+	MINU	X30, X5, X6				// 33d3e20b or b33f5f00b30ff04133c3e20133f36f0033c36200
+	MINU	X30, X5					// b3d2e20b or b3bfe201b30ff041b3425f00b3f25f00b3425f00
 	ORN	X6, X7, X8				// 33e46340 or 1344f3ff33e48300
 	ORN	X6, X7					// b3e36340 or 934ff3ffb3e3f301
 	SEXTB	X16, X17				// 93184860
@@ -420,6 +424,856 @@ start:
 	BSET	$63, X9					// 9394f42b
 	BSETI	$1, X10, X11				// 93151528
 
+	//
+	// "V" Standard Extension for Vector Operations, Version 1.0
+	//
+
+	// 31.6: Configuration Setting Instructions
+	VSETVLI	X10, E8, M1, TU, MU, X12		// 57760500
+	VSETVLI	X10, E16, M1, TU, MU, X12		// 57768500
+	VSETVLI	X10, E32, M1, TU, MU, X12		// 57760501
+	VSETVLI	X10, E64, M1, TU, MU, X12		// 57768501
+	VSETVLI	X10, E32, M1, TU, MA, X12		// 57760509
+	VSETVLI	X10, E32, M1, TA, MA, X12		// 5776050d
+	VSETVLI	X10, E32, M2, TA, MA, X12		// 5776150d
+	VSETVLI	X10, E32, M4, TA, MA, X12		// 5776250d
+	VSETVLI	X10, E32, M8, TA, MA, X12		// 5776350d
+	VSETVLI	X10, E32, MF2, TA, MA, X12		// 5776550d
+	VSETVLI	X10, E32, MF4, TA, MA, X12		// 5776650d
+	VSETVLI	X10, E32, MF8, TA, MA, X12		// 5776750d
+	VSETVLI	X10, E32, M1, TA, MA, X12		// 5776050d
+	VSETVLI	$15, E32, M1, TA, MA, X12		// 57f607cd
+	VSETIVLI $0, E32, M1, TA, MA, X12		// 577600cd
+	VSETIVLI $15, E32, M1, TA, MA, X12		// 57f607cd
+	VSETIVLI $31, E32, M1, TA, MA, X12		// 57f60fcd
+	VSETVL	X10, X11, X12				// 57f6a580
+
+	// 31.7.4: Vector Unit-Stride Instructions
+	VLE8V		(X10), V3			// 87010502
+	VLE8V		(X10), V0, V3			// 87010500
+	VLE16V		(X10), V3			// 87510502
+	VLE16V		(X10), V0, V3			// 87510500
+	VLE32V		(X10), V3			// 87610502
+	VLE32V		(X10), V0, V3			// 87610500
+	VLE64V		(X10), V3			// 87710502
+	VLE64V		(X10), V0, V3			// 87710500
+	VSE8V		V3, (X10)			// a7010502
+	VSE8V		V3, V0, (X10)			// a7010500
+	VSE16V		V3, (X10)			// a7510502
+	VSE16V		V3, V0, (X10)			// a7510500
+	VSE32V		V3, (X10)			// a7610502
+	VSE32V		V3, V0, (X10)			// a7610500
+	VSE64V		V3, (X10)			// a7710502
+	VSE64V		V3, V0, (X10)			// a7710500
+	VLMV		(X10), V3			// 8701b502
+	VSMV		V3, (X10)			// a701b502
+
+	// 31.7.5: Vector Strided Instructions
+	VLSE8V		(X10), X11, V3			// 8701b50a
+	VLSE8V		(X10), X11, V0, V3		// 8701b508
+	VLSE16V		(X10), X11, V3			// 8751b50a
+	VLSE16V		(X10), X11, V0, V3		// 8751b508
+	VLSE32V		(X10), X11, V3			// 8761b50a
+	VLSE32V		(X10), X11, V0, V3		// 8761b508
+	VLSE64V		(X10), X11, V3			// 8771b50a
+	VLSE64V		(X10), X11, V0, V3		// 8771b508
+	VSSE8V		V3, X11, (X10)			// a701b50a
+	VSSE8V		V3, X11, V0, (X10)		// a701b508
+	VSSE16V		V3, X11, (X10)			// a751b50a
+	VSSE16V		V3, X11, V0, (X10)		// a751b508
+	VSSE32V		V3, X11, (X10)			// a761b50a
+	VSSE32V		V3, X11, V0, (X10)		// a761b508
+	VSSE64V		V3, X11, (X10)			// a771b50a
+	VSSE64V		V3, X11, V0, (X10)		// a771b508
+
+	// 31.7.6: Vector Indexed Instructions
+	VLUXEI8V	(X10), V2, V3			// 87012506
+	VLUXEI8V	(X10), V2, V0, V3		// 87012504
+	VLUXEI16V	(X10), V2, V3			// 87512506
+	VLUXEI16V	(X10), V2, V0, V3		// 87512504
+	VLUXEI32V	(X10), V2, V3			// 87612506
+	VLUXEI32V	(X10), V2, V0, V3		// 87612504
+	VLUXEI64V	(X10), V2, V3			// 87712506
+	VLUXEI64V	(X10), V2, V0, V3		// 87712504
+	VLOXEI8V	(X10), V2, V3			// 8701250e
+	VLOXEI8V	(X10), V2, V0, V3		// 8701250c
+	VLOXEI16V	(X10), V2, V3			// 8751250e
+	VLOXEI16V	(X10), V2, V0, V3		// 8751250c
+	VLOXEI32V	(X10), V2, V3			// 8761250e
+	VLOXEI32V	(X10), V2, V0, V3		// 8761250c
+	VLOXEI64V	(X10), V2, V3			// 8771250e
+	VLOXEI64V	(X10), V2, V0, V3		// 8771250c
+	VSUXEI8V	V3, V2, (X10)			// a7012506
+	VSUXEI8V	V3, V2, V0, (X10)		// a7012504
+	VSUXEI16V	V3, V2, (X10)			// a7512506
+	VSUXEI16V	V3, V2, V0, (X10)		// a7512504
+	VSUXEI32V	V3, V2, (X10)			// a7612506
+	VSUXEI32V	V3, V2, V0, (X10)		// a7612504
+	VSUXEI64V	V3, V2, (X10)			// a7712506
+	VSUXEI64V	V3, V2, V0, (X10)		// a7712504
+	VSOXEI8V	V3, V2, (X10)			// a701250e
+	VSOXEI8V	V3, V2, V0, (X10)		// a701250c
+	VSOXEI16V	V3, V2, (X10)			// a751250e
+	VSOXEI16V	V3, V2, V0, (X10)		// a751250c
+	VSOXEI32V	V3, V2, (X10)			// a761250e
+	VSOXEI32V	V3, V2, V0, (X10)		// a761250c
+	VSOXEI64V	V3, V2, (X10)			// a771250e
+	VSOXEI64V	V3, V2, V0, (X10)		// a771250c
+
+	// 31.7.9: Vector Load/Store Whole Register Instructions
+	VL1RV		(X10), V3			// 87018502
+	VL1RE8V		(X10), V3			// 87018502
+	VL1RE16V	(X10), V3			// 87518502
+	VL1RE32V	(X10), V3			// 87618502
+	VL1RE64V	(X10), V3			// 87718502
+	VL2RV		(X10), V2			// 07018522
+	VL2RE8V		(X10), V2			// 07018522
+	VL2RE16V	(X10), V2			// 07518522
+	VL2RE32V	(X10), V2			// 07618522
+	VL2RE64V	(X10), V2			// 07718522
+	VL4RV		(X10), V4			// 07028562
+	VL4RE8V		(X10), V4			// 07028562
+	VL4RE16V	(X10), V4			// 07528562
+	VL4RE32V	(X10), V4			// 07628562
+	VL4RE64V	(X10), V4			// 07728562
+	VL8RV		(X10), V8			// 070485e2
+	VL8RE8V		(X10), V8			// 070485e2
+	VL8RE16V	(X10), V8			// 075485e2
+	VL8RE32V	(X10), V8			// 076485e2
+	VL8RE64V	(X10), V8			// 077485e2
+	VS1RV		V3, (X11)			// a7818502
+	VS2RV		V2, (X11)			// 27818522
+	VS4RV		V4, (X11)			// 27828562
+	VS8RV		V8, (X11)			// 278485e2
+
+	// 31.11.1: Vector Single-Width Integer Add and Subtract
+	VADDVV		V1, V2, V3			// d7812002
+	VADDVV		V1, V2, V0, V3			// d7812000
+	VADDVX		X10, V2, V3			// d7412502
+	VADDVX		X10, V2, V0, V3			// d7412500
+	VADDVI		$15, V2, V3			// d7b12702
+	VADDVI		$15, V2, V0, V3			// d7b12700
+	VADDVI		$-16, V2, V3			// d7312802
+	VADDVI		$-16, V2, V0, V3		// d7312800
+	VSUBVV		V1, V2, V3			// d781200a
+	VSUBVV		V1, V2, V0, V3			// d7812008
+	VSUBVX		X10, V2, V3			// d741250a
+	VSUBVX		X10, V2, V0, V3			// d7412508
+	VRSUBVX		X10, V2, V3			// d741250e
+	VRSUBVX		X10, V2, V0, V3			// d741250c
+	VRSUBVI		$15, V2, V0, V3			// d7b1270c
+	VRSUBVI		$-16, V2, V0, V3		// d731280c
+	VNEGV		V2, V3				// d741200e
+	VNEGV		V2, V0, V3			// d741200c
+
+	// 31.11.2: Vector Widening Integer Add/Subtract
+	VWADDUVV	V1, V2, V3			// d7a120c2
+	VWADDUVV	V1, V2, V0, V3			// d7a120c0
+	VWADDUVX	X10, V2, V3			// d76125c2
+	VWADDUVX	X10, V2, V0, V3			// d76125c0
+	VWSUBUVV	V1, V2, V3			// d7a120ca
+	VWSUBUVV	V1, V2, V0, V3			// d7a120c8
+	VWSUBUVX	X10, V2, V3			// d76125ca
+	VWSUBUVX	X10, V2, V0, V3			// d76125c8
+	VWADDVV		V1, V2, V3			// d7a120c6
+	VWADDVV		V1, V2, V0, V3			// d7a120c4
+	VWADDVX		X10, V2, V3			// d76125c6
+	VWADDVX		X10, V2, V0, V3			// d76125c4
+	VWSUBVV		V1, V2, V3			// d7a120ce
+	VWSUBVV		V1, V2, V0, V3			// d7a120cc
+	VWSUBVX		X10, V2, V3			// d76125ce
+	VWSUBVX		X10, V2, V0, V3			// d76125cc
+	VWADDUWV	V1, V2, V3			// d7a120d2
+	VWADDUWV	V1, V2, V0, V3			// d7a120d0
+	VWADDUWX	X10, V2, V3			// d76125d2
+	VWADDUWX	X10, V2, V0, V3			// d76125d0
+	VWSUBUWV	V1, V2, V3			// d7a120da
+	VWSUBUWV	V1, V2, V0, V3			// d7a120d8
+	VWSUBUWX	X10, V2, V3			// d76125da
+	VWSUBUWX	X10, V2, V0, V3			// d76125d8
+	VWADDWV		V1, V2, V3			// d7a120d6
+	VWADDWV		V1, V2, V0, V3			// d7a120d4
+	VWADDWX		X10, V2, V3			// d76125d6
+	VWADDWX		X10, V2, V0, V3			// d76125d4
+	VWSUBWV		V1, V2, V3			// d7a120de
+	VWSUBWV		V1, V2, V0, V3			// d7a120dc
+	VWSUBWX		X10, V2, V3			// d76125de
+	VWSUBWX		X10, V2, V0, V3			// d76125dc
+	VWCVTXXV	V2, V3				// d76120c6
+	VWCVTXXV	V2, V0, V3			// d76120c4
+	VWCVTUXXV	V2, V3				// d76120c2
+	VWCVTUXXV	V2, V0, V3			// d76120c0
+
+	// 31.11.3: Vector Integer Extension
+	VZEXTVF2	V2, V3				// d721234a
+	VZEXTVF2	V2, V0, V3			// d7212348
+	VSEXTVF2	V2, V3				// d7a1234a
+	VSEXTVF2	V2, V0, V3			// d7a12348
+	VZEXTVF4	V2, V3				// d721224a
+	VZEXTVF4	V2, V0, V3			// d7212248
+	VSEXTVF4	V2, V3				// d7a1224a
+	VSEXTVF4	V2, V0, V3			// d7a12248
+	VZEXTVF8	V2, V3				// d721214a
+	VZEXTVF8	V2, V0, V3			// d7212148
+	VSEXTVF8	V2, V3				// d7a1214a
+	VSEXTVF8	V2, V0, V3			// d7a12148
+
+	// 31.11.4: Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+	VADCVVM		V1, V2, V0, V3			// d7812040
+	VADCVXM		X11, V2, V0, V3			// d7c12540
+	VADCVIM		$15, V2, V0, V3			// d7b12740
+	VMADCVVM	V1, V2, V0, V3			// d7812044
+	VMADCVXM	X11, V2, V0, V3			// d7c12544
+	VMADCVIM	$15, V2, V0, V3			// d7b12744
+	VMADCVV		V1, V2, V3			// d7812046
+	VMADCVX		X11, V2, V3			// d7c12546
+	VMADCVI		$15, V2, V3			// d7b12746
+	VSBCVVM		V1, V2, V0, V3			// d7812048
+	VSBCVXM		X11, V2, V0, V3			// d7c12548
+	VMSBCVVM	V1, V2, V0, V3			// d781204c
+	VMSBCVXM	X11, V2, V0, V3			// d7c1254c
+	VMSBCVV		V1, V2, V3			// d781204e
+	VMSBCVX		X11, V2, V3			// d7c1254e
+
+	// 31.11.5: Vector Bitwise Logical Instructions
+	VANDVV		V1, V2, V3			// d7812026
+	VANDVV		V1, V2, V0, V3			// d7812024
+	VANDVX		X11, V2, V3			// d7c12526
+	VANDVX		X11, V2, V0, V3			// d7c12524
+	VANDVI		$15, V2, V3			// d7b12726
+	VANDVI		$15, V2, V0, V3			// d7b12724
+	VORVV		V1, V2, V3			// d781202a
+	VORVV		V1, V2, V0, V3			// d7812028
+	VORVX		X11, V2, V3			// d7c1252a
+	VORVX		X11, V2, V0, V3			// d7c12528
+	VORVI		$15, V2, V3			// d7b1272a
+	VORVI		$15, V2, V0, V3			// d7b12728
+	VXORVV		V1, V2, V3			// d781202e
+	VXORVV		V1, V2, V0, V3			// d781202c
+	VXORVX		X11, V2, V3			// d7c1252e
+	VXORVX		X11, V2, V0, V3			// d7c1252c
+	VXORVI		$15, V2, V3			// d7b1272e
+	VXORVI		$15, V2, V0, V3			// d7b1272c
+	VNOTV		V2, V3				// d7b12f2e
+	VNOTV		V2, V0, V3			// d7b12f2c
+
+	// 31.11.6: Vector Single-Width Shift Instructions
+	VSLLVV		V1, V2, V3			// d7812096
+	VSLLVV		V1, V2, V0, V3			// d7812094
+	VSLLVX		X11, V2, V3			// d7c12596
+	VSLLVX		X11, V2, V0, V3			// d7c12594
+	VSLLVI		$15, V2, V3			// d7b12796
+	VSLLVI		$15, V2, V0, V3			// d7b12794
+	VSRLVV		V1, V2, V3			// d78120a2
+	VSRLVV		V1, V2, V0, V3			// d78120a0
+	VSRLVX		X11, V2, V3			// d7c125a2
+	VSRLVX		X11, V2, V0, V3			// d7c125a0
+	VSRLVI		$15, V2, V3			// d7b127a2
+	VSRLVI		$15, V2, V0, V3			// d7b127a0
+	VSRAVV		V1, V2, V3			// d78120a6
+	VSRAVV		V1, V2, V0, V3			// d78120a4
+	VSRAVX		X11, V2, V3			// d7c125a6
+	VSRAVX		X11, V2, V0, V3			// d7c125a4
+	VSRAVI		$15, V2, V3			// d7b127a6
+	VSRAVI		$15, V2, V0, V3			// d7b127a4
+
+	// 31.11.7: Vector Narrowing Integer Right Shift Instructions
+	VNSRLWV		V1, V2, V3			// d78120b2
+	VNSRLWV		V1, V2, V0, V3			// d78120b0
+	VNSRLWX		X10, V2, V3			// d74125b2
+	VNSRLWX		X10, V2, V0, V3			// d74125b0
+	VNSRLWI		$31, V2, V3			// d7b12fb2
+	VNSRLWI		$31, V2, V0, V3			// d7b12fb0
+	VNSRAWV		V1, V2, V3			// d78120b6
+	VNSRAWV		V1, V2, V0, V3			// d78120b4
+	VNSRAWX		X10, V2, V3			// d74125b6
+	VNSRAWX		X10, V2, V0, V3			// d74125b4
+	VNSRAWI		$31, V2, V3			// d7b12fb6
+	VNSRAWI		$31, V2, V0, V3			// d7b12fb4
+	VNCVTXXW	V2, V3				// d74120b2
+	VNCVTXXW	V2, V0, V3			// d74120b0
+
+	// 31.11.8: Vector Integer Compare Instructions
+	VMSEQVV		V1, V2, V3			// d7812062
+	VMSEQVV		V1, V2, V0, V3			// d7812060
+	VMSEQVX		X10, V2, V3			// d7412562
+	VMSEQVX		X10, V2, V0, V3			// d7412560
+	VMSEQVI		$15, V2, V3			// d7b12762
+	VMSEQVI		$15, V2, V0, V3			// d7b12760
+	VMSNEVV		V1, V2, V3			// d7812066
+	VMSNEVV		V1, V2, V0, V3			// d7812064
+	VMSNEVX		X10, V2, V3			// d7412566
+	VMSNEVX		X10, V2, V0, V3			// d7412564
+	VMSNEVI		$15, V2, V3			// d7b12766
+	VMSNEVI		$15, V2, V0, V3			// d7b12764
+	VMSLTUVV	V1, V2, V3			// d781206a
+	VMSLTUVV	V1, V2, V0, V3			// d7812068
+	VMSLTUVX	X10, V2, V3			// d741256a
+	VMSLTUVX	X10, V2, V0, V3			// d7412568
+	VMSLTVV		V1, V2, V3			// d781206e
+	VMSLTVV		V1, V2, V0, V3			// d781206c
+	VMSLTVX		X10, V2, V3			// d741256e
+	VMSLTVX		X10, V2, V0, V3			// d741256c
+	VMSLEUVV	V1, V2, V3			// d7812072
+	VMSLEUVV	V1, V2, V0, V3			// d7812070
+	VMSLEUVX	X10, V2, V3			// d7412572
+	VMSLEUVX	X10, V2, V0, V3			// d7412570
+	VMSLEUVI	$15, V2, V3			// d7b12772
+	VMSLEUVI	$15, V2, V0, V3			// d7b12770
+	VMSLEVV		V1, V2, V3			// d7812076
+	VMSLEVV		V1, V2, V0, V3			// d7812074
+	VMSLEVX		X10, V2, V3			// d7412576
+	VMSLEVX		X10, V2, V0, V3			// d7412574
+	VMSLEVI		$15, V2, V3			// d7b12776
+	VMSLEVI		$15, V2, V0, V3			// d7b12774
+	VMSGTUVX	X10, V2, V3			// d741257a
+	VMSGTUVX	X10, V2, V0, V3			// d7412578
+	VMSGTUVI	$15, V2, V3			// d7b1277a
+	VMSGTUVI	$15, V2, V0, V3			// d7b12778
+	VMSGTVX		X10, V2, V3			// d741257e
+	VMSGTVX		X10, V2, V0, V3			// d741257c
+	VMSGTVI		$15, V2, V3			// d7b1277e
+	VMSGTVI		$15, V2, V0, V3			// d7b1277c
+	VMSGTVV		V1, V2, V3			// d701116e
+	VMSGTVV		V1, V2, V0, V3			// d701116c
+	VMSGTUVV	V1, V2, V3			// d701116a
+	VMSGTUVV	V1, V2, V0, V3			// d7011168
+	VMSGEVV		V1, V2, V3			// d7011176
+	VMSGEVV		V1, V2, V0, V3			// d7011174
+	VMSGEUVV	V1, V2, V3			// d7011172
+	VMSGEUVV	V1, V2, V0, V3			// d7011170
+	VMSLTVI		$15, V2, V3			// d7312776
+	VMSLTVI		$15, V2, V0, V3			// d7312774
+	VMSLTUVI	$15, V2, V3			// d7312772
+	VMSLTUVI	$15, V2, V0, V3			// d7312770
+	VMSGEVI		$15, V2, V3			// d731277e
+	VMSGEVI		$15, V2, V0, V3			// d731277c
+	VMSGEUVI	$15, V2, V3			// d731277a
+	VMSGEUVI	$15, V2, V0, V3			// d7312778
+
+	// 31.11.9: Vector Integer Min/Max Instructions
+	VMINUVV		V1, V2, V3			// d7812012
+	VMINUVV		V1, V2, V0, V3			// d7812010
+	VMINUVX		X10, V2, V3			// d7412512
+	VMINUVX		X10, V2, V0, V3			// d7412510
+	VMINVV		V1, V2, V3			// d7812016
+	VMINVV		V1, V2, V0, V3			// d7812014
+	VMINVX		X10, V2, V3			// d7412516
+	VMINVX		X10, V2, V0, V3			// d7412514
+	VMAXUVV		V1, V2, V3			// d781201a
+	VMAXUVV		V1, V2, V0, V3			// d7812018
+	VMAXUVX		X10, V2, V3			// d741251a
+	VMAXUVX		X10, V2, V0, V3			// d7412518
+	VMAXVV		V1, V2, V3			// d781201e
+	VMAXVV		V1, V2, V0, V3			// d781201c
+	VMAXVX		X10, V2, V3			// d741251e
+	VMAXVX		X10, V2, V0, V3			// d741251c
+
+	// 31.11.10: Vector Single-Width Integer Multiply Instructions
+	VMULVV		V1, V2, V3			// d7a12096
+	VMULVV		V1, V2, V0, V3			// d7a12094
+	VMULVX		X10, V2, V3			// d7612596
+	VMULVX		X10, V2, V0, V3			// d7612594
+	VMULHVV		V1, V2, V3			// d7a1209e
+	VMULHVV		V1, V2, V0, V3			// d7a1209c
+	VMULHVX		X10, V2, V3			// d761259e
+	VMULHVX		X10, V2, V0, V3			// d761259c
+	VMULHUVV	V1, V2, V3			// d7a12092
+	VMULHUVV	V1, V2, V0, V3			// d7a12090
+	VMULHUVX	X10, V2, V3			// d7612592
+	VMULHUVX	X10, V2, V0, V3			// d7612590
+	VMULHSUVV	V1, V2, V3			// d7a1209a
+	VMULHSUVV	V1, V2, V0, V3			// d7a12098
+	VMULHSUVX	X10, V2, V3			// d761259a
+	VMULHSUVX	X10, V2, V0, V3			// d7612598
+
+	// 31.11.11: Vector Integer Divide Instructions
+	VDIVUVV		V1, V2, V3			// d7a12082
+	VDIVUVV		V1, V2, V0, V3			// d7a12080
+	VDIVUVX		X10, V2, V3			// d7612582
+	VDIVUVX		X10, V2, V0, V3			// d7612580
+	VDIVVV		V1, V2, V3			// d7a12086
+	VDIVVV		V1, V2, V0, V3			// d7a12084
+	VDIVVX		X10, V2, V3			// d7612586
+	VDIVVX		X10, V2, V0, V3			// d7612584
+	VREMUVV		V1, V2, V3			// d7a1208a
+	VREMUVV		V1, V2, V0, V3			// d7a12088
+	VREMUVX		X10, V2, V3			// d761258a
+	VREMUVX		X10, V2, V0, V3			// d7612588
+	VREMVV		V1, V2, V3			// d7a1208e
+	VREMVV		V1, V2, V0, V3			// d7a1208c
+	VREMVX		X10, V2, V3			// d761258e
+	VREMVX		X10, V2, V0, V3			// d761258c
+
+	// 31.11.12: Vector Widening Integer Multiply Instructions
+	VWMULVV		V1, V2, V3			// d7a120ee
+	VWMULVV		V1, V2, V0, V3			// d7a120ec
+	VWMULVX		X10, V2, V3			// d76125ee
+	VWMULVX		X10, V2, V0, V3			// d76125ec
+	VWMULUVV	V1, V2, V3			// d7a120e2
+	VWMULUVV	V1, V2, V0, V3			// d7a120e0
+	VWMULUVX	X10, V2, V3			// d76125e2
+	VWMULUVX	X10, V2, V0, V3			// d76125e0
+	VWMULSUVV	V1, V2, V3			// d7a120ea
+	VWMULSUVV	V1, V2, V0, V3			// d7a120e8
+	VWMULSUVX	X10, V2, V3			// d76125ea
+	VWMULSUVX	X10, V2, V0, V3			// d76125e8
+
+	// 31.11.13: Vector Single-Width Integer Multiply-Add Instructions
+	VMACCVV		V1, V2, V3			// d7a120b6
+	VMACCVV		V1, V2, V0, V3			// d7a120b4
+	VMACCVX		X10, V2, V3			// d76125b6
+	VMACCVX		X10, V2, V0, V3			// d76125b4
+	VNMSACVV	V1, V2, V3			// d7a120be
+	VNMSACVV	V1, V2, V0, V3			// d7a120bc
+	VNMSACVX	X10, V2, V3			// d76125be
+	VNMSACVX	X10, V2, V0, V3			// d76125bc
+	VMADDVV		V1, V2, V3			// d7a120a6
+	VMADDVV		V1, V2, V0, V3			// d7a120a4
+	VMADDVX		X10, V2, V3			// d76125a6
+	VMADDVX		X10, V2, V0, V3			// d76125a4
+	VNMSUBVV	V1, V2, V3			// d7a120ae
+	VNMSUBVV	V1, V2, V0, V3			// d7a120ac
+	VNMSUBVX	X10, V2, V3			// d76125ae
+	VNMSUBVX	X10, V2, V0, V3			// d76125ac
+
+	// 31.11.14: Vector Widening Integer Multiply-Add Instructions
+	VWMACCUVV	V1, V2, V3			// d7a120f2
+	VWMACCUVV	V1, V2, V0, V3			// d7a120f0
+	VWMACCUVX	X10, V2, V3			// d76125f2
+	VWMACCUVX	X10, V2, V0, V3			// d76125f0
+	VWMACCVV	V1, V2, V3			// d7a120f6
+	VWMACCVV	V1, V2, V0, V3			// d7a120f4
+	VWMACCVX	X10, V2, V3			// d76125f6
+	VWMACCVX	X10, V2, V0, V3			// d76125f4
+	VWMACCSUVV	V1, V2, V3			// d7a120fe
+	VWMACCSUVV	V1, V2, V0, V3			// d7a120fc
+	VWMACCSUVX	X10, V2, V3			// d76125fe
+	VWMACCSUVX	X10, V2, V0, V3			// d76125fc
+	VWMACCUSVX	X10, V2, V3			// d76125fa
+	VWMACCUSVX	X10, V2, V0, V3			// d76125f8
+
+	// 31.11.15: Vector Integer Merge Instructions
+	VMERGEVVM	V1, V2, V0, V3			// d781205c
+	VMERGEVXM	X10, V2, V0, V3			// d741255c
+	VMERGEVIM	$15, V2, V0, V3			// d7b1275c
+
+	// 31.11.16: Vector Integer Move Instructions
+	VMVVV		V2, V3				// d701015e
+	VMVVX		X10, V3				// d741055e
+	VMVVI		$15, V3				// d7b1075e
+
+	// 31.12.1: Vector Single-Width Saturating Add and Subtract
+	VSADDUVV	V1, V2, V3			// d7812082
+	VSADDUVV	V1, V2, V0, V3			// d7812080
+	VSADDUVX	X10, V2, V3			// d7412582
+	VSADDUVX	X10, V2, V0, V3			// d7412580
+	VSADDUVI	$15, V2, V3			// d7b12782
+	VSADDUVI	$15, V2, V0, V3			// d7b12780
+	VSADDVV		V1, V2, V3			// d7812086
+	VSADDVV		V1, V2, V0, V3			// d7812084
+	VSADDVX		X10, V2, V3			// d7412586
+	VSADDVX		X10, V2, V0, V3			// d7412584
+	VSADDVI		$15, V2, V3			// d7b12786
+	VSADDVI		$15, V2, V0, V3			// d7b12784
+	VSSUBUVV	V1, V2, V3			// d781208a
+	VSSUBUVV	V1, V2, V0, V3			// d7812088
+	VSSUBUVX	X10, V2, V3			// d741258a
+	VSSUBUVX	X10, V2, V0, V3			// d7412588
+	VSSUBVV		V1, V2, V3			// d781208e
+	VSSUBVV		V1, V2, V0, V3			// d781208c
+	VSSUBVX		X10, V2, V3			// d741258e
+	VSSUBVX		X10, V2, V0, V3			// d741258c
+
+	// 31.12.2: Vector Single-Width Averaging Add and Subtract
+	VAADDUVV	V1, V2, V3			// d7a12022
+	VAADDUVV	V1, V2, V0, V3			// d7a12020
+	VAADDUVX	X10, V2, V3			// d7612522
+	VAADDUVX	X10, V2, V0, V3			// d7612520
+	VAADDVV		V1, V2, V3			// d7a12026
+	VAADDVV		V1, V2, V0, V3			// d7a12024
+	VAADDVX		X10, V2, V3			// d7612526
+	VAADDVX		X10, V2, V0, V3			// d7612524
+	VASUBUVV	V1, V2, V3			// d7a1202a
+	VASUBUVV	V1, V2, V0, V3			// d7a12028
+	VASUBUVX	X10, V2, V3			// d761252a
+	VASUBUVX	X10, V2, V0, V3			// d7612528
+	VASUBVV		V1, V2, V3			// d7a1202e
+	VASUBVV		V1, V2, V0, V3			// d7a1202c
+	VASUBVX		X10, V2, V3			// d761252e
+	VASUBVX		X10, V2, V0, V3			// d761252c
+
+	// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
+	VSMULVV		V1, V2, V3			// d781209e
+	VSMULVV		V1, V2, V0, V3			// d781209c
+	VSMULVX		X10, V2, V3			// d741259e
+	VSMULVX		X10, V2, V0, V3			// d741259c
+
+	// 31.12.4: Vector Single-Width Scaling Shift Instructions
+	VSSRLVV		V1, V2, V3			// d78120aa
+	VSSRLVV		V1, V2, V0, V3			// d78120a8
+	VSSRLVX		X10, V2, V3			// d74125aa
+	VSSRLVX		X10, V2, V0, V3			// d74125a8
+	VSSRLVI		$15, V2, V3			// d7b127aa
+	VSSRLVI		$15, V2, V0, V3			// d7b127a8
+	VSSRAVV		V1, V2, V3			// d78120ae
+	VSSRAVV		V1, V2, V0, V3			// d78120ac
+	VSSRAVX		X10, V2, V3			// d74125ae
+	VSSRAVX		X10, V2, V0, V3			// d74125ac
+	VSSRAVI		$16, V2, V3			// d73128ae
+	VSSRAVI		$16, V2, V0, V3			// d73128ac
+
+	// 31.12.5: Vector Narrowing Fixed-Point Clip Instructions
+	VNCLIPUWV	V1, V2, V3			// d78120ba
+	VNCLIPUWV	V1, V2, V0, V3			// d78120b8
+	VNCLIPUWX	X10, V2, V3			// d74125ba
+	VNCLIPUWX	X10, V2, V0, V3			// d74125b8
+	VNCLIPUWI	$16, V2, V3			// d73128ba
+	VNCLIPUWI	$16, V2, V0, V3			// d73128b8
+	VNCLIPWV	V1, V2, V3			// d78120be
+	VNCLIPWV	V1, V2, V0, V3			// d78120bc
+	VNCLIPWX	X10, V2, V3			// d74125be
+	VNCLIPWX	X10, V2, V0, V3			// d74125bc
+	VNCLIPWI	$16, V2, V3			// d73128be
+	VNCLIPWI	$16, V2, V0, V3			// d73128bc
+
+	// 31.13.2: Vector Single-Width Floating-Point Add/Subtract Instructions
+	VFADDVV		V1, V2, V3			// d7912002
+	VFADDVV		V1, V2, V0, V3			// d7912000
+	VFADDVF		F10, V2, V3			// d7512502
+	VFADDVF		F10, V2, V0, V3			// d7512500
+	VFSUBVV		V1, V2, V3			// d791200a
+	VFSUBVV		V1, V2, V0, V3			// d7912008
+	VFSUBVF		F10, V2, V3			// d751250a
+	VFSUBVF		F10, V2, V0, V3			// d7512508
+	VFRSUBVF	F10, V2, V3			// d751259e
+	VFRSUBVF	F10, V2, V0, V3			// d751259c
+
+	// 31.13.3: Vector Widening Floating-Point Add/Subtract Instructions
+	VFWADDVV	V1, V2, V3			// d79120c2
+	VFWADDVV	V1, V2, V0, V3			// d79120c0
+	VFWADDVF	F10, V2, V3			// d75125c2
+	VFWADDVF	F10, V2, V0, V3			// d75125c0
+	VFWSUBVV	V1, V2, V3			// d79120ca
+	VFWSUBVV	V1, V2, V0, V3			// d79120c8
+	VFWSUBVF	F10, V2, V3			// d75125ca
+	VFWSUBVF	F10, V2, V0, V3			// d75125c8
+	VFWADDWV	V1, V2, V3			// d79120d2
+	VFWADDWV	V1, V2, V0, V3			// d79120d0
+	VFWADDWF	F10, V2, V3			// d75125d2
+	VFWADDWF	F10, V2, V0, V3			// d75125d0
+	VFWSUBWV	V1, V2, V3			// d79120da
+	VFWSUBWV	V1, V2, V0, V3			// d79120d8
+	VFWSUBWF	F10, V2, V3			// d75125da
+	VFWSUBWF	F10, V2, V0, V3			// d75125d8
+
+	// 31.13.4: Vector Single-Width Floating-Point Multiply/Divide Instructions
+	VFMULVV		V1, V2, V3			// d7912092
+	VFMULVV		V1, V2, V0, V3			// d7912090
+	VFMULVF		F10, V2, V3			// d7512592
+	VFMULVF		F10, V2, V0, V3			// d7512590
+	VFDIVVV		V1, V2, V3			// d7912082
+	VFDIVVV		V1, V2, V0, V3			// d7912080
+	VFDIVVF		F10, V2, V3			// d7512582
+	VFDIVVF		F10, V2, V0, V3			// d7512580
+	VFRDIVVF	F10, V2, V3			// d7512586
+	VFRDIVVF	F10, V2, V0, V3			// d7512584
+
+	// 31.13.5: Vector Widening Floating-Point Multiply
+	VFWMULVV	V1, V2, V3			// d79120e2
+	VFWMULVV	V1, V2, V0, V3			// d79120e0
+	VFWMULVF	F10, V2, V3			// d75125e2
+	VFWMULVF	F10, V2, V0, V3			// d75125e0
+
+	// 31.13.6: Vector Single-Width Floating-Point Fused Multiply-Add Instructions
+	VFMACCVV	V2, V1, V3			// d79120b2
+	VFMACCVV	V2, V1, V0, V3			// d79120b0
+	VFMACCVF	V2, F10, V3			// d75125b2
+	VFMACCVF	V2, F10, V0, V3			// d75125b0
+	VFNMACCVV	V2, V1, V3			// d79120b6
+	VFNMACCVV	V2, V1, V0, V3			// d79120b4
+	VFNMACCVF	V2, F10, V3			// d75125b6
+	VFNMACCVF	V2, F10, V0, V3			// d75125b4
+	VFMSACVV	V2, V1, V3			// d79120ba
+	VFMSACVV	V2, V1, V0, V3			// d79120b8
+	VFMSACVF	V2, F10, V3			// d75125ba
+	VFMSACVF	V2, F10, V0, V3			// d75125b8
+	VFNMSACVV	V2, V1, V3			// d79120be
+	VFNMSACVV	V2, V1, V0, V3			// d79120bc
+	VFNMSACVF	V2, F10, V3			// d75125be
+	VFNMSACVF	V2, F10, V0, V3			// d75125bc
+	VFMADDVV	V2, V1, V3			// d79120a2
+	VFMADDVV	V2, V1, V0, V3			// d79120a0
+	VFMADDVF	V2, F10, V3			// d75125a2
+	VFMADDVF	V2, F10, V0, V3			// d75125a0
+	VFNMADDVV	V2, V1, V3			// d79120a6
+	VFNMADDVV	V2, V1, V0, V3			// d79120a4
+	VFNMADDVF	V2, F10, V3			// d75125a6
+	VFNMADDVF	V2, F10, V0, V3			// d75125a4
+	VFMSUBVV	V2, V1, V3			// d79120aa
+	VFMSUBVV	V2, V1, V0, V3			// d79120a8
+	VFMSUBVF	V2, F10, V3			// d75125aa
+	VFMSUBVF	V2, F10, V0, V3			// d75125a8
+	VFNMSUBVV	V2, V1, V3			// d79120ae
+	VFNMSUBVV	V2, V1, V0, V3			// d79120ac
+	VFNMSUBVF	V2, F10, V3			// d75125ae
+	VFNMSUBVF	V2, F10, V0, V3			// d75125ac
+
+	// 31.13.7: Vector Widening Floating-Point Fused Multiply-Add Instructions
+	VFWMACCVV	V2, V1, V3			// d79120f2
+	VFWMACCVV	V2, V1, V0, V3			// d79120f0
+	VFWMACCVF	V2, F10, V3			// d75125f2
+	VFWMACCVF	V2, F10, V0, V3			// d75125f0
+	VFWNMACCVV	V2, V1, V3			// d79120f6
+	VFWNMACCVV	V2, V1, V0, V3			// d79120f4
+	VFWNMACCVF	V2, F10, V3			// d75125f6
+	VFWNMACCVF	V2, F10, V0, V3			// d75125f4
+	VFWMSACVV	V2, V1, V3			// d79120fa
+	VFWMSACVV	V2, V1, V0, V3			// d79120f8
+	VFWMSACVF	V2, F10, V3			// d75125fa
+	VFWMSACVF	V2, F10, V0, V3			// d75125f8
+	VFWNMSACVV	V2, V1, V3			// d79120fe
+	VFWNMSACVV	V2, V1, V0, V3			// d79120fc
+	VFWNMSACVF	V2, F10, V3			// d75125fe
+	VFWNMSACVF	V2, F10, V0, V3			// d75125fc
+
+	// 31.13.8: Vector Floating-Point Square-Root Instruction
+	VFSQRTV		V2, V3				// d711204e
+	VFSQRTV		V2, V0, V3			// d711204c
+
+	// 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction
+	VFRSQRT7V	V2, V3				// d711224e
+	VFRSQRT7V	V2, V0, V3			// d711224c
+
+	// 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction
+	VFREC7V		V2, V3				// d791224e
+	VFREC7V		V2, V0, V3			// d791224c
+
+	// 31.13.11: Vector Floating-Point MIN/MAX Instructions
+	VFMINVV		V1, V2, V3			// d7912012
+	VFMINVV		V1, V2, V0, V3			// d7912010
+	VFMINVF		F10, V2, V3			// d7512512
+	VFMINVF		F10, V2, V0, V3			// d7512510
+	VFMAXVV		V1, V2, V3			// d791201a
+	VFMAXVV		V1, V2, V0, V3			// d7912018
+	VFMAXVF		F10, V2, V3			// d751251a
+	VFMAXVF		F10, V2, V0, V3			// d7512518
+
+	// 31.13.12: Vector Floating-Point Sign-Injection Instructions
+	VFSGNJVV	V1, V2, V3			// d7912022
+	VFSGNJVV	V1, V2, V0, V3			// d7912020
+	VFSGNJVF	F10, V2, V3			// d7512522
+	VFSGNJVF	F10, V2, V0, V3			// d7512520
+	VFSGNJNVV	V1, V2, V3			// d7912026
+	VFSGNJNVV	V1, V2, V0, V3			// d7912024
+	VFSGNJNVF	F10, V2, V3			// d7512526
+	VFSGNJNVF	F10, V2, V0, V3			// d7512524
+	VFSGNJXVV	V1, V2, V3			// d791202a
+	VFSGNJXVV	V1, V2, V0, V3			// d7912028
+	VFSGNJXVF	F10, V2, V3			// d751252a
+	VFSGNJXVF	F10, V2, V0, V3			// d7512528
+	VFNEGV		V2, V3				// d7112126
+	VFNEGV		V2, V0, V3			// d7112124
+	VFABSV		V2, V3				// d711212a
+	VFABSV		V2, V0, V3			// d7112128
+
+	// 31.13.13: Vector Floating-Point Compare Instructions
+	VMFEQVV		V1, V2, V3			// d7912062
+	VMFEQVV		V1, V2, V0, V3			// d7912060
+	VMFEQVF		F10, V2, V3			// d7512562
+	VMFEQVF		F10, V2, V0, V3			// d7512560
+	VMFNEVV		V1, V2, V3			// d7912072
+	VMFNEVV		V1, V2, V0, V3			// d7912070
+	VMFNEVF		F10, V2, V3			// d7512572
+	VMFNEVF		F10, V2, V0, V3			// d7512570
+	VMFLTVV		V1, V2, V3			// d791206e
+	VMFLTVV		V1, V2, V0, V3			// d791206c
+	VMFLTVF		F10, V2, V3			// d751256e
+	VMFLTVF		F10, V2, V0, V3			// d751256c
+	VMFLEVV		V1, V2, V3			// d7912066
+	VMFLEVV		V1, V2, V0, V3			// d7912064
+	VMFLEVF		F10, V2, V3			// d7512566
+	VMFLEVF		F10, V2, V0, V3			// d7512564
+	VMFGTVF		F10, V2, V3			// d7512576
+	VMFGTVF		F10, V2, V0, V3			// d7512574
+	VMFGEVF		F10, V2, V3			// d751257e
+	VMFGEVF		F10, V2, V0, V3			// d751257c
+	VMFGTVV		V1, V2, V3			// d711116e
+	VMFGTVV		V1, V2, V0, V3			// d711116c
+	VMFGEVV		V1, V2, V3			// d7111166
+	VMFGEVV		V1, V2, V0, V3			// d7111164
+
+	// 31.13.14: Vector Floating-Point Classify Instruction
+	VFCLASSV	V2, V3				// d711284e
+	VFCLASSV	V2, V0, V3			// d711284c
+
+	// 31.13.15: Vector Floating-Point Merge Instruction
+	VFMERGEVFM	F10, V2, V0, V3			// d751255c
+
+	// 31.13.16: Vector Floating-Point Move Instruction
+	VFMVVF		F10, V3				// d751055e
+
+	// 31.13.17: Single-Width Floating-Point/Integer Type-Convert Instructions
+	VFCVTXUFV	V2, V3				// d711204a
+	VFCVTXUFV	V2, V0, V3			// d7112048
+	VFCVTXFV	V2, V3				// d791204a
+	VFCVTXFV	V2, V0, V3			// d7912048
+	VFCVTRTZXUFV	V2, V3				// d711234a
+	VFCVTRTZXUFV	V2, V0, V3			// d7112348
+	VFCVTRTZXFV	V2, V3				// d791234a
+	VFCVTRTZXFV	V2, V0, V3			// d7912348
+	VFCVTFXUV	V2, V3				// d711214a
+	VFCVTFXUV	V2, V0, V3			// d7112148
+	VFCVTFXV	V2, V3				// d791214a
+	VFCVTFXV	V2, V0, V3			// d7912148
+
+	// 31.13.18: Widening Floating-Point/Integer Type-Convert Instructions
+	VFWCVTXUFV	V2, V3				// d711244a
+	VFWCVTXUFV	V2, V0, V3			// d7112448
+	VFWCVTXFV	V2, V3				// d791244a
+	VFWCVTXFV	V2, V0, V3			// d7912448
+	VFWCVTRTZXUFV	V2, V3				// d711274a
+	VFWCVTRTZXUFV	V2, V0, V3			// d7112748
+	VFWCVTRTZXFV	V2, V3				// d791274a
+	VFWCVTRTZXFV	V2, V0, V3			// d7912748
+	VFWCVTFXUV	V2, V3				// d711254a
+	VFWCVTFXUV	V2, V0, V3			// d7112548
+	VFWCVTFXV	V2, V3				// d791254a
+	VFWCVTFXV	V2, V0, V3			// d7912548
+	VFWCVTFFV	V2, V3				// d711264a
+	VFWCVTFFV	V2, V0, V3			// d7112648
+
+	// 31.13.19: Narrowing Floating-Point/Integer Type-Convert Instructions
+	VFNCVTXUFW	V2, V3				// d711284a
+	VFNCVTXUFW	V2, V0, V3			// d7112848
+	VFNCVTXFW	V2, V3				// d791284a
+	VFNCVTXFW	V2, V0, V3			// d7912848
+	VFNCVTRTZXUFW	V2, V3				// d7112b4a
+	VFNCVTRTZXUFW	V2, V0, V3			// d7112b48
+	VFNCVTRTZXFW	V2, V3				// d7912b4a
+	VFNCVTRTZXFW	V2, V0, V3			// d7912b48
+	VFNCVTFXUW	V2, V3				// d711294a
+	VFNCVTFXUW	V2, V0, V3			// d7112948
+	VFNCVTFXW	V2, V3				// d791294a
+	VFNCVTFXW	V2, V0, V3			// d7912948
+	VFNCVTFFW	V2, V3				// d7112a4a
+	VFNCVTFFW	V2, V0, V3			// d7112a48
+	VFNCVTRODFFW	V2, V3				// d7912a4a
+	VFNCVTRODFFW	V2, V0, V3			// d7912a48
+
+	// 31.14.1: Vector Single-Width Integer Reduction Instructions
+	VREDSUMVS	V1, V2, V3			// d7a12002
+	VREDSUMVS	V1, V2, V0, V3			// d7a12000
+	VREDMAXUVS	V1, V2, V3			// d7a1201a
+	VREDMAXUVS	V1, V2, V0, V3			// d7a12018
+	VREDMAXVS	V1, V2, V3			// d7a1201e
+	VREDMAXVS	V1, V2, V0, V3			// d7a1201c
+	VREDMINUVS	V1, V2, V3			// d7a12012
+	VREDMINUVS	V1, V2, V0, V3			// d7a12010
+	VREDMINVS	V1, V2, V3			// d7a12016
+	VREDMINVS	V1, V2, V0, V3			// d7a12014
+	VREDANDVS	V1, V2, V3			// d7a12006
+	VREDANDVS	V1, V2, V0, V3			// d7a12004
+	VREDORVS	V1, V2, V3			// d7a1200a
+	VREDORVS	V1, V2, V0, V3			// d7a12008
+	VREDXORVS	V1, V2, V3			// d7a1200e
+	VREDXORVS	V1, V2, V0, V3			// d7a1200c
+
+	// 31.14.2: Vector Widening Integer Reduction Instructions
+	VWREDSUMUVS	V1, V2, V3			// d78120c2
+	VWREDSUMUVS	V1, V2, V0, V3			// d78120c0
+	VWREDSUMVS	V1, V2, V3			// d78120c6
+	VWREDSUMVS	V1, V2, V0, V3			// d78120c4
+
+	// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
+	VFREDOSUMVS	V1, V2, V3			// d791200e
+	VFREDOSUMVS	V1, V2, V0, V3			// d791200c
+	VFREDUSUMVS	V1, V2, V3			// d7912006
+	VFREDUSUMVS	V1, V2, V0, V3			// d7912004
+	VFREDMAXVS	V1, V2, V3			// d791201e
+	VFREDMAXVS	V1, V2, V0, V3			// d791201c
+	VFREDMINVS	V1, V2, V3			// d7912016
+	VFREDMINVS	V1, V2, V0, V3			// d7912014
+
+	// 31.14.4: Vector Widening Floating-Point Reduction Instructions
+	VFWREDOSUMVS	V1, V2, V3			// d79120ce
+	VFWREDOSUMVS	V1, V2, V0, V3			// d79120cc
+	VFWREDUSUMVS	V1, V2, V3			// d79120c6
+	VFWREDUSUMVS	V1, V2, V0, V3			// d79120c4
+
+	// 31.15: Vector Mask Instructions
+	VMANDMM		V1, V2, V3			// d7a12066
+	VMNANDMM	V1, V2, V3			// d7a12076
+	VMANDNMM	V1, V2, V3			// d7a12062
+	VMXORMM		V1, V2, V3			// d7a1206e
+	VMORMM		V1, V2, V3			// d7a1206a
+	VMNORMM		V1, V2, V3			// d7a1207a
+	VMORNMM		V1, V2, V3			// d7a12072
+	VMXNORMM	V1, V2, V3			// d7a1207e
+	VMMVM		V2, V3				// d7212166
+	VMCLRM		V3				// d7a1316e
+	VMSETM		V3				// d7a1317e
+	VMNOTM		V2, V3				// d7212176
+	VCPOPM		V2, X10				// 57252842
+	VCPOPM		V2, V0, X10			// 57252840
+	VFIRSTM		V2, X10				// 57a52842
+	VFIRSTM		V2, V0, X10			// 57a52840
+	VMSBFM		V2, V3				// d7a12052
+	VMSBFM		V2, V0, V3			// d7a12050
+	VMSIFM		V2, V3				// d7a12152
+	VMSIFM		V2, V0, V3			// d7a12150
+	VMSOFM		V2, V3				// d7212152
+	VMSOFM		V2, V0, V3			// d7212150
+	VIOTAM		V2, V3				// d7212852
+	VIOTAM		V2, V0, V3			// d7212850
+	VIDV		V3				// d7a10852
+	VIDV		V0, V3				// d7a10850
+
+	// 31.16.1: Integer Scalar Move Instructions
+	VMVXS		V2, X10				// 57252042
+	VMVSX		X10, V2				// 57610542
+
+	// 31.16.2: Floating-Point Scalar Move Instructions
+	VFMVFS		V2, F10				// 57152042
+	VFMVSF		F10, V2				// 57510542
+
+	// 31.16.3: Vector Slide Instructions
+	VSLIDEUPVX	X10, V2, V3			// d741253a
+	VSLIDEUPVX	X10, V2, V0, V3			// d7412538
+	VSLIDEUPVI	$16, V2, V3			// d731283a
+	VSLIDEUPVI	$16, V2, V0, V3			// d7312838
+	VSLIDEDOWNVX	X10, V2, V3			// d741253e
+	VSLIDEDOWNVX	X10, V2, V0, V3			// d741253c
+	VSLIDEDOWNVI	$16, V2, V3			// d731283e
+	VSLIDEDOWNVI	$16, V2, V0, V3			// d731283c
+	VSLIDE1UPVX	X10, V2, V3			// d761253a
+	VSLIDE1UPVX	X10, V2, V0, V3			// d7612538
+	VFSLIDE1UPVF	F10, V2, V3			// d751253a
+	VFSLIDE1UPVF	F10, V2, V0, V3			// d7512538
+	VSLIDE1DOWNVX	X10, V2, V3			// d761253e
+	VSLIDE1DOWNVX	X10, V2, V0, V3			// d761253c
+	VFSLIDE1DOWNVF	F10, V2, V3			// d751253e
+	VFSLIDE1DOWNVF	F10, V2, V0, V3			// d751253c
+
+	// 31.16.4: Vector Register Gather Instructions
+	VRGATHERVV	V1, V2, V3			// d7812032
+	VRGATHERVV	V1, V2, V0, V3			// d7812030
+	VRGATHEREI16VV	V1, V2, V3			// d781203a
+	VRGATHEREI16VV	V1, V2, V0, V3			// d7812038
+	VRGATHERVX	X10, V2, V3			// d7412532
+	VRGATHERVX	X10, V2, V0, V3			// d7412530
+	VRGATHERVI	$16, V2, V3			// d7312832
+	VRGATHERVI	$16, V2, V0, V3			// d7312830
+
+	// 31.16.5: Vector Compress Instruction
+	VCOMPRESSVM	V1, V2, V3			// d7a1205e
+
+	// 31.16.6: Whole Vector Register Move
+	VMV1RV		V2, V1				// d730209e
+	VMV2RV		V12, V10			// 57b5c09e
+	VMV4RV		V8, V4				// 57b2819e
+	VMV8RV		V8, V0				// 57b0839e
+
 	//
 	// Privileged ISA
 	//
@@ -435,20 +1289,36 @@ start:
 	WORD	$0x9abcdef0	// WORD $2596069104	// f0debc9a
 
 	// MOV pseudo-instructions
-	MOV	X5, X6					// 13830200
-	MOV	$2047, X5				// 9302f07f
-	MOV	$-2048, X5				// 93020080
-	MOV	$2048, X5				// b71200009b820280
-	MOV	$-2049, X5				// b7f2ffff9b82f27f
-	MOV	$4096, X5				// b7120000
-	MOV	$2147479552, X5				// b7f2ff7f
-	MOV	$2147483647, X5				// b70200809b82f2ff
-	MOV	$-2147483647, X5			// b70200809b821200
+	MOV	X5, X6								// 13830200
+	MOV	$2047, X5							// 9302f07f
+	MOV	$-2048, X5							// 93020080
+	MOV	$2048, X5							// b71200009b820280
+	MOV	$-2049, X5							// b7f2ffff9b82f27f
+	MOV	$4096, X5							// b7120000
+	MOV	$0x7ffff000, X5		// MOV	$2147479552, X5			// b7f2ff7f
+	MOV	$-0x7ffff000, X5	// MOV	$-2147479552, X5		// b7120080
+	MOV	$0x7fffffff, X5		// MOV	$2147483647, X5			// b70200809b82f2ff
+	MOV	$-0x7fffffff, X5	// MOV	$-2147483647, X5		// b70200809b821200
+
+	// Converted to load and shift(s)
+	MOV	$0xffffffff, X5		// MOV	$4294967295, X5			// 9302f0ff93d20202
+	MOV	$0x100000000, X5	// MOV	$4294967296, X5			// 9302100093920202
+	MOV	$0xfffffffffffda, X5	// MOV	$4503599627370458, X5		// 9302d0fe9392d20093d2c200
+	MOV	$0xffffffffffffe, X5	// MOV	$4503599627370494, X5		// 9302f0ff9392d20093d2c200
+	MOV	$0x7fffffff00000000, X5	// MOV	$9223372032559808512, X5	// b70200809b82f2ff93920202
+	MOV	$0x8000000100000000, X5	// MOV	$-9223372032559808512, X5	// b70200809b82120093920202
+	MOV	$0xffffffff00000000, X5	// MOV	$-4294967296, X5		// 9302f0ff93920202
+	MOV	$0x1ffffffff0000000, X5	// MOV	$2305843008945258496, X5	// 9302f0ff9392f20193d23200
+	MOV	$0x7fffffffffffffff, X5 // MOV	$9223372036854775807, X5	// 9302f0ff93d21200
 
 	// Converted to load of symbol (AUIPC + LD)
-	MOV	$4294967295, X5				// 9702000083b20200
-	// Converted to MOV $1, X5 + SLLI $32, X5
-	MOV	$4294967296, X5				// 9302100093920202
+	MOV	$0x80000001, X5		// MOV	$2147483649, X5			// 9702000083b20200
+	MOV	$0x100000001, X5	// MOV	$4294967297, X5			// 9702000083b20200
+	MOV	$0x0800000010000000, X5	// MOV	$576460752571858944, X5		// 9702000083b20200
+	MOV	$0x8000000010000000, X5	// MOV	$-9223372036586340352, X5	// 9702000083b20200
+	MOV	$0x0abcdabcd0000000, X5	// MOV	$773733740479250432, X5		// 9702000083b20200
+	MOV	$0x8abcdabcd0000000, X5	// MOV	$-8449638296375525376, X5	// 9702000083b20200
+	MOV	$0xfff0000000ffffff, X5 // MOV	$-4503599610593281, X5		// 9702000083b20200
 
 	MOV	(X5), X6				// 03b30200
 	MOV	4(X5), X6				// 03b34200
@@ -482,6 +1352,9 @@ start:
 	MOVD	F0, 4(X5)				// 27b20200
 	MOVD	F0, F1					// d3000022
 
+	// Convert to load of symbol (AUIPC + FLD)
+	MOVD	$(709.78271289338397), F3		// 970f000087b10f00
+
 	// TLS load with local-exec (LUI + ADDIW + ADD of TP + load)
 	MOV	tls(SB), X5				// b70f00009b8f0f00b38f4f0083b20f00
 	MOVB	tls(SB), X5				// b70f00009b8f0f00b38f4f0083820f00

src/cmd/asm/internal/asm/testdata/riscv64error.s

@@ -30,6 +30,8 @@ TEXT errors(SB),$0
 	SLLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
 	SRLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
 	SRAI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
+	BEQ	X5, X6, $1			// ERROR "instruction with branch-like opcode lacks destination"
+	BEQ	X5, X6, 31(X10)			// ERROR "instruction with branch-like opcode lacks destination"
 	RORI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
 	SLLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
 	SRLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
@@ -43,7 +45,340 @@ TEXT errors(SB),$0
 	SRLIW	$-1, X5, X6			// ERROR "immediate out of range 0 to 31"
 	SRAIW	$-1, X5, X6			// ERROR "immediate out of range 0 to 31"
 	SD	X5, 4294967296(X6)		// ERROR "constant 4294967296 too large"
-	SRLI	$1, X5, F1			// ERROR "expected integer register in rd position but got non-integer register F1"
-	SRLI	$1, F1, X5			// ERROR "expected integer register in rs1 position but got non-integer register F1"
 	FNES	F1, (X5)			// ERROR "needs an integer register output"
+
+	//
+	// "V" Standard Extension for Vector Operations, Version 1.0
+	//
+	VSETIVLI	X10, E32, M2, TA, MA, X12	// ERROR "expected immediate value"
+	VLE8V		(X10), V1, V3			// ERROR "invalid vector mask register"
+	VSE8V		V3, V1, (X10)			// ERROR "invalid vector mask register"
+	VLSE8V		(X10), X10, V1, V3		// ERROR "invalid vector mask register"
+	VSSE8V		V3, X11, V1, (X10)		// ERROR "invalid vector mask register"
+	VLUXEI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"
+	VSUXEI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
+	VLOXEI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"
+	VSOXEI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
+	VL1RV		(X10), V0, V3			// ERROR "too many operands for instruction"
+	VS1RV		V3, V0, (X11)			// ERROR "too many operands for instruction"
+	VADDVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VADDVX		X10, V2, V1, V3			// ERROR "invalid vector mask register"
+	VADDVI		$15, V4, V1, V2			// ERROR "invalid vector mask register"
+	VSUBVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSUBVX		X10, V2, V1, V3			// ERROR "invalid vector mask register"
+	VRSUBVX		X10, V2, V1, V3			// ERROR "invalid vector mask register"
+	VRSUBVI		$15, V4, V1, V2			// ERROR "invalid vector mask register"
+	VNEGV		V2, V3, V4			// ERROR "invalid vector mask register"
+	VWADDUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWADDUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWSUBUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWSUBUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWADDVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWADDVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWSUBVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWSUBVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWADDUWV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWADDUWX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWSUBUWV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWSUBUWX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWADDWV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWADDWX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWSUBWV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWSUBWX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWCVTXXV	V2, V1, V3			// ERROR "invalid vector mask register"
+	VWCVTUXXV	V2, V1, V3			// ERROR "invalid vector mask register"
+	VZEXTVF2	V2, V3, V4			// ERROR "invalid vector mask register"
+	VSEXTVF2	V2, V3, V4			// ERROR "invalid vector mask register"
+	VZEXTVF4	V2, V3, V4			// ERROR "invalid vector mask register"
+	VSEXTVF4	V2, V3, V4			// ERROR "invalid vector mask register"
+	VZEXTVF8	V2, V3, V4			// ERROR "invalid vector mask register"
+	VSEXTVF8	V2, V3, V4			// ERROR "invalid vector mask register"
+	VADCVVM		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VADCVVM		V1, V2, V3			// ERROR "invalid vector mask register"
+	VADCVXM		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VADCVXM		X10, V2, V3			// ERROR "invalid vector mask register"
+	VADCVIM		$15, V2, V1, V3			// ERROR "invalid vector mask register"
+	VADCVIM		$15, V2, V3			// ERROR "invalid vector mask register"
+	VMADCVVM	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMADCVVM	V1, V2, V3			// ERROR "invalid vector mask register"
+	VMADCVXM	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMADCVXM	X10, V2, V3			// ERROR "invalid vector mask register"
+	VMADCVIM	$15, V2, V1, V3			// ERROR "invalid vector mask register"
+	VMADCVIM	$15, V2, V3			// ERROR "invalid vector mask register"
+	VSBCVVM		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSBCVVM		V1, V2, V3			// ERROR "invalid vector mask register"
+	VSBCVXM		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSBCVXM		X10, V2, V3			// ERROR "invalid vector mask register"
+	VMSBCVVM	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSBCVVM	V1, V2, V3			// ERROR "invalid vector mask register"
+	VMSBCVXM	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSBCVXM	X10, V2, V3			// ERROR "invalid vector mask register"
+	VANDVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VANDVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VANDVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VORVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VORVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VORVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VXORVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VXORVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VXORVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNOTV		V1, V2, V3			// ERROR "invalid vector mask register"
+	VSLLVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSLLVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSLLVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSRLVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSRLVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSRLVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSRAVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSRAVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSRAVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNSRLWV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNSRLWX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNSRLWI		$31, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNSRAWV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNSRAWX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNSRAWI		$31, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNCVTXXW	V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSEQVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSEQVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSEQVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSNEVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSNEVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSNEVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLTUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLTUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLTVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLTVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLEUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLEUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLEUVI	$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLEVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLEVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLEVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSGTUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSGTUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSGTUVI	$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSGTVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSGTVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSGTVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSGEVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSGEUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLTVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSLTUVI	$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSGEVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSGEUVI	$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMINUVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMINUVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMINVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMINVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMAXUVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMAXUVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMAXVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMAXVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMULVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMULVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMULHVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMULHVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMULHUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMULHUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMULHSUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMULHSUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VDIVUVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VDIVUVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VDIVVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VDIVVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VREMUVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VREMUVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VREMVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VREMVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMULVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMULVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMULUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMULUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMULSUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMULSUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMACCVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMACCVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNMSACVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNMSACVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMADDVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMADDVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNMSUBVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNMSUBVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMACCUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMACCUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMACCVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMACCVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMACCSUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMACCSUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWMACCUSVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMERGEVVM	V1, V2, V3			// ERROR "invalid vector mask register"
+	VMERGEVVM	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMERGEVXM	X10, V2, V3			// ERROR "invalid vector mask register"
+	VMERGEVXM	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMERGEVIM	$15, V2, V3			// ERROR "invalid vector mask register"
+	VMERGEVIM	$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMVVV		V1, V2, V3			// ERROR "too many operands for instruction"
+	VMVVX		X10, V2, V3			// ERROR "too many operands for instruction"
+	VMVVI		$15, V2, V3			// ERROR "too many operands for instruction"
+	VSADDUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSADDUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSADDUVI	$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSADDVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSADDVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSADDVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSSUBUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSSUBUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSSUBVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSSUBVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VAADDUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VAADDUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VAADDVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VAADDVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VASUBUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VASUBUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VASUBVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VASUBVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSMULVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSMULVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSSRLVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSSRLVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSSRLVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSSRAVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSSRAVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSSRAVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNCLIPUWV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNCLIPUWX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNCLIPUWI	$16, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNCLIPWV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNCLIPWX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VNCLIPWI	$16, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFADDVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFADDVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFSUBVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFSUBVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFRSUBVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWADDVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWADDVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWSUBVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWSUBVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWADDWV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWADDWF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWSUBWV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWSUBWF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFMULVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFMULVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFDIVVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFDIVVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFRDIVVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWMULVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWMULVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFMACCVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFMACCVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFNMACCVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFNMACCVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFMSACVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFMSACVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFNMSACVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFNMSACVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFMADDVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFMADDVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFNMADDVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFNMADDVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFMSUBVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFMSUBVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFNMSUBVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFNMSUBVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFWMACCVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFWMACCVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFWNMACCVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFWNMACCVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFWMSACVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFWMSACVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFWNMSACVV	V2, V1, V4, V3			// ERROR "invalid vector mask register"
+	VFWNMSACVF	V2, F10, V4, V3			// ERROR "invalid vector mask register"
+	VFSQRTV		V2, V4, V3			// ERROR "invalid vector mask register"
+	VFRSQRT7V	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFREC7V		V2, V4, V3			// ERROR "invalid vector mask register"
+	VFMINVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFMINVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFMAXVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFMAXVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFSGNJVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFSGNJVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFSGNJNVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFSGNJNVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFSGNJXVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFSGNJXVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFNEGV		V2, V4, V3			// ERROR "invalid vector mask register"
+	VFABSV		V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFEQVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFEQVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFNEVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFNEVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFLTVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFLTVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFLEVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFLEVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFGTVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFGEVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFGTVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VMFGEVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFMERGEVFM	X10, V2, V3			// ERROR "invalid vector mask register"
+	VFMERGEVFM	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFCVTXUFV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFCVTXFV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFCVTRTZXUFV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFCVTRTZXFV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFCVTFXUV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFCVTFXV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWCVTXUFV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWCVTXFV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWCVTRTZXUFV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWCVTRTZXFV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWCVTFXUV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWCVTFXV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWCVTFFV	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFNCVTXUFW	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFNCVTXFW	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFNCVTRTZXUFW	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFNCVTRTZXFW	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFNCVTFXUW	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFNCVTFXW	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFNCVTFFW	V2, V4, V3			// ERROR "invalid vector mask register"
+	VFNCVTRODFFW	V2, V4, V3			// ERROR "invalid vector mask register"
+	VREDSUMVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VREDMAXUVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VREDMAXVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VREDMINUVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VREDMINVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VREDANDVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VREDORVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VREDXORVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWREDSUMUVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VWREDSUMVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFREDOSUMVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFREDUSUMVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFREDMAXVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFREDMINVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFWREDOSUMVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VCPOPM		V2, V4, X10			// ERROR "invalid vector mask register"
+	VFIRSTM		V2, V4, X10			// ERROR "invalid vector mask register"
+	VMSBFM		V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSIFM		V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSOFM		V2, V4, V3			// ERROR "invalid vector mask register"
+	VIOTAM		V2, V4, V3			// ERROR "invalid vector mask register"
+	VSLIDEUPVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSLIDEUPVI	$16, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSLIDEDOWNVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSLIDEDOWNVI	$16, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSLIDE1UPVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFSLIDE1UPVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VSLIDE1DOWNVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VFSLIDE1DOWNVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VRGATHERVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VRGATHEREI16VV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VRGATHERVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"
+	VRGATHERVI	$16, V2, V4, V3			// ERROR "invalid vector mask register"
+
 	RET

src/cmd/asm/internal/asm/testdata/riscv64validation.s

@@ -0,0 +1,431 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// This file is for validation errors only, i.e., errors reported by the validate function.
+// Negative test cases for errors generated earlier in the assembler's preprocess stage
+// should be added to riscv64error.s.  If they are added to this file, they will prevent
+// the validate function from being run and TestRISCVValidation will report missing
+// errors.
+
+TEXT validation(SB),$0
+	SRLI	$1, X5, F1			// ERROR "expected integer register in rd position but got non-integer register F1"
+	SRLI	$1, F1, X5			// ERROR "expected integer register in rs1 position but got non-integer register F1"
+
+	//
+	// "V" Standard Extension for Vector Operations, Version 1.0
+	//
+	VSETVLI		$32, E16, M1, TU, MU, X12	// ERROR "must be in range [0, 31] (5 bits)"
+	VSETVLI		$-1, E32, M2, TA, MA, X12	// ERROR "must be in range [0, 31] (5 bits)"
+	VSETVL		X10, X11			// ERROR "expected integer register in rs1 position"
+	VLE8V		(X10), X10			// ERROR "expected vector register in vd position"
+	VLE8V		(V1), V3			// ERROR "expected integer register in rs1 position"
+	VSE8V		X10, (X10)			// ERROR "expected vector register in vs1 position"
+	VSE8V		V3, (V1)			// ERROR "expected integer register in rd position"
+	VLSE8V		(X10), V3			// ERROR "expected integer register in rs2 position"
+	VLSE8V		(X10), X10, X11			// ERROR "expected vector register in vd position"
+	VLSE8V		(V1), X10, V3			// ERROR "expected integer register in rs1 position"
+	VLSE8V		(X10), V1, V0, V3		// ERROR "expected integer register in rs2 position"
+	VSSE8V		V3, (X10)			// ERROR "expected integer register in rs2 position"
+	VSSE8V		X10, X11, (X10)			// ERROR "expected vector register in vd position"
+	VSSE8V		V3, X11, (V1)			// ERROR "expected integer register in rs1 position"
+	VSSE8V		V3, V1, V0, (X10)		// ERROR "expected integer register in rs2 position"
+	VLUXEI8V	(X10), V2, X11			// ERROR "expected vector register in vd position"
+	VLUXEI8V	(X10), V2, X11			// ERROR "expected vector register in vd position"
+	VLUXEI8V	(V1), V2, V3			// ERROR "expected integer register in rs1 position"
+	VLUXEI8V	(X10), X11, V0, V3		// ERROR "expected vector register in vs2 position"
+	VSUXEI8V	X10, V2, (X10)			// ERROR "expected vector register in vd position"
+	VSUXEI8V	V3, V2, (V1)			// ERROR "expected integer register in rs1 position"
+	VSUXEI8V	V3, X11, V0, (X10)		// ERROR "expected vector register in vs2 position"
+	VLOXEI8V	(X10), V2, X11			// ERROR "expected vector register in vd position"
+	VLOXEI8V	(V1), V2, V3			// ERROR "expected integer register in rs1 position"
+	VLOXEI8V	(X10), X11, V0, V3		// ERROR "expected vector register in vs2 position"
+	VSOXEI8V	X10, V2, (X10)			// ERROR "expected vector register in vd position"
+	VSOXEI8V	V3, V2, (V1)			// ERROR "expected integer register in rs1 position"
+	VSOXEI8V	V3, X11, V0, (X10)		// ERROR "expected vector register in vs2 position"
+	VL1RV		(X10), X10			// ERROR "expected vector register in vd position"
+	VL1RV		(V1), V3			// ERROR "expected integer register in rs1 position"
+	VS1RV		X11, (X11)			// ERROR "expected vector register in vs1 position"
+	VS1RV		V3, (V1)			// ERROR "expected integer register in rd position"
+	VADDVV		V1, X10, V3			// ERROR "expected vector register in vs2 position"
+	VADDVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VADDVI		$16, V4, V2			// ERROR "signed immediate 16 must be in range [-16, 15] (5 bits)"
+	VADDVI		$-17, V4, V2			// ERROR "signed immediate -17 must be in range [-16, 15] (5 bits)"
+	VSUBVV		V1, X10, V3			// ERROR "expected vector register in vs2 position"
+	VSUBVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VRSUBVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VRSUBVI		$16, V4, V2			// ERROR "signed immediate 16 must be in range [-16, 15] (5 bits)"
+	VRSUBVI		$-17, V4, V2			// ERROR "signed immediate -17 must be in range [-16, 15] (5 bits)"
+	VNEGV		X10, V3				// ERROR "expected vector register in vs2 position"
+	VNEGV		V2				// ERROR "expected vector register in vd position"
+	VWADDUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWADDUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWSUBUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWSUBUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWADDVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWADDVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWSUBVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWSUBVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWADDUWV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWADDUWX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWSUBUWV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWSUBUWX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWADDWV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWADDWX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWSUBWV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWSUBWX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWCVTXXV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VWCVTUXXV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VZEXTVF2	V2, V0, V3, V4			// ERROR "expected no register in rs3"
+	VZEXTVF2	X10, V3				// ERROR "expected vector register in vs2 position"
+	VSEXTVF2	V2, V0, V3, V4			// ERROR "expected no register in rs3"
+	VSEXTVF2	X10, V3				// ERROR "expected vector register in vs2 position"
+	VZEXTVF4	V2, V0, V3, V4			// ERROR "expected no register in rs3"
+	VZEXTVF4	X10, V3				// ERROR "expected vector register in vs2 position"
+	VSEXTVF4	V2, V0, V3, V4			// ERROR "expected no register in rs3"
+	VSEXTVF4	X10, V3				// ERROR "expected vector register in vs2 position"
+	VZEXTVF8	V2, V0, V3, V4			// ERROR "expected no register in rs3"
+	VZEXTVF8	X10, V3				// ERROR "expected vector register in vs2 position"
+	VSEXTVF8	V2, V0, V3, V4			// ERROR "expected no register in rs3"
+	VSEXTVF8	X10, V3				// ERROR "expected vector register in vs2 position"
+	VADCVVM		X10, V2, V0, V3			// ERROR "expected vector register in vs1 position"
+	VADCVXM		V1, V2, V0, V3			// ERROR "expected integer register in rs1 position"
+	VADCVIM		$16, V2, V0, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VADCVIM		$-17, V2, V0, V3		// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMADCVVM	X10, V2, V0, V3			// ERROR "expected vector register in vs1 position"
+	VMADCVXM	V1, V2, V0, V3			// ERROR "expected integer register in rs1 position"
+	VMADCVIM	$16, V2, V0, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMADCVIM	$-17, V2, V0, V3		// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMADCVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMADCVV		V1, V2, V0, V3			// ERROR "expected no register in rs3"
+	VMADCVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMADCVX		X10, V2, V0, V3			// ERROR "expected no register in rs3"
+	VMADCVI		$16, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMADCVI		$-17, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMADCVI		$15, V2, V0, V3			// ERROR "expected no register in rs3"
+	VSBCVVM		X10, V2, V0, V3			// ERROR "expected vector register in vs1 position"
+	VSBCVXM		V1, V2, V0, V3			// ERROR "expected integer register in rs1 position"
+	VMSBCVVM	X10, V2, V0, V3			// ERROR "expected vector register in vs1 position"
+	VMSBCVXM	V1, V2, V0, V3			// ERROR "expected integer register in rs1 position"
+	VMSBCVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMSBCVV		V1, V2, V0, V3			// ERROR "expected no register in rs3"
+	VMSBCVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMSBCVX		X10, V2, V0, V3			// ERROR "expected no register in rs3"
+	VANDVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VANDVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VANDVI		$16, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VANDVI		$-17, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VORVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VORVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VORVI		$16, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VORVI		$-17, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VXORVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VXORVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VXORVI		$16, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VXORVI		$-17, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VNOTV		V3				// ERROR "expected vector register in vd position"
+	VNOTV		X10, V3				// ERROR "expected vector register in vs2 position"
+	VSLLVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VSLLVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VSLLVI		$32, V2, V3			// ERROR "unsigned immediate 32 must be in range [0, 31]"
+	VSLLVI		$-1, V2, V3			// ERROR "unsigned immediate -1 must be in range [0, 31]"
+	VSRLVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VSRLVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VSRLVI		$32, V2, V3			// ERROR "unsigned immediate 32 must be in range [0, 31]"
+	VSRLVI		$-1, V2, V3			// ERROR "unsigned immediate -1 must be in range [0, 31]"
+	VSRAVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VSRAVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VSRAVI		$32, V2, V3			// ERROR "unsigned immediate 32 must be in range [0, 31]"
+	VSRAVI		$-1, V2, V3			// ERROR "unsigned immediate -1 must be in range [0, 31]"
+	VNSRLWV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VNSRLWX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VNSRLWI		$32, V2, V3			// ERROR "unsigned immediate 32 must be in range [0, 31]"
+	VNSRLWI		$-1, V2, V3			// ERROR "unsigned immediate -1 must be in range [0, 31]"
+	VNSRAWV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VNSRAWX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VNSRAWI		$32, V2, V3			// ERROR "unsigned immediate 32 must be in range [0, 31]"
+	VNSRAWI		$-1, V2, V3			// ERROR "unsigned immediate -1 must be in range [0, 31]"
+	VNCVTXXW	X10, V3				// ERROR "expected vector register in vs2 position"
+	VMSEQVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMSEQVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMSEQVI		$16, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMSEQVI		$-17, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMSNEVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMSNEVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMSNEVI		$16, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMSNEVI		$-17, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMSLTUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMSLTUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMSLTVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMSLTVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMSLEUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMSLEUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMSLEUVI	$16, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMSLEUVI	$-17, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMSLEVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMSLEVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMSLEVI		$16, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMSLEVI		$-17, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMSGTUVV	X10, V2, V3			// ERROR "expected vector register in vs2 position"
+	VMSGTUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMSGTUVI	$16, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMSGTUVI	$-17, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMSGTVV		X10, V2, V3			// ERROR "expected vector register in vs2 position"
+	VMSGTVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMSGTVI		$16, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMSGTVI		$-17, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMSGEVV		X10, V2, V3			// ERROR "expected vector register in vs2 position"
+	VMSGEUVV	X10, V2, V3			// ERROR "expected vector register in vs2 position"
+	VMSLTVI		$17, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMSLTVI		$-16, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMSLTUVI	$17, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMSLTUVI	$-16, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMSGEVI		$17, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMSGEVI		$-16, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMSGEUVI	$17, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMSGEUVI	$-16, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMINUVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMINUVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMINVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMINVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMAXUVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMAXUVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMAXVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMAXVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMULVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMULVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMULHVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMULHVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMULHUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMULHUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMULHSUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMULHSUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VDIVUVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VDIVUVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VDIVVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VDIVVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VREMUVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VREMUVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VREMVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VREMVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWMULVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWMULVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWMULUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWMULUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWMULSUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWMULSUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMACCVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMACCVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VNMSACVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VNMSACVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMADDVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMADDVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VNMSUBVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VNMSUBVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWMACCUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWMACCUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWMACCVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWMACCVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWMACCSUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWMACCSUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VWMACCUSVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VMERGEVVM	X10, V2, V0, V3			// ERROR "expected vector register in vs1 position"
+	VMERGEVXM	V1, V2, V0, V3			// ERROR "expected integer register in rs1 position"
+	VMERGEVIM	$16, V2, V0, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMERGEVIM	$-17, V2, V0, V3		// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VMVVV		X10, V3				// ERROR "expected vector register in vs1 position"
+	VMVVX		V1, V2				// ERROR "expected integer register in rs1 position"
+	VMVVI		$16, V2				// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VMVVI		$-17, V2			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VSADDUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VSADDUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VSADDUVI	$16, V2, V3			// ERROR "signed immediate 16 must be in range [-16, 15]"
+	VSADDUVI	$-17, V2, V3			// ERROR "signed immediate -17 must be in range [-16, 15]"
+	VSSUBUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VSSUBUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VAADDUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VAADDUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VAADDVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VAADDVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VASUBUVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VASUBUVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VASUBVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VASUBVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VSMULVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VSMULVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VSSRLVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VSSRLVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VSSRLVI		$32, V2, V3			// ERROR "signed immediate 32 must be in range [0, 31]"
+	VSSRLVI		$-1, V2, V3			// ERROR "signed immediate -1 must be in range [0, 31]"
+	VSSRAVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VSSRAVX		V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VSSRAVI		$32, V2, V3			// ERROR "signed immediate 32 must be in range [0, 31]"
+	VSSRAVI		$-1, V2, V3			// ERROR "signed immediate -1 must be in range [0, 31]"
+	VNCLIPUWV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VNCLIPUWX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VNCLIPUWI	$32, V2, V3			// ERROR "signed immediate 32 must be in range [0, 31]"
+	VNCLIPUWI	$-1, V2, V3			// ERROR "signed immediate -1 must be in range [0, 31]"
+	VNCLIPWV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VNCLIPWX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VNCLIPWI	$32, V2, V3			// ERROR "signed immediate 32 must be in range [0, 31]"
+	VNCLIPWI	$-1, V2, V3			// ERROR "signed immediate -1 must be in range [0, 31]"
+	VFADDVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFADDVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFSUBVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFSUBVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFRSUBVF	X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFWADDVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFWADDVF	X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFWSUBVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFWSUBVF	X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFWADDWV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFWADDWF	X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFWSUBWV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFWSUBWF	X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFMULVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFMULVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFDIVVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFDIVVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFRDIVVF	X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFWMULVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFWMULVF	X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFMACCVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFMACCVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFNMACCVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFNMACCVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFMSACVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFMSACVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFNMSACVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFNMSACVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFMADDVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFMADDVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFNMADDVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFNMADDVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFMSUBVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFMSUBVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFNMSUBVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFNMSUBVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFWMACCVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFWMACCVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFWNMACCVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFWNMACCVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFWMSACVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFWMSACVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFWNMSACVV	V2, X10, V3			// ERROR "expected vector register in vs1 position"
+	VFWNMSACVF	V2, X10, V3			// ERROR "expected float register in rs1 position"
+	VFSQRTV		X10, V3				// ERROR "expected vector register in vs2 position"
+	VFRSQRT7V	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFREC7V		X10, V3				// ERROR "expected vector register in vs2 position"
+	VFMINVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFMINVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFMAXVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFMAXVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFSGNJVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFSGNJVF	X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFSGNJNVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFSGNJNVF	X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFSGNJXVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFSGNJXVF	X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VFNEGV		V2, X10				// ERROR "expected vector register in vd position"
+	VFABSV		V2, X10				// ERROR "expected vector register in vd position"
+	VMFEQVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMFEQVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VMFNEVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMFNEVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VMFLTVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMFLTVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VMFLEVV		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMFLEVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VMFGTVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VMFGEVF		X10, V2, V3			// ERROR "expected float register in rs1 position"
+	VMFGTVV		X10, V2, V3			// ERROR "expected vector register in vs2 position"
+	VMFGEVV		X10, V2, V3			// ERROR "expected vector register in vs2 position"
+	VFCLASSV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFMERGEVFM	X10, V2, V0, V3			// ERROR "expected float register in rs1 position"
+	VFMVVF		X10, V3				// ERROR "expected float register in rs1 position"
+	VFCVTXUFV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFCVTXFV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFCVTRTZXUFV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFCVTRTZXFV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFCVTFXUV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFCVTFXV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFWCVTXUFV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFWCVTXFV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFWCVTRTZXUFV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFWCVTRTZXFV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFWCVTFXUV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFWCVTFXV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFWCVTFFV	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFNCVTXUFW	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFNCVTXFW	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFNCVTRTZXUFW	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFNCVTRTZXFW	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFNCVTFXUW	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFNCVTFXW	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFNCVTFFW	X10, V3				// ERROR "expected vector register in vs2 position"
+	VFNCVTRODFFW	X10, V3				// ERROR "expected vector register in vs2 position"
+	VREDSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VREDMAXUVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VREDMAXVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VREDMINUVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VREDMINVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VREDANDVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VREDORVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VREDXORVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWREDSUMUVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VWREDSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFREDOSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFREDUSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFREDMAXVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFREDMINVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFWREDOSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VFWREDUSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMANDMM		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMNANDMM	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMANDNMM	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMXORMM		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMORMM		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMNORMM		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMORNMM		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMXNORMM	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMMVM		V3, X10				// ERROR "expected vector register in vd position"
+	VMNOTM		V3, X10				// ERROR "expected vector register in vd position"
+	VCPOPM		V2, V1				// ERROR "expected integer register in rd position"
+	VCPOPM		X11, X10			// ERROR "expected vector register in vs2 position"
+	VFIRSTM		V2, V1				// ERROR "expected integer register in rd position"
+	VFIRSTM		X11, X10			// ERROR "expected vector register in vs2 position"
+	VMSBFM		X10, V3				// ERROR "expected vector register in vs2 position"
+	VMSIFM		X10, V3				// ERROR "expected vector register in vs2 position"
+	VMSOFM		X10, V3				// ERROR "expected vector register in vs2 position"
+	VIOTAM		X10, V3				// ERROR "expected vector register in vs2 position"
+	VIDV		X10				// ERROR "expected vector register in vd position"
+	VMVXS		X11, X10			// ERROR "expected vector register in vs2 position"
+	VMVXS		V2, V1				// ERROR "expected integer register in rd position"
+	VMVSX		X11, X10			// ERROR "expected vector register in vd position"
+	VMVSX		V2, V1				// ERROR "expected integer register in rs2 position"
+	VFMVFS		X10, F10			// ERROR "expected vector register in vs2 position"
+	VFMVFS		V2, V1				// ERROR "expected float register in rd position"
+	VFMVSF		X10, V2				// ERROR "expected float register in rs2 position"
+	VFMVSF		V2, V1				// ERROR "expected float register in rs2 position"
+	VSLIDEUPVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VSLIDEUPVI	$-1, V2, V3			// ERROR "unsigned immediate -1 must be in range [0, 31]"
+	VSLIDEUPVI	$32, V2, V3			// ERROR "unsigned immediate 32 must be in range [0, 31]"
+	VSLIDEDOWNVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VSLIDEDOWNVI	$-1, V2, V3			// ERROR "unsigned immediate -1 must be in range [0, 31]"
+	VSLIDEDOWNVI	$32, V2, V3			// ERROR "unsigned immediate 32 must be in range [0, 31]"
+	VSLIDE1UPVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VFSLIDE1UPVF	V1, V2, V3			// ERROR "expected float register in rs1 position"
+	VSLIDE1DOWNVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VFSLIDE1DOWNVF	V1, V2, V3			// ERROR "expected float register in rs1 position"
+	VRGATHERVV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VRGATHEREI16VV	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VRGATHERVX	V1, V2, V3			// ERROR "expected integer register in rs1 position"
+	VRGATHERVI	$-1, V2, V3			// ERROR "unsigned immediate -1 must be in range [0, 31]"
+	VRGATHERVI	$32, V2, V3			// ERROR "unsigned immediate 32 must be in range [0, 31]"
+	VCOMPRESSVM	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMV1RV		X10, V1				// ERROR "expected vector register in vs2 position"
+	VMV2RV		X10, V10			// ERROR "expected vector register in vs2 position"
+	VMV4RV		X10, V4				// ERROR "expected vector register in vs2 position"
+	VMV8RV		X10, V0				// ERROR "expected vector register in vs2 position"
+
+	RET

src/cmd/asm/internal/asm/testdata/s390x.s

@@ -401,6 +401,7 @@ TEXT main·foo(SB),DUPOK|NOSPLIT,$16-0 // TEXT main.foo(SB), DUPOK|NOSPLIT, $16-
 	FMADDS	F1, F2, F3             // b30e3012
 	FMSUB	F4, F5, F5             // b31f5045
 	FMSUBS	F6, F6, F7             // b30f7066
+	LCDBR	F0, F2                 // b3130020
 	LPDFR	F1, F2                 // b3700021
 	LNDFR	F3, F4                 // b3710043
 	CPSDR	F5, F6, F7             // b3725076
@@ -420,8 +421,8 @@ TEXT main·foo(SB),DUPOK|NOSPLIT,$16-0 // TEXT main.foo(SB), DUPOK|NOSPLIT, $16-
 	KLMD	R2, R8                 // b93f0028
 	KIMD	R0, R4                 // b93e0004
 	KDSA	R0, R8                 // b93a0008
-	KMA	R2, R6, R4              // b9296024
-	KMCTR   R2, R6, R4              // b92d6024
+	KMA	R2, R6, R4             // b9296024
+	KMCTR   R2, R6, R4             // b92d6024
 
 	// vector add and sub instructions
 	VAB	V3, V4, V4              // e743400000f3

src/cmd/asm/main.go

@@ -49,6 +49,7 @@ func main() {
 	ctxt.Debugpcln = flags.DebugFlags.PCTab
 	ctxt.IsAsm = true
 	ctxt.Pkgpath = *flags.Importpath
+	ctxt.DwTextCount = objabi.DummyDwarfFunctionCountForAssembler()
 	switch *flags.Spectre {
 	default:
 		log.Printf("unknown setting -spectre=%s", *flags.Spectre)

src/cmd/cgo/gcc.go

@@ -2863,7 +2863,7 @@ func (c *typeConv) loadType(dtype dwarf.Type, pos token.Pos, parent string) *Typ
 			if ss, ok := dwarfToName[s]; ok {
 				s = ss
 			}
-			s = strings.Replace(s, " ", "", -1)
+			s = strings.ReplaceAll(s, " ", "")
 			name := c.Ident("_Ctype_" + s)
 			tt := *t
 			typedef[name.Name] = &tt

src/cmd/cgo/internal/swig/swig_test.go

@@ -40,8 +40,9 @@ func TestCallback(t *testing.T) {
 }
 
 func run(t *testing.T, dir string, lto bool, args ...string) {
+	testenv.MustHaveGoRun(t)
 	runArgs := append([]string{"run", "."}, args...)
-	cmd := exec.Command("go", runArgs...)
+	cmd := exec.Command(testenv.GoToolPath(t), runArgs...)
 	cmd.Dir = dir
 	if lto {
 		// On the builders we're using the default /usr/bin/ld, but
@@ -68,7 +69,7 @@ func run(t *testing.T, dir string, lto bool, args ...string) {
 
 func mustHaveCxx(t *testing.T) {
 	// Ask the go tool for the CXX it's configured to use.
-	cxx, err := exec.Command("go", "env", "CXX").CombinedOutput()
+	cxx, err := exec.Command(testenv.GoToolPath(t), "env", "CXX").CombinedOutput()
 	if err != nil {
 		t.Fatalf("go env CXX failed: %s", err)
 	}

src/cmd/cgo/internal/test/issue18146.go

@@ -11,6 +11,7 @@ package cgotest
 import (
 	"bytes"
 	"crypto/md5"
+	"internal/testenv"
 	"os"
 	"os/exec"
 	"runtime"
@@ -73,7 +74,7 @@ func test18146(t *testing.T) {
 		}
 		runtime.GOMAXPROCS(threads)
 		argv := append(os.Args, "-test.run=^$")
-		if err := syscall.Exec(os.Args[0], argv, os.Environ()); err != nil {
+		if err := syscall.Exec(testenv.Executable(t), argv, os.Environ()); err != nil {
 			t.Fatal(err)
 		}
 	}
@@ -87,7 +88,7 @@ func test18146(t *testing.T) {
 
 	args := append(append([]string(nil), os.Args[1:]...), "-test.run=^Test18146$")
 	for n := attempts; n > 0; n-- {
-		cmd := exec.Command(os.Args[0], args...)
+		cmd := exec.Command(testenv.Executable(t), args...)
 		cmd.Env = append(os.Environ(), "test18146=exec")
 		buf := bytes.NewBuffer(nil)
 		cmd.Stdout = buf

src/cmd/cgo/internal/test/issue4029.go

@@ -11,6 +11,7 @@ package cgotest
 
 /*
 #include <stdint.h>
+#include <stdlib.h>
 #include <dlfcn.h>
 #cgo linux LDFLAGS: -ldl
 
@@ -24,6 +25,7 @@ import "C"
 
 import (
 	"testing"
+	"unsafe"
 )
 
 var callbacks int
@@ -66,7 +68,9 @@ func loadThySelf(t *testing.T, symbol string) {
 	}
 	defer C.dlclose4029(this_process)
 
-	symbol_address := C.dlsym4029(this_process, C.CString(symbol))
+	symCStr := C.CString(symbol)
+	defer C.free(unsafe.Pointer(symCStr))
+	symbol_address := C.dlsym4029(this_process, symCStr)
 	if symbol_address == 0 {
 		t.Error("dlsym:", C.GoString(C.dlerror()))
 		return

src/cmd/cgo/internal/test/issue42018_windows.go

@@ -27,6 +27,7 @@ func test42018(t *testing.T) {
 	recurseHWND(400, hwnd, uintptr(unsafe.Pointer(&i)))
 }
 
+//go:noinline
 func recurseHANDLE(n int, p C.HANDLE, v uintptr) {
 	if n > 0 {
 		recurseHANDLE(n-1, p, v)
@@ -36,6 +37,7 @@ func recurseHANDLE(n int, p C.HANDLE, v uintptr) {
 	}
 }
 
+//go:noinline
 func recurseHWND(n int, p C.HWND, v uintptr) {
 	if n > 0 {
 		recurseHWND(n-1, p, v)

src/cmd/cgo/internal/test/test.go

@@ -1098,6 +1098,7 @@ func testErrno(t *testing.T) {
 func testMultipleAssign(t *testing.T) {
 	p := C.CString("234")
 	n, m := C.strtol(p, nil, 345), C.strtol(p, nil, 10)
+	defer C.free(unsafe.Pointer(p))
 	if runtime.GOOS == "openbsd" {
 		// Bug in OpenBSD strtol(3) - base > 36 succeeds.
 		if (n != 0 && n != 239089) || m != 234 {
@@ -1106,7 +1107,6 @@ func testMultipleAssign(t *testing.T) {
 	} else if n != 0 || m != 234 {
 		t.Fatal("Strtol x2: ", n, m)
 	}
-	C.free(unsafe.Pointer(p))
 }
 
 var (
@@ -1632,7 +1632,9 @@ func testNaming(t *testing.T) {
 
 func test6907(t *testing.T) {
 	want := "yarn"
-	if got := C.GoString(C.Issue6907CopyString(want)); got != want {
+	s := C.Issue6907CopyString(want)
+	defer C.free(unsafe.Pointer(s))
+	if got := C.GoString(s); got != want {
 		t.Errorf("C.GoString(C.Issue6907CopyString(%q)) == %q, want %q", want, got, want)
 	}
 }
@@ -1881,6 +1883,7 @@ func test17537(t *testing.T) {
 	}
 
 	p := (*C.char)(C.malloc(1))
+	defer C.free(unsafe.Pointer(p))
 	*p = 17
 	if got, want := C.F17537(&p), C.int(17); got != want {
 		t.Errorf("got %d, want %d", got, want)

src/cmd/cgo/internal/testcarchive/carchive_test.go

@@ -218,7 +218,7 @@ func genHeader(t *testing.T, header, dir string) {
 		t.Fatal(err)
 	}
 
-	cmd := exec.Command("go", "tool", "cgo",
+	cmd := exec.Command(testenv.GoToolPath(t), "tool", "cgo",
 		"-objdir", objDir,
 		"-exportheader", header)
 	cmd.Args = append(cmd.Args, files...)
@@ -524,7 +524,7 @@ func TestEarlySignalHandler(t *testing.T) {
 		}()
 	}
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-o", "libgo2.a", "./libgo2")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-o", "libgo2.a", "./libgo2")
 	if out, err := cmd.CombinedOutput(); err != nil {
 		t.Logf("%s", out)
 		t.Fatal(err)
@@ -674,7 +674,7 @@ func buildSignalForwardingTest(t *testing.T) {
 	}
 
 	t.Log("go build -buildmode=c-archive -o libgo2.a ./libgo2")
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-o", "libgo2.a", "./libgo2")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-o", "libgo2.a", "./libgo2")
 	out, err := cmd.CombinedOutput()
 	if len(out) > 0 {
 		t.Logf("%s", out)
@@ -801,7 +801,7 @@ func TestOsSignal(t *testing.T) {
 		}()
 	}
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-o", "libgo3.a", "./libgo3")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-o", "libgo3.a", "./libgo3")
 	if out, err := cmd.CombinedOutput(); err != nil {
 		t.Logf("%s", out)
 		t.Fatal(err)
@@ -843,7 +843,7 @@ func TestSigaltstack(t *testing.T) {
 		}()
 	}
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-o", "libgo4.a", "./libgo4")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-o", "libgo4.a", "./libgo4")
 	if out, err := cmd.CombinedOutput(); err != nil {
 		t.Logf("%s", out)
 		t.Fatal(err)
@@ -908,7 +908,7 @@ func TestExtar(t *testing.T) {
 		t.Fatal(err)
 	}
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-ldflags=-extar="+filepath.Join(dir, "testar"), "-o", "libgo4.a", "./libgo4")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-ldflags=-extar="+filepath.Join(dir, "testar"), "-o", "libgo4.a", "./libgo4")
 	if out, err := cmd.CombinedOutput(); err != nil {
 		t.Logf("%s", out)
 		t.Fatal(err)
@@ -955,7 +955,7 @@ func TestPIE(t *testing.T) {
 	// be running this test in a GOROOT owned by root.)
 	genHeader(t, "p.h", "./p")
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "./libgo")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "./libgo")
 	if out, err := cmd.CombinedOutput(); err != nil {
 		t.Logf("%s", out)
 		t.Fatal(err)
@@ -1042,7 +1042,7 @@ func TestSIGPROF(t *testing.T) {
 		}()
 	}
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-o", "libgo6.a", "./libgo6")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-o", "libgo6.a", "./libgo6")
 	out, err := cmd.CombinedOutput()
 	t.Logf("%v\n%s", cmd.Args, out)
 	if err != nil {
@@ -1089,7 +1089,7 @@ func TestCompileWithoutShared(t *testing.T) {
 		}()
 	}
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-gcflags=-shared=false", "-o", "libgo2.a", "./libgo2")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-gcflags=-shared=false", "-o", "libgo2.a", "./libgo2")
 	out, err := cmd.CombinedOutput()
 	t.Logf("%v\n%s", cmd.Args, out)
 	if err != nil {
@@ -1204,7 +1204,7 @@ func TestManyCalls(t *testing.T) {
 		}()
 	}
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-o", "libgo7.a", "./libgo7")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-o", "libgo7.a", "./libgo7")
 	out, err := cmd.CombinedOutput()
 	t.Logf("%v\n%s", cmd.Args, out)
 	if err != nil {
@@ -1259,7 +1259,7 @@ func TestPreemption(t *testing.T) {
 		}()
 	}
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-o", "libgo8.a", "./libgo8")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-o", "libgo8.a", "./libgo8")
 	out, err := cmd.CombinedOutput()
 	t.Logf("%v\n%s", cmd.Args, out)
 	if err != nil {
@@ -1309,7 +1309,7 @@ func TestDeepStack(t *testing.T) {
 		}()
 	}
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-o", "libgo9.a", "./libgo9")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-o", "libgo9.a", "./libgo9")
 	out, err := cmd.CombinedOutput()
 	t.Logf("%v\n%s", cmd.Args, out)
 	if err != nil {
@@ -1372,7 +1372,7 @@ func BenchmarkCgoCallbackMainThread(b *testing.B) {
 		}()
 	}
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-o", "libgo10.a", "./libgo10")
+	cmd := exec.Command(testenv.GoToolPath(b), "build", "-buildmode=c-archive", "-o", "libgo10.a", "./libgo10")
 	out, err := cmd.CombinedOutput()
 	b.Logf("%v\n%s", cmd.Args, out)
 	if err != nil {
@@ -1414,7 +1414,7 @@ func TestSharedObject(t *testing.T) {
 		}()
 	}
 
-	cmd := exec.Command("go", "build", "-buildmode=c-archive", "-o", "libgo_s.a", "./libgo")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-buildmode=c-archive", "-o", "libgo_s.a", "./libgo")
 	out, err := cmd.CombinedOutput()
 	t.Logf("%v\n%s", cmd.Args, out)
 	if err != nil {

src/cmd/cgo/internal/testcshared/cshared_test.go

@@ -407,7 +407,7 @@ func main() {
 		argv = append(argv, "-ldflags", "-extldflags=-Wl,--export-all-symbols")
 	}
 	argv = append(argv, "-o", objfile, srcfile)
-	out, err := exec.Command("go", argv...).CombinedOutput()
+	out, err := exec.Command(testenv.GoToolPath(t), argv...).CombinedOutput()
 	if err != nil {
 		t.Fatalf("build failure: %s\n%s\n", err, string(out))
 	}
@@ -880,3 +880,44 @@ func TestIssue36233(t *testing.T) {
 		t.Error("missing functions")
 	}
 }
+
+func TestIssue68411(t *testing.T) {
+	globalSkip(t)
+	testenv.MustHaveCGO(t)
+
+	t.Parallel()
+
+	// Test that the export header uses a void function parameter for
+	// exported Go functions with no parameters.
+
+	tmpdir := t.TempDir()
+
+	const exportHeader = "issue68411.h"
+
+	run(t, nil, "go", "tool", "cgo", "-exportheader", exportHeader, "-objdir", tmpdir, "./issue68411/issue68411.go")
+	data, err := os.ReadFile(exportHeader)
+	if err != nil {
+		t.Fatal(err)
+	}
+
+	funcs := []struct{ name, signature string }{
+		{"exportFuncWithNoParams", "void exportFuncWithNoParams(void)"},
+		{"exportFuncWithParams", "exportFuncWithParams(GoInt a, GoInt b)"},
+	}
+
+	var found int
+	for line := range bytes.Lines(data) {
+		for _, fn := range funcs {
+			if bytes.Contains(line, []byte(fn.name)) {
+				found++
+				if !bytes.Contains(line, []byte(fn.signature)) {
+					t.Errorf("function signature mismatch; got %q, want %q", line, fn.signature)
+				}
+			}
+		}
+	}
+
+	if found != len(funcs) {
+		t.Error("missing functions")
+	}
+}

src/cmd/cgo/internal/testcshared/testdata/issue68411/issue68411.go

@@ -0,0 +1,15 @@
+// Copyright 2025 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package main
+
+import "C"
+
+//export exportFuncWithNoParams
+func exportFuncWithNoParams() {}
+
+//export exportFuncWithParams
+func exportFuncWithParams(a, b int) {}
+
+func main() {}

src/cmd/cgo/internal/testerrors/argposition_test.go

@@ -81,7 +81,7 @@ func TestArgumentsPositions(t *testing.T) {
 		t.Fatal(err)
 	}
 
-	cmd := exec.Command("go", "tool", "cgo",
+	cmd := exec.Command(testenv.GoToolPath(t), "tool", "cgo",
 		"-srcdir", testdata,
 		"-objdir", dir,
 		"issue42580.go")

src/cmd/cgo/internal/testerrors/badsym_test.go

@@ -136,7 +136,7 @@ func TestBadSymbol(t *testing.T) {
 	makeFile(godir, "go.mod", "module badsym")
 
 	// Try to build our little package.
-	cmd := exec.Command("go", "build", "-ldflags=-v")
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-ldflags=-v")
 	cmd.Dir = godir
 	output, err := cmd.CombinedOutput()
 

src/cmd/cgo/internal/testerrors/errors_test.go

@@ -76,7 +76,7 @@ func expect(t *testing.T, errors []*regexp.Regexp, files ...string) {
 	for _, file := range files {
 		args = append(args, path(file))
 	}
-	cmd := exec.Command("go", args...)
+	cmd := exec.Command(testenv.GoToolPath(t), args...)
 	out, err := cmd.CombinedOutput()
 	if err == nil {
 		t.Errorf("expected cgo to fail but it succeeded")
@@ -105,10 +105,10 @@ func expect(t *testing.T, errors []*regexp.Regexp, files ...string) {
 func sizeofLongDouble(t *testing.T) int {
 	testenv.MustHaveGoRun(t)
 	testenv.MustHaveCGO(t)
-	cmd := exec.Command("go", "run", path("long_double_size.go"))
+	cmd := exec.Command(testenv.GoToolPath(t), "run", path("long_double_size.go"))
 	out, err := cmd.CombinedOutput()
 	if err != nil {
-		t.Fatalf("%#q: %v:\n%s", strings.Join(cmd.Args, " "), err, out)
+		t.Fatalf("%#q: %v:\n%s", cmd, err, out)
 	}
 
 	i, err := strconv.Atoi(strings.TrimSpace(string(out)))
@@ -158,11 +158,11 @@ func TestToleratesOptimizationFlag(t *testing.T) {
 			testenv.MustHaveCGO(t)
 			t.Parallel()
 
-			cmd := exec.Command("go", "build", path("issue14669.go"))
+			cmd := exec.Command(testenv.GoToolPath(t), "build", path("issue14669.go"))
 			cmd.Env = append(os.Environ(), "CGO_CFLAGS="+cflags)
 			out, err := cmd.CombinedOutput()
 			if err != nil {
-				t.Errorf("%#q: %v:\n%s", strings.Join(cmd.Args, " "), err, out)
+				t.Errorf("%#q: %v:\n%s", cmd, err, out)
 			}
 		})
 	}
@@ -173,10 +173,10 @@ func TestMallocCrashesOnNil(t *testing.T) {
 	testenv.MustHaveGoRun(t)
 	t.Parallel()
 
-	cmd := exec.Command("go", "run", path("malloc.go"))
+	cmd := exec.Command(testenv.GoToolPath(t), "run", path("malloc.go"))
 	out, err := cmd.CombinedOutput()
 	if err == nil {
-		t.Logf("%#q:\n%s", strings.Join(cmd.Args, " "), out)
+		t.Logf("%#q:\n%s", cmd, out)
 		t.Fatalf("succeeded unexpectedly")
 	}
 }

src/cmd/cgo/internal/testerrors/ptr_test.go

@@ -609,7 +609,7 @@ func buildPtrTests(t *testing.T, gopath string, cgocheck2 bool) (exe string) {
 	if cgocheck2 {
 		exeName = "ptrtest2.exe"
 	}
-	cmd := exec.Command("go", "build", "-o", exeName)
+	cmd := exec.Command(testenv.GoToolPath(t), "build", "-o", exeName)
 	cmd.Dir = src
 	cmd.Env = append(os.Environ(), "GOPATH="+gopath)
 

src/cmd/cgo/internal/testfortran/fortran_test.go

@@ -75,7 +75,7 @@ func TestFortran(t *testing.T) {
 	// Finally, run the actual test.
 	t.Log("go", "run", "./testdata/testprog")
 	var stdout, stderr strings.Builder
-	cmd := exec.Command("go", "run", "./testdata/testprog")
+	cmd := exec.Command(testenv.GoToolPath(t), "run", "./testdata/testprog")
 	cmd.Stdout = &stdout
 	cmd.Stderr = &stderr
 	err := cmd.Run()

src/cmd/cgo/internal/testgodefs/testgodefs_test.go

@@ -51,7 +51,7 @@ func TestGoDefs(t *testing.T) {
 	}
 
 	for _, fp := range filePrefixes {
-		cmd := exec.Command("go", "tool", "cgo",
+		cmd := exec.Command(testenv.GoToolPath(t), "tool", "cgo",
 			"-godefs",
 			"-srcdir", testdata,
 			"-objdir", dir,
@@ -60,7 +60,7 @@ func TestGoDefs(t *testing.T) {
 
 		out, err := cmd.Output()
 		if err != nil {
-			t.Fatalf("%s: %v\n%s", strings.Join(cmd.Args, " "), err, cmd.Stderr)
+			t.Fatalf("%#q: %v\n%s", cmd, err, cmd.Stderr)
 		}
 
 		fn := fp + "_defs.go"
@@ -107,10 +107,10 @@ func TestGoDefs(t *testing.T) {
 	// instead of invoking 'go build' and the resulting binary separately, so that
 	// this test can pass on mobile builders, which do not copy artifacts back
 	// from remote invocations.
-	cmd := exec.Command("go", "run", ".")
+	cmd := exec.Command(testenv.GoToolPath(t), "run", ".")
 	cmd.Env = append(os.Environ(), "GOPATH="+gopath)
 	cmd.Dir = dir
 	if out, err := cmd.CombinedOutput(); err != nil {
-		t.Fatalf("%s [%s]: %v\n%s", strings.Join(cmd.Args, " "), dir, err, out)
+		t.Fatalf("%#q [%s]: %v\n%s", cmd, dir, err, out)
 	}
 }

src/cmd/cgo/internal/testlife/life_test.go

@@ -50,7 +50,7 @@ func TestTestRun(t *testing.T) {
 	testenv.MustHaveGoRun(t)
 	testenv.MustHaveCGO(t)
 
-	cmd := exec.Command("go", "run", "main.go")
+	cmd := exec.Command(testenv.GoToolPath(t), "run", "main.go")
 	got, err := cmd.CombinedOutput()
 	if err != nil {
 		t.Fatalf("%v: %s\n%s", cmd, err, got)

src/cmd/cgo/internal/testplugin/plugin_test.go

@@ -145,8 +145,8 @@ func goCmd(t *testing.T, op string, args ...string) string {
 
 // escape converts a string to something suitable for a shell command line.
 func escape(s string) string {
-	s = strings.Replace(s, "\\", "\\\\", -1)
-	s = strings.Replace(s, "'", "\\'", -1)
+	s = strings.ReplaceAll(s, "\\", "\\\\")
+	s = strings.ReplaceAll(s, "'", "\\'")
 	// Conservative guess at characters that will force quoting
 	if s == "" || strings.ContainsAny(s, "\\ ;#*&$~?!|[]()<>{}`") {
 		s = "'" + s + "'"
@@ -194,10 +194,10 @@ func run(t *testing.T, bin string, args ...string) string {
 	out, err := cmd.Output()
 	if err != nil {
 		if t == nil {
-			log.Panicf("%s: %v\n%s", strings.Join(cmd.Args, " "), err, cmd.Stderr)
+			log.Panicf("%#q: %v\n%s", cmd, err, cmd.Stderr)
 		} else {
 			t.Helper()
-			t.Fatalf("%s: %v\n%s", strings.Join(cmd.Args, " "), err, cmd.Stderr)
+			t.Fatalf("%#q: %v\n%s", cmd, err, cmd.Stderr)
 		}
 	}
 
@@ -245,7 +245,7 @@ func TestIssue18676(t *testing.T) {
 	cmd := exec.CommandContext(ctx, "./issue18676.exe")
 	out, err := cmd.CombinedOutput()
 	if err != nil {
-		t.Fatalf("%s: %v\n%s", strings.Join(cmd.Args, " "), err, out)
+		t.Fatalf("%#q: %v\n%s", cmd, err, out)
 	}
 }